United States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,726,479
`
`Matsumoto et a].
`
`[45] Date of Patent:
`
`Mar. 10, 1998
`
`U8005726479A
`
`[54] SEMICONDUCTOR DEVICE HAVING
`POLYSILICON ELECTRODE
`MINIMIZATION RESULTING IN A SMALL
`RESISTANCE VALUE
`
`[75]
`
`Inventors: Michikazn Matsnmoto. Osaka;
`Minoru Fujii. Hyogo; Toshlki Yabu.
`Osaka. all of Japan
`
`[73] Assignee: Matsushita Electric Industrial Co.,
`Ltd.. Osaka. Japan
`
`[21] Appl. No.: 584,123
`
`[22]
`
`Filed:
`
`Jan. 11, 1996
`
`Foreign Application Priority Data
`[30]
`Jan. 12, 1995
`[JP]
`Japan
`Jun. 30, 1995
`[JP]
`Japan
`Int. CL6 ............................. H01L 29/76; H01L 29/94
`[51]
`[52] U.S. Cl. .......................... 257/412; 257/344; 257/413;
`257/383; 257/384; 257/388; 257/903; 437/41;
`437/44; 437/913
`[58] Field of Search ..................................... 257/383. 384.
`257/412. 413. 344. 903; 437/41. 44. 913
`
`7—003012
`7-164976
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,102,733
`4,374,700
`4,321,085
`4,912,061
`
`............. 257/413
`7/1978 De La Moneda et a].
`.. 257/377
`2/1983 Scott et al.
`................
`
`.. 257/412
`4/1989 Haken et a1.
`3/1990 Nasr ........................................ 257/413
`
`4,994,873
`2/1991 Marian .................................... 257/903
`5,234,850
`8/1993 Liao ........................ 257/344
`
`
`5,241,207
`8/1993 Toyoshima et al.
`257/334
`5,256,894 10/1993 Shino ...................................... 257/388
`5,397,722
`3/1995 Bashiretal..
`
`FOREIGN PATENT DOCUMENTS
`
`4—48657
`5—136398
`5-112219
`
`2/1992
`6/1993
`4/1994
`
`Japan .
`Japan .
`Japan .
`
`Primary Examiner—Valencia Martin Wallace
`Attomey, Agent, or Firm—McDermott. Will & Emery
`
`[57]
`
`ABSTRACT
`
`A polysilicon electrode is formed in an active area sur-
`rounded by an isolation on a silicon substrate with a gate
`oxide film sandwiched therebetween. a polysilicon wire is
`formed on the isolation. and a source/drain region is formed
`on both sides of the polysilicon electrode. On the both sides
`of a polysilicon film constituting the electrode and the wire
`are formed side walls having a height that is 4/5 or less of the
`height of the polysilioon film. Furthermore. the polysilicon
`film is provided with a silicide layer in contact with the top
`surface and portions of the side surfaces of the polysilioon
`film projecting from the side walls. and another silicide layer
`is formed in contact With the source/drain region. Since the
`sectional area of the silicide layer is increased. the resistance
`value can be suppressed even when the dimension of the
`polysilicon film is minimized. Thus. the invention provides
`a semiconductor device including an FET having a low
`resistance value applicable to a refined pattern.
`
`18 Claims, 23 Drawing Sheets
`
`90
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`TSMC 1017
`TSMC 1017
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`

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`US. Patent
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`Mar. 10, 1998
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`Sheet 1 of 23
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`5,726,479
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`US. Patent
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`Mar. 10, 1998
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`Sheet 2 of 23
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`US. Patent
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`Mar. 10, 1998
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`U.S. Patent
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`Mar. 10, 1998
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`US. Patent
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`‘ Mar. 10, 1993
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`Sheet 5 of 23
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`US. Patent
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`Mar. 10, 1998
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`Sheet 6 of 23
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`US. Patent
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`Mar. 10, 1998
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`US. Patent
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`Mar. 10, 1998
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`Sheet 9 of 23
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`Fig.9
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`US. Patent
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`Mar. 10, 1998
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`Sheet 10 of 23
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`US. Patent
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`Mar. 10, 1998
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`Sheet 11 of 23
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`US. Patent
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`Mar. 10, 1998
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`US. Patent
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`Mar. 10, 1998
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`US. Patent
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`Mar.10, 1998
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`Sheet 14 of 23
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`US. Patent
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`Mar. 10, 1998
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`Sheet 15 of 23
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`US. Patent
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`Mar. 10, 1998
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`Sheet 16 of 23
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`Mar. 10, 1998
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`US. Patent
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`Mar. 10, 1998
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`Sheet 18 of 23
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`US. Patent
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`Mar. 10, 1998
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`Sheet 19 of 23
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`US. Patent
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`Mar. 10, 1993
`
`Sheet 20 of 23
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`US. Patent
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`Mar. 10, 1998
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`Sheet 21 of 23
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`US. Patent
`
`Mar. 10, 1998
`
`Sheet 22 of 23
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`5,726,479
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`PRIOR ART
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`US. Patent
`
`Mar. 10, 1998
`
`Sheet 23 of 23
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`5,726,479
`
`Fig.23t0)
`PRIOR ART
`
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`

`1
`SEMICONDUCTOR DEVICE HAVING
`POLYSILICON ELECTRODE
`MINIMIZATION RESULTING IN A SMALL
`RESISTANCE VALUE
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a semiconductor device
`mounting an FEI' having a silicidated electrode and a
`production method for the semiconductor device. and more
`particularly. it relates to decrease of a resistance value in the
`semiconductor device.
`
`Recently. elements used in the field of VLSI have become
`more and more minimized and refined. and have attained a
`higher speed operation with smaller power consumption. In
`order to achieve such properties of the elements. resistance
`of a polysilicon electrode. a polysilicon wire and a source/
`drain difiused layer of a MOS transistor is reduced so as to
`reduce the capacity of the source/drain diffused layer in the
`production procedure of a VLSI circuit. One of known
`techniques for decreasing resistance of a polysilicon gate
`electrode and a source/drain region or resistance of a poly-
`silicon wire of a MOS transistor is designated as a silicide
`process using silicide. that is. a compound of silicon and a
`metal. A semiconductor device produced through this
`cide process can realize. owing to the decrease of the
`resistance of a source/drain region. a minimized area of the
`source/drain region. decrease of the parasitic capacity of the
`source/drain region and a high speed operation of the
`resultant VLSI circuit.
`
`As an example of the silicide process. a so—called salicide
`(self aligned silicide) process has been developed. In the
`salicide process. a MOS transistor has a structure including
`a gate electrode composed of a lower polysilicon electrode
`and an upper silicide layer. and another silicide layer in
`contact with a source/drain region. In the production of such
`a MOS transistor. the polysilicon electrode and the source!
`drain region are simultaneously silicidated. Therefore. in the
`salicide process.
`the gate electrode and the source/drain
`region can be silicidated in one and the same step. and
`hence. the number of required steps and the production cost
`can be reduced. Because of these advantages. the salicide
`process is regarded to be a useful process for refining an
`element. and more and more studies and developments have
`been made on this process.
`Now. a conventional salicide structure and the conven—
`tional salicide process will be described referring to FIGS.
`22 and 23(a) through 230‘).
`FIG. 22 shows an exemplified sectional structure of a
`MOS transistor having the conventional salicide structure.
`In the MOS transistor of FIG. 22. respective reference
`numerals are used to refer to the following elements: A
`reference numeral 1 denotes a silicon substrate. A reference
`numeral 2 denotes an isolation provided for surrounding and
`electrically separating active areas of respective MOS tran—
`sistors formed on the semiconductor substrate 1 from one
`
`another. Areference numeral 3 denotes a gate oxide film. A
`reference numeral 4a denotes a polysilicon electrode formed
`on the active area and functioning as a gate. and a reference
`numeral 4b denotes a polysilicon wire formed on the isola—
`tion 2 and functioning as a wire. Both the polysilicon
`electrode 4a and the polysilicon wire 4b are formed out of
`polysilicon films simultaneously deposited. A reference
`numeral 5 denotes a protection oxide film for protecting the
`polysilicon electrode 4a and the like. A reference numeral 6
`denotes a low concentration source/drain region formed by
`doping with an impurity at a low concentration for relaxing
`
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`a local electric field during the operation of the transistor so
`as to improve its reliability. A reference numeral 7 denotes
`a side wall. which is used as a mask for ion injection in
`forming a high concentration source/drain region when a
`so—called LDD structure is adopted. A reference numeral 8
`denotes a high concentration source/drain region formed by
`doping with an impurity at a high concentration. The high
`concentration source/drain region 8 corresponds to an
`n+region where. for example. As or the like is injected. in an
`N-channel transistor. and corresponds to a p+region. where
`BF2 or the like is injected. in a P-channel transistor. A
`reference numeral 9a denotes an electrode silicide film
`formed on the polysilicon electrode 4a. a reference numeral
`9b denotes a wire silicide layer formed on the polysilicon
`wire 4b. and a reference numeral 9c denotes a substrate
`silicide layer formed on the high concentration source/drain
`region 8. The silicide layers 90 through 9c are simulta-
`neously formed by silicidating portions close to the surfaces
`of the polysilicon electrode 4a. the polysilicon wire 4b and
`the high concentration source/drain region 8 in the salicide
`process. A typical silicide material can be TiSiz. and other
`examples of the material include CoSiz. NiSi. WSi and
`PtSiz.
`In the semiconductor device having the structure as
`shown in FIG. 22. the resistance values of the polysilicon
`electrode 40. the polysilicon wire 4b and the high concen-
`tration source/drain region 8 can be suppressed because of
`the silicide layers 9a through 9c respectively formed in
`contact with these elements. In a semiconductor device. for
`example. comprising a polysilicon electrode and a polysili-
`con wire bearing no silicide layer. when it is assumed that a
`polysilicon film has a thickness of 330 nm.
`the sheet
`resistance value of the polysilicon film is approximately
`3003A] even when the polysilicon film is doped with phos-
`phorus. In contrast. the sheet resistance value of the poly-
`silicon film including the silicide layers 9a and 9b of FIG.
`22 can be reduced to be lower than 3031:]. Furthermore. the
`sheet resistance value of the high concentration source/drain
`region 8 including the substrate silicide layer 9c can be
`reduced from approximately 100(c/Ij. which is a sheet
`resistance value when the silicide layer is not provided. to a
`value smaller than Stu/D. In addition. in the MOS transistor
`having the salicide structure. a contact resistance can be
`reduced to a value of 1/10 of that of a MOS transistor having
`a non-salicide structure. This is because. although not shown
`in FIG. 22. the polysilicon wire 4b and the high concentra-
`tion source/drain region 8 are connected to wire metal for
`interconnecting transistors by means of a junction between
`wire metal and a silicide layer. while they are connected by
`means of a junction between wire metal and silicon in a
`transistor of a non—salicide structure.
`
`As described above. by silicidating the upper portions of
`the polysilicon electrode 4a. the polysilicon wire 4b and the
`high concentration source/drain region 8.
`the resistance
`values thereof can be decreased. This results in minimization
`and refinement of wires and elements in a semiconductor
`
`device. and a rapid operation and low power consumption of
`the device.
`
`The production method for a MOS transistor having the
`conventional salicide structure will now be described refer-
`ring to FIGS. 23(a) through 230).
`First. as is shown in FIG. 23(a). the gate oxide film 3 and
`the polysilicon electrode 4a are formed in the active area
`surrounded by the isolation 2 around the surface of the
`silicon substrate 1. and the entire surface of the resultant
`substrate 1 is covered with the protection oxide film 5. At
`this point. also on the isolation 2 are formed the polysilicon
`
`

`

`5 ,726.479
`
`3
`wire 4b. which is deposited and patterned simultaneously
`with the polysilicon electrode 4a. and the protection oxide
`film 5. Then. by using the gate electrode 4a and the
`protecn‘on oxide film 5 as masks. impurity ions are injected
`into the active area of the silicon substrate 1 at a low
`concentration.
`thereby forming the low concentration
`source/drain region 6. After this. the side walls 7 are formed
`on the both sides of the polysilicon electrode 4a and the
`polysilicon wire 4b by anisotropic etching of a thick oxide
`film deposited by the chemical vapor deposition method
`(CVD). FIG. 23(0) shows the sectional view of the resultant
`substrate 1 at time when the formation of the side walls 7 is
`completed.
`Then. as is shown in FIG. 230)). by using the polysilicon
`electrode 4a and the side walls 7 as masks. the impurity ions
`are injected into the active area of the silicon substrate 1 at
`a high concentration. thereby forming the high concentration
`source/drain region 8.
`Next. as is shown in FIG. 23(c). the protection oxide film
`5 remaining on the polysilicon electrode 4a. the polysilicon
`wire 4b and the high concentration source/drain region 8 is
`removed by wet etching. so as to expose the surfaces of the
`polysilicon film and the silicon substrate. Then. a metal film
`10 (for example. a titanium film) is deposited on the entire
`surface of the resultant substrate 1 by the sputtering method.
`Then. as is shown in FIG. 23(a'). the resultant substrate 1
`is subjected to a rapid thermal annealing (RI‘A) treatment at
`a temperature of 600° C. to 700° C.. thereby allowing silicon
`contained in the polysilicon electrode 4a. the polysilicon
`wire 4b and the high concentration source/drain region 8 to
`react with titanium. so as to form silicide layers 11a through
`116 made of TiSi2 films. At this point. the titanium film 10
`on the isolation 2 and the side walls 7 is not silicidated owing
`to the absence of silicon therebelow but remains to be
`formed out of unreacted titanium.
`
`Next. as is shown in FIG. 23(e). the resultant substrate 1
`is subjected to the wet etching. thereby selectively removing
`merely the titanium film 10 made of unreacted titanium
`remaining on the isolation 2 and the side walls 7. while
`maintaining the silicide layers 11a through 11c. A typically
`used selective wet etching solution is an aqueous solution of
`hydrogen peroxide including ammonia or sulfuric acid. or
`the like.
`
`It is noted that the 'IiSi2 films (C49) constituting the
`silicide layers lla through 11c have rather high resistivity
`because they are formed through the annealing treatment at
`a comparatively low temperature (i.e.. 600° C. to 700° C.).
`Therefore. as is shown in FIG. 230‘). in order to further
`decrease the resistance of the silicide (TiSiz) layers 11a
`through 11¢. a second RI‘A treatment is performed at a
`comparatively high temperature of 750° C.
`to 850° C..
`thereby forming the silicide layers 9a through 9c made of
`"I'iSi2 films (CS4) with low resistivity. Thereafter. although
`the sectional View of the substrate in the subsequent proce-
`dure is not shown. an inter-layer insulating film is deposited
`and flattened. a contact hall is formed. a metal wire film is
`deposited. and a metal wire is formed. so as to complete an
`LSI.
`
`Through the aforementioned procedure. the MOS transis-
`tor having the salicide structure as shown in FIG. 22 can be
`produced.
`The salicide process has been developed and practically
`used for improving the performance of a VLSI as described
`above. As a VLSI becomes more and more refined and the
`design rule is progressively refined to 0.35 pm or 0.25 pm.
`the width of a polysilicon electrode and a polysilicon wire on
`
`10
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`25
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`30
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`35
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`45
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`the isolation is also minimized to 0.35 pm or 0.25 pm. As a
`result. there arises a problem that. although a resistance
`value per unit area (Le. a sheet resistance value) of the
`polysilicon film is not varied as the width of the polysilicon
`electrode 4a and the polysilicon wire 4b is minimized. the
`resistance value of the polysilicon film itself is increased in
`proportion to the inverse of the width thereof.
`In particular. a TiSi2 film. which is most commonly used
`as a silicide material and is most easily used in the process.
`is disadvantageous in View of this problem. This is because
`when the width of the polysilicon film is smaller than 1.0
`pm. the resistance value per unit area (the sheet resistance
`value) of the TiSi2 film is largely increased. Therefore. when
`the design rule is refined to 0.35 pm or 0.25 pm in using the
`TiSi2 film. the sheet resistance value of a wire with a
`minimum width of 0.35 um or 0.25 pm is very large as
`compared with the sheet resistance value of a wire with a
`width exceeding 1.0 pm. As a result. the effectivity as a
`silicide LSI wire cannot be exhibited (See Nikkei
`Microdevice. June issue. 1994. pp. 52—59). In using other
`materials with a high melting point other than TiSiz. such as
`CoSi2 and NiSi. the resistance values per unit area (the sheet
`resistance value) of these materials are comparatively less
`increased by the minimization of the width. However. when
`the width is further decreased. there possibly arises the same
`problem of the increase of the resistance value. and addi-
`tionally these materials also have another problem of difli—
`culty in practical use.
`SUMMARY OF THE INVENTION
`
`The present invention was devised to solve the aforemen-
`tioned problems. and the objective is providing. as a struc-
`ture or a production method for a semiconductor device
`mounting a transistor having a silicide layer on a polysilicon
`electrode. a semiconductor device having an extremely
`small resistance value applicable to minimization of the
`dimension of a polysilicon electrode and the like. and a
`production method for the same.
`In order to achieve the objective. not only the top surface
`of a polysilicon film but also part of the side surfaces thereof
`are silicidated in this invention. thereby reducing the resis-
`tance value.
`
`Specifically. the first semiconductor device of this inven-
`tion comprises an active m'ea formed in a part of a semi-
`conductor substrate; an isolation for surrounding the active
`area; a line-like polysilicon film formed at least on the active
`area and serving as a gate electrode on the active area; a pair
`of side walls formed on both side surfaces of the polysilicon
`film and made of an insulating film having a height of ‘/5 or
`less of a height of the polysilicon film; a silicide layer
`formed in contact with atop surface and portions of the side
`surfaces of the polysilicon film projecting from the side
`walls. and serving as the gate electrode on the active area
`together with the polysilicon film; and a source/drain region
`formed on the active area so as to be positioned on both sides
`of the polysilicon film.
`By adopting this structure in which not only the top
`surface but also part of the side surfaces of the polysilicon
`film are provided with the silicide layer. the resistance value
`of the gate electrode formed out of the silicide layer and the
`polysilicon film can be decreased. Accordingly. even when
`the dimension of the gate electrode is minimized. a sulfi-
`ciently small resistance value can be obtained.
`In the first semiconductor device. the following preferred
`embodiments can be adopted:
`The polysilicon film is formed on the active area and the
`isolation. and the polysilicon film on the isolation and the
`silicide layer on the isolation together form a wire.
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`5.726.479
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`5
`In this structure. the resistance value of the wire. which
`occupies a larger area than the gate electrode. can be
`reduced.
`
`The portions of the polysilicon film projecting from the
`side walls have a height to minimum linewidth ratio of 1/2 or
`more. and the silicide layer is formed by allowing silicidated
`portions from the both side surfaces of the polysilicon film
`to come in contact with each other at the center of a top
`surface of the polysilicon film.
`In this structure.
`the electric resistance value can be
`reduced when the gate electrode is further refined.
`The semiconductor device further comprises a second
`silicide layer formed in contact with the source/drain region.
`In this structure including the second silicide layer formed
`in contact with the source/drain region. which corresponds
`to a so-called salicide structure. the resistance value of the
`whole device can be suppressed even when the semicon—
`ductor device is refined. Thus. the advantage of the salicide
`structure cannot be spoiled.
`The isolation is a trench type isolation. and the top surface
`of the isolation is higher in a step—wise manner than a top
`surface of the semiconductor substrate in the active area.
`In this structure. the isolation function of the isolan'on can
`be prevented from degrading due to the decrease of its
`thickness during the formation of the side walls. and hence.
`it is possible to easily form the side walls having a smaller
`height than the height of the polysilicon film. Accordingly.
`the production procedure for the semiconductor device can
`be stabilized. improving the yield and the reliability thereof.
`The polysilicon film has a double-layer structure. at least
`in the active area. including a first polysilicon film and a
`second polysilicon film deposited on the first polysilicon
`film. and the side walls have a height smaller than a total
`thickness of the first polysilicon film and the second poly-
`silicon film.
`
`it is possible to appropriately adjust
`In this structure.
`properties such as impurity concentrations in the first and
`second polysilicon films in accordance with the application
`and the kind of the semiconductor device.
`On the isolation is formed a wire made of the second
`polysilicon film alone. and the top surface of the isolation is
`positioned at substantially the same height as a top surface
`of the first polysilicon film on the active area.
`In this structure. the groundwork of the second polysili-
`con film is flat. and hence. the patterning accuracy in the
`formation of the polysilicon film can be improved In other
`words. even when the semiconductor device is refined. a
`high dimension accuracy for the gate electrode can be
`attained
`
`The first polysilicon film is doped with a first conductivity
`type impurity at a high concentration. and the second
`polysilicon film is doped with the first conductivity type
`impurity at a low concentration.
`In this structure. not only the resistance value of the first
`polysilicon film is decreased but also the second polysilicon
`film can be silicidated with ease. Accordingly.
`the total
`resistance value of the polysilicon films can be largely
`decreased.
`
`The side walls are made of a silicon nitride film repre-
`sented by a general formula of Sifiy. and a protection oxide
`film is interposed between the silicon nitride film. and the
`polysilicon film or the semiconductor substrate.
`In this structure. since the etch selectivity between the
`silicon nitride film and the oxide film is high. the decrease
`of the thickness of the isolation during the formation of the
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`side walls can be suppressed to be as small as possible. This
`improves the isolation function.
`The second semiconductor device of this invention com-
`
`prises an active area formed in a part of a semiconductor
`substrate; an isolation for surrounding the active area: a
`line-like polysilicon film formed at least on the active area
`and serving as a gate electrode on the active area; a pair of
`electrode side walls made of L-shaped insulating films with
`a substantially constant thickness including vertical portions
`formed on side surfaces of the polysilicon film and horizon—
`tal portions extending from bottoms of the vertical portions
`in an opposite direction of the polysilicon film; a silicide
`layer formed in contact with a top surface of the polysilicon
`film and portions of the side surfaces of the polysilicon film
`projecting from the side walls. and serving as the gate
`electrode together with the polysilicon film; and a source/
`drain region formed in the active area so as to be positioned
`on both sides of the polysilicon film.
`By adopting this structure. the height of the side walls can
`be easily controlled. Accordingly. the effect attained by the
`first semiconductor device can be achieved more definitely.
`Also in the second semiconductor device. the aforemen-
`tioned preferred embodiments of the first semiconductor
`device can be adopted.
`The first production method for a semiconductor device of
`this invention comprises a first step of forming an isolation
`in an area close to a surface of a semiconductor substrate so
`as to surround an active area; a second step of forming a gate
`insulating film in the active area on the semiconductor
`substrate; a third step of depositing a plate-like polysilicon
`film on the gate insulating film and the isolation; a fourth
`step of forming a line-like polysilicon film at least on the
`active area by selectively removing the plate-like polysilicon
`film by etching; a fifth step of depositing an insulating film
`for a side wall on the semiconductor substrate bearing the
`line-like polysilicon film; a sixth step of forming side walls
`on both sides of the line—like polysilicon film by etching
`back the insulating film for a side wall. the side walls having
`a height that is 4/5 or less of a height of the line—like
`polysilicon film; a seventh step of forming a sourceldrain
`region by introducing impurity into the semiconductor sub-
`strate so as to be positioned on the both sides of the line-like
`polysilicon film in the active area; an eighth step of depos-
`iting a metal film on the entire surface of the substrate in
`which a top surface of the line—like polysilicon film and
`portions of side surfaces thereof projecting from the side
`walls are exposed; a ninth step of forming a silicide layer in
`contact with the top surface and the portions of the side
`surfaces of the line—like polysilicon film by allowing the
`metal film to react with the exposed portions of the line-like
`polysilicon film through a high temperature annealing treat-
`ment; and a tenth step of removing an unreacth portion of
`the metal film.
`
`By this production method. the first semiconductor device
`can be produced with ease.
`In the first production method. the following preferred
`embodiments can be adopted:
`The line-like polysilicon film is formed on the active area
`and the isolation in the fourth step.
`The side walls are formed so that the portions of the side
`surfaces of the line—like polysilicon film projecting from the
`side walls have a height to minimum linewidth ratio of '/2 or
`more in the sixth step. and the silicide layers proceeding
`from the side surfaces of the line-like polysilicon film are
`allowed to come in contact with each other at the center of
`the top surface of the line—like polysilicon film so that the
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`5 .726.479
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`7
`portions of the side surfaces of the line-like polysilicon film
`projecting from the side walls are entirely silicidated in the
`ninth step.
`The metal film is deposited with a surface of the source/
`drain region exposed in the eighth step. and a second silicide
`layer in contact with the source/drain region is simulta-
`neously formed in the ninth step.
`In the sixth step in particular. after the side walls are
`formed so as to have a height substantially equal to a
`thickness of the line-like polysilicon film by anisotropic dry
`etching. isotropic etching is conducted so as to reduce the
`height of the side walls.
`In this method.
`the decrease of the thickness of the
`isolation in the sixth step can be suppressed to be as small
`as possible by making use of a characteristic of wet etching
`that the etch selectivity between the side walls and the
`isolation can be increased.
`
`A silicon nitride film represented by a general formula of
`SixN'v is deposited as the insulating film for a side wall in the
`fifth step. and the method is further provided with a step of
`depositing a protection oxide film at least on the line-er
`polysilicon film and the surface of the semiconductor sub-
`strate between the fourth step and the fifth step.
`The first step includes steps of depositing an etching
`stopper film on the semiconductor substrate; forming a mask
`having an opening corresponding to an area for the isolation
`on the etching stopper film. conducting etching by using the
`mask so as to remove part of the etching stopper film
`corresponding to the opening of the mask. and then forming
`a trench by trenching part of the semiconductor substrate
`from the surface of the semiconductor substrate by a pre-
`determined depth; depositing an insulating film for embed-
`ding the trench on the semiconductor substrate bearing the
`trench; etching back the insulating film for embedding the
`trench and substantially flattening the surface of the semi-
`conductor substrate so as to expose at least a surface of the
`etching stopper film; and selectively removing the etching
`stopper film. The insulating film for embedding the trench
`that has remained in the trench forms trench type an isolation
`having a top surface that is higher in a step-wise manner than
`the top surface of the semiconductor substrate in the active
`area.
`
`In this method. even in the case where the thickness of the
`isolation is decreased in the sixth step, the isolation function
`can be avoided from degrading if a step is previously
`provided in anticipation of the decrease. Accordingly. the
`condition for the sixth step can be selected in a wider range.
`resulting in easy production of the semiconductor device.
`The first step includes steps of depositing an underlying
`polysilicon film on the semiconductor substrate; forming a
`mask having an opening corresponding to an area for the
`isolation on the underlying polysilicon film. conducting
`etching by using the mask so as to remove part of the
`underlying polysilicon film corresponding to the opening of
`the mask. and then forming a trench by trenching part of the
`semiconductor substrate from the surface thereof by a pre-
`determined depth; depositing an insulating film for embed-
`ding the trench on the semiconductor substrate bearing the
`trench; and etching back the insulating film for embedding
`the trench and substantially flattening the surface of the
`semiconductor substrate so as to expose at least a surface of
`the underlying polysilicon film. The insulating film for
`embedding the trench that has remained in the trench forms
`trench type an isolation having a top surface that is higher in
`a step—wise manner than the top surface of the semiconduc—
`tor substrate in the active area. The second step is conducted
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`before the step of depositing the underlying polysilicon film
`of the first step. The plate-like polysilicon film is deposited
`on the underlying polysilicon film and the trench type an
`isolation in the third step. The line-er polysilicon film in
`the active area is formed out of the underlying polysilicon
`film and the plate-like polysilicon film. and the line—er
`polysilicon film on the trench type an isolation is formed out
`of the plate-like polysilicon film alone.
`In this method. the accuracy in patterning the gate elec-
`trode can be improved.
`In the sixth step. after forming the side walls having a
`height substantially equal to the thickness of the line—like
`polysilicon film through anisotropic dry etching. the height
`of the side walls is reduced by further conducting anisotro-
`pic dry over-etching.
`In this method. the height of the side walls can be adjusted
`by dry etching which is superior in the control of an etching
`amount. and hence. the production procedure can be more
`stabilized.
`
`The second production method for a semiconductor
`device of this invention comprises a first step of forming an
`isolation in an area close to a surface of a semiconductor
`substrate so as to surround an active area; a second ste