of 85% relative humidity, 85 degrees centigrade, pressure cooker
`(121°C :3 100% RH. 15 psig) and a boiling water test which
`involves
`immersion of
`the device in boiling deionized water.
`Table II is a compilation of results of these tests. All tests unless
`otherwise noted were performed upon plastic encapsulated devices.
`The extremely low failure rates are indicative of the passivation
`provided by the anodic oxide. Those devices which did fail were
`subjected to failure analysis. It was determined that most failures
`were associated with the bond pad areas which do not receive an
`anodic overcoat. Some of the failures were associated with cor-
`rosion of the bond wires. No failures were noted which could be
`associated with corrosion of
`leads which were imbedded in and
`overcoated with the anodic oxide.
`Figure 5 is comparative data of anodized versus glass passivated
`process on identical devices of a different device type. Both the
`anodized samples and the control groups were subjected to the
`same 85% relative humidity 85°C environment. Both groups
`were unencapsulated. This data indicated that
`the passivating
`capability of
`the anodic oxide is nearly an order of magnitude
`greater than that of a glass overcoat.
`
`Conclusion
`The anodic processing of aluminum interconnect patterns pro—
`vides a method of
`rendering aluminum interconnect compatible
`with non hermetic packaging. The presence of the barrier layer
`at the aluminum surface acts to greatly enhance the corrosion re-
`sistance of aluminum metal. The reliability of such interconnects
`on plastic encapsulated integrated circuits has been demonstrated.
`An evaluation of the dielectric properties of the anodic oxide of
`aluminum indicate properties which are compatible with single
`and multilevel interconnects for integrated circuits.
`
`PERCENT FAILURE VS HOURS OF TESTING
`Aria/85
`
`CONTROLGROUPS
`
`AVG
`
`ANODIZED AI
`
`
`
`
`100
`
`I
`200
`
`|
`
`400
`
`600
`
`3001000
`HOURS
`
`2000
`
`4000
`
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`
`10000
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`
`Figure 5
`
`tangent.
`loss
`which again reflects the frequency insensitivity of
`Table I gives the dielectric properties of the anodic oxide grown
`under
`the conditions used in the fabrication of
`interconnect
`patterns.
`
`Reliability
`As discussed earlier the environment of high humidity and ele-
`vated temperature have the most deleterious effects upon aluminum
`interconnects. Transistor—transistor
`logic circuits were fabricated
`by the anodic process and subjected to a battery of
`reliability
`evaluation. The most severe environment encountered were those
`
`CURRENT CONCEPTS IN THE PASSIVATION
`AND ENCAPSULATION OF SEMICONDUCTOR
`DEVICES
`
`by
`BRUCE E. DEAL
`Research and Development Laboratory
`Fairchz’ld Camera and Instrument Corporation
`Palo Alto, California 94304
`71C38EI—21
`
`Introduction
`For several years after the introduction of the Planar passivated
`transistor,‘ this simple structure with thermal silicon dioxide over
`the junctions provided the basis of
`the standard semiconductor
`technology. The device was sealed in a hermetic metal package
`and little subsequent attention had to be given to it. Gold or
`aluminum bonds were made to aluminum contacts alloyed to the
`silicon contact regions. However,
`the development of integrated
`circuits,
`initially simple by today’s standards,
`lead to increased
`complexity of structure and of fabrication procedures. Further—
`more, improved reliability became a necessity with the introduction
`of MOS transistors. which are very surface sensitive. It was found
`that by careful processing the same thermal oxide passivated struc—
`tures in metal packages could provide stable MOS devices. How—
`ever, it also became apparent that for mass production and low
`costs required in the industry, other means of passivation and
`encapsulation would have to be developed, This was especially
`true when the complexity of the integrated circuits was combined
`with the sensitiveness of MOS devices.
`This paper provides a review of these new concepts in passiva~
`tion and encapsulation of semiconductor devices. The changing
`role of
`the dielectric films used for passivation and protection
`will be discussed along with newer approaches to the metal con-
`tacts and interconnections. Also,
`the various types of packages—
`metal, ceramic and plasticfiwill be briefly described, as well as
`problems associated with each system. Finally, the use of dielectric
`layers for providing corrosion and mechanical protection of
`the
`metallized circuits will be considered. along with possible inter-
`actions between the various packaging materials and device com-
`ponents.
`It will be observed that the proper selection of the di—
`electric films will be a key factor in the successful development
`of reliable, low cost semiconductor devices.
`
`Passivation
`A cross—section of a typical, Planar—passivated diffused junction
`in silicon is shown in Figure 1. The drawing is such that the left—
`hand side might represent a diode or a collector—base junction of
`a bipolar transistor, while the right—hand includes a metal
`field
`plate over the oxide as is the case for an MOS transistor. It is now
`well known that several charges can be associated with the ther-
`mally oxidized silicon system. These include fast interface states,
`Nxt,
`fixed surface charge, st, mobile impurity charge, Q", and
`traps due to ionizing radiation, Not, as Well as ion or charge
`migration on the oxide surface?" These charges and their loca-
`tion in the oxide are also indicated in Figure 1. The measurement
`and characterization of
`these charges has been the subject of
`numerous investigations, many of them listed in the MIS bibliog—
`raphies of Schlegal.5 Many of these investigations made use of
`the MOS capacitance—voltage method of analysis,“7 and this pro—
`cedure continues to provide a rapid but simple means of studying
`charge effects in dielectric layers on semiconductors.
`The presence (or migration) of the charges in the MOS struc—
`tures has been found to have an appreciable effect on device
`
`MIGRATION OF CHARGES
`ON OXIDE SURFACE
`
`
` METAL FIELDPLATE
`
`P—TYPE Si
`
`
`Figure l—Example of Charges Associated with Thermally
`Oxidized Silicon Device Structure: Q58, Fixed Surface
`Charge; Q“, Mobile Impurity Ion; Nat, Fast Surface State;
`Not, Hole Traps Formed by Ionizing Radiation; and Charge
`Migration on Oxide Surface.
`
`TSMC 1014
`TSMC 1014
`
`

`

`low current beta, noise, and
`electrical properties. For instance,
`breakdown voltage of bipolar transistors can be affected, while
`turn—on voltage and channel conductance in MOS devices have a
`critical dependence on the charge densities. Figure 2
`indicates
`some of the possible changes in the densities or location of these
`charges in the oxide due to electric fields and the resulting effects
`on the silicon surface.
`It has been adequately demonstrated,
`however,
`that by careful processing,
`these charge densities can
`be controlled and minimized so that stable MOS and other devices
`can be fabricated.2 However, as the need for increased production
`of more complex devices occurred with an additional requirement
`of lower costs, it was found that the control procedures required
`for stable oxide—passivated devices were very difficult to implement
`under production conditions Further, expensive hermetic packages
`were also required for these sensitive devices. While the thermal
`oxide can be produced free of
`ionic contaminants,
`its structure
`does not prevent subsequent penetration by ionic impurities or
`other contamination even at low temperatures. Thus the concept
`of double dielectrics was established,
`in which a second dielectric
`capable of masking ionic impurity migration is deposited over
`the passivating thermal oxide.
`The first dielectric to be used as a passivating layer over ther—
`mally oxidized silicon devices was phosphosilicate glass
`(PSG).R
`It is applied by the vapor deposition of P20; as in diffusion pre-
`deposition processing,
`the phosphorus oxide mixing with the outer
`SiO: layer to form a PQOS-SIO: glass—like structure. This film was
`found to prevent ionic impurities from diffusing through it as well
`as to getter impurity ions such as sodium from the underlying
`5102. Its disadvantages were that it reacts readily with water as well
`as exhibiting an undesirable structural polarization effect.9 Even so,
`under proper conditions,
`i.e. controlled thickness and phosphorus
`concentration, it can be used effectively to better passivate thermal
`oxides and the associated device structures.10
`Another type of passivating layer used in conjunction with ther—
`mal oxides is a “dense” dielectric such as silicon nitride (SLAM)
`or aluminum oxide (A1203). This type of film prevents the ionic
`impurities from diffusing through it due to close—packed structure,
`as opposed to the complexing or gettering action of the phospho‘
`silicate glass. Silicon nitride is generally deposited by the vapor
`phase reaction of SiI—I. or SICII with NH; in the temperature range
`650-IOOO°C, while alumina films have been produced by the low
`temperature anodization of deposited aluminum as well as the
`higher temperature vapor deposition processes. Both types of films
`have also been deposited by sputtering techniques.
`Investigations
`
`300°C
`
`vG >0
`
`AI
`
`300°C v <0
`
`No+ Nc+ NO+ No+
`|
`I
`I
`I
`I
`I
`I
`I
`I
`l
`.
`
`I
`I
`I
`|
`I
`I
`No+ No+ No+
`CI— 0- CI-
`
`
`
`SiOg
`
`SI
`
`(CI) MIGRATION OF POSI-
`TIVE IONS (Qo)
`THROUGH OXIDE TO
`SIOZ -$I INTERFACE
`
`(b) MIGRATION OF POSI-
`TIVE IONS TO AI'SIOZ
`INTERFACE, LEAVING
`IMMOBILE NEGATIVE
`IONS IN OXIDE
`
`300°C v «o
`
`AI
`
`SI
`
`SiOa
`
`VG >0
`
`
`
`(a)
`
`INDUCTION OF ADDI-
`TIONAL POSITIVE FIXED
`CHARGE (033) AND FAST
`STATES (N37) BY HIGH
`FIELD -TEMPERATURE
`STRESS (DRIFT II)
`
`(d) INDUCTION OF HOLE
`TRAPS (No-r) AND
`FAST STATES (NST)
`BY IONIZING RADIA-
`TION
`
`involving double layers of $th or A1203 over thermally oxidized
`silicon are reported.1145
`these dense
`the use of
`It has been definitely established that
`films, especially silicon nitride. will provide much more reliable
`devices. The main advantage is that up to 500°C.
`ion migration
`through the film is essentially eliminated. The main disadvantages
`of
`these films are that processing, especially photomasking, be-
`comes more difficult, and that additional
`instabilities are en-
`countered. These are discussed below. A typical passivated device
`structure is shown in Figure 3, where the second dielectric may be
`phosphosilicate glass,
`silicon nitride or aluminum oxide. Note
`the two examples where the edge of the oxide contact cut may or
`may not be “sealed” with the second dielectric.
`Other dielectrics used over thermal oxides have included SiO:
`and other oxides deposited by various techniques. These include
`evaporation, sputtering, vapor phase reaction and sedimentation.
`The main purpose of these second layer oxides is to increase the
`thickness of
`the original
`thermal oxide and thus prevent
`field
`inversion beneath current—carrying interconnections.
`In general.
`these oxides will not prevent ion migration. They may be valuable
`in providing chip protection of
`the metallized circuits. and this
`aspect
`is discussed below. A general discussion of these deposited
`oxides is available.“3*17
`An important consideration for the effectiveness of all the above
`double-layer dielectrics
`is whether
`they contribute
`additional
`instabilities to the device properties. The advantage gained by the
`elimination of ion migration may be canceled by additional effects.
`Four possible charge effects have been found that can be associated
`with double»dielectric structures. These are indicated in Figure 4.
`and are shown to be polarization due to dipole orientation, inter—
`face trapping. polarization due to conductivity differences and
`interface charge formation.2 Many studies have been reported for
`all
`these cases and most of
`the instabilities can be minimized
`by proper process conditions and control
`for each type of
`di—
`electriC.
`It is not within the scope of this paper to discuss these
`effects, but they must each be considered in evaluating any given
`double-dielectric system.
`
`Metallization
`films were originally used to provide an
`Evaporated metal
`ohmic contact between the silicon junction areas and a lead wire
`for connections to outside the package. As geometries got smaller
`and with the development of integrated circuits, the metal system
`became a complex array of interconnecting lines and contacts (see
`Figure 5). More attention had to be paid to effects of
`the
`metallization on device characteristics and reliability as well as the
`effect of the package and/or ambient on the metal integrity itself.
`The most commonly used metal
`for
`the above applications in
`semiconductor
`technology has been aluminum.1“*“‘ Schnablem
`in his
`review, discusses advantages and disadvantages of
`the
`aluminum metallization system. The advantages are based on its
`ease of processing (deposition, etching, etc). its high conductivity.
`and its good adherence and contacting properties. At
`the same
`time its reactivity, which accounts for most of
`these desirable
`properties, also leads to disadvantages. That is, it can be attacked
`readily by plastics used for packages and by moisture which is
`present
`in nonhermetic packages,
`It
`is also subject
`to electro—
`migration under high current density conditions
`and micro—
`cracking when deposited over steep oxide steps.
`The corrosion problem of aluminum interconnections in plastic
`packages has led to the investigation of other systems. One of the
`most notable is a part of the Beam Lead Structure (mentioned
`below) which makes use of a Pt—Sig contact to the silicon, covered
`by a Ti—Pt-Au multilayer structure.20 This is then combined with
`a Si::Nf-Si02 dielectric passivation system/31 Neither
`this metal
`system (especially the platinum) nor the silicon nitride will allow
`
`PSG OR 8 I3N4
`PASSIVATING
`
`LAYER
`
`SEALED 0x105
`CONTACT CUT
`
`UNSEALED OXIDE
`CONTACT CUT
`
`COLLECTOR
`
`EMITTER
`
`SILICON
`
`Figure Z—Examples of Processing Effects on Density
`or Location of Four Types of Charges in Thermally Oxi-
`dized Silicon Structure.
`
`Figure 3—Typical Double Dielectric Structure Used for
`Passivating Semiconductor Device. Examples of Both
`“Sealed” and “Unsealed” Oxide Contact Cut are Indicated.
`
`64
`
`

`

`VG >> O 25°C
`
`ALUMINUM
`
`DEPOSITED
`DIELECTRIC
`
`THERMAL
`OXIDE
`
`
`
`SILICON
`(a) POLARIZATION DUE TO
`DIPOLE ORIENTATION
`
`j:
`INTERFACE
`TRAPPING
`
`(b)
`
`+vG 25°—300°c
`ALUMINUM
`
`DEPOSITED
`
`DIELECTRIC
`
` THERMAL
`
`OXIDE
`
`1L SILICON
`(C) POLARIZATION (OR
`TRAPPING) DUE TO
`CONDUCTIVITY DIFF-
`ERENCES
`
`vG =0
`
`25°C
`
`
`
`(d) INTERFACE CHARGE
`(AS DEPOSITED)
`
`lnstabilities or
`Figure 4—Four Different Types of
`Charges Associated With MIOS (Metal-Insulator-Oxide—
`Semiconductor) Structures.
`
`
`
`Figure 5—Comparison of Early and Simple (~1963,
`'70 X 70 mils, 6 Components) and Recent and Complex
`(1970, 110><140 mils, 2485 Components)
`Integrated
`Circuits with Aluminum lnterconnections.
`
`sodium penetration up to at least 300°C and thus a sealed device
`structure is obtained. Furthermore,
`the outer gold layer is very
`inert to corrosion. As it turns out, however, the nonreactivity of
`the gold and platinum also result
`in more difficult processing.
`Thus the advantages and disadvantages are just
`the opposite as
`compared to aluminum.
`Other metallization systems have also been reported. These in—
`clude Mo—Au, W—Au, Cr—Au, and Cr-Ag—Au multilayers and Al—Si
`or Al-Cu alloys?“25 Each of
`these combinations shows some
`advantages, but processing difficulties and other problems indicate
`that no one system satisfies all requirements.
`In general, the more
`active the metal, the easier the processing but the more likelihood
`of corrosion in plastic and nonhermetic packages. One of
`the
`problems associated with any nonreactive metal such as platinum,
`is
`that
`its high melting and boiling points
`require that e.b.
`evaporation or sputtering be used for the deposition.
`In either
`case ionizing radiation is produced and can adversely affect device
`parameters, Also‘
`these processes are more difficult
`to operate
`and control under production conditions.
`A recent development in the fabrication of gates for MOS devices
`the use of a high temperature metal such as molybdenum.26
`is
`Its high melting point and relatively ease of etching allows subse—
`quent high temperature processing such as diffusion and dielectric
`deposition.
`It
`is therefore possible to fabricate self—aligned gate
`MOS transistors with dielectric passivation over
`the gate. The
`same concept has been followed in the fabrication of silicon—gate
`MOS transistors?7 The use of silicon as a gate and interconnection
`material provides additional advantages in that
`it can be doped
`for low resistance applications or left undoped, it can be oxidized
`and it is very compatible with the Si—SiO: system. A silicon-gate
`structure is shown in Figure 6.
`
`Assembly and Encapsulation
`Once the semiconductor device or circuit is fabricated and diced,
`contacts must be made from the device pad areas to leads going
`to the outside world and it must
`then be suitably encapsulated
`Miller has presented two good reviews on the subject of “chip—
`joining techniques” which are the assembly procedures used to
`mount and connect to devices in chip form/“"3" He divides these
`chip—joining schemes into:
`(a) back-joined configurations [wire
`bonding 5‘“ and imbedded devices 31],
`(b)
`flip—chip procedures
`[controlled—collapse?“ nonmolten pads,” and spider bond 33],
`and (c) beam leads20 It is obvious that device reliability is going
`to depend on effects on electrical characteristics due to the applica—
`tion of the various metals involved in the schemes, as well as on
`changes in the contact characteristics of these systems. For pur—
`poses of
`this discussion,
`the main concern will be the ability of
`
`A I
`
`A I
`
`
`
`
`
`//
`
`
`
`
`P+ Si
`
`SOURCE
`
`
`
`
`Figure 6—Cross-Section and Top View of Si-Gate
`Transistor.
`
`65
`
`

`

`in the contact area to withstand corrosion and to
`the metal
`prevent
`ions from migrating into the passivating dielectric layer.
`The latter possibility is shown in Figure 7.
`In the example shown,
`the SinNi
`layer does not cover the edge of the oxide cut. Thus,
`sodium can, by penetrating the aluminum, migrate into the oxide
`region over
`the junction. Obviously a metal such as platinum,
`which masks against sodium,
`is desirable as has been found in
`the Ti—Pt-Au beam lead system?1 The degree to which a metal
`will mask against
`this migration will determine the amount and
`nature of masking required by the underlying dielectric film.
`Three general
`types of packages have been used for
`semi—
`conductor device encapsulation These are metal, ceramic and
`plastic.
`In turn, many types of each have been used, depending
`on the requirement. Discussions of the various packaging concepts
`for semiconductor devices are available/“’3‘
`In all cases,
`the possible interactions between the packaging
`materials and the various parts of the device structure, e.g.
`di—
`electric films, metallization, etc. and the subsequent degradation
`of electrical characteristics have been important aspects in de‘
`termining the usefulness of any given package. At the same time,
`however,
`the fabrication cost and complexity also have been im—
`portant factors in selecting a package.
`For a number of years,
`the package used to encapsulate tran—
`sistors and diodes was the metal can.
`It could be hermetically
`sealed and thus provided no difficulties in regards to interaction
`with the device structure.
`In fact,
`if it could still be used with
`integrated circuits,
`the
`complex dielectric passivation schemes
`discussed earlier would not be necessary. Several factors, however,
`led to the introduction of ceramic hermetic packages and plastic
`encapsulation. For one,
`the complexity of
`the circuits required
`many leadsiconsiderably more than twelve which was possible
`with the metal can. Also. automated assembly techniques and the
`associated low cost were not compatible with the conventional
`TO—S or TO-18 header assemblies.
`Various types of ceramic packages have thus been introduced
`which use a variety of
`lead configurations and sealing methods,
`Materials used for sealing can have a considerable effect on device
`properties and reliability. These sealing materials include metals.
`glasses and plastics. The glasses which can provide the best seals
`and are easy to work with are also the hardest
`to control and
`can have very adverse effects on device properties. Difficulties
`that have been encountered with glass seals are:
`(a) device con—
`tamination due to impurities vaporizing from the glass during
`sealing, (b) splattering of glass on the device during sealing,
`(c)
`attack of
`the device metallization or
`the glass
`seal
`itself by
`moisture, and (d)
`reduction of the glass components resulting in
`lead shorts. A cross—section of a typical ceramic structure with
`a glass seal is shown in Figure 8, and possible splattering of
`the
`glass due to improper processing is indicated.
`Plastic packages meet
`the requirements involving low cost and
`automatic assembly. Unfortunately most plastics are not
`com—
`pletely hermetic and the formulations include chemical
`species
`detrimental
`to device reliability. Even so, more and more plastic
`encapsulated devices are being fabricated and ways to solve the
`above problems are being worked out. A very good review of
`plastics for semiconductor devices is given by Licari.39 In addi—
`tion, other papers have been written on the subject of device re—
`liability in plastic packagesmT”
`Two common types of plastics have been used for device en—
`capsulation. These are epoxies and silicones. The epoxies tend
`to be less susceptible to moisture penetration but are generally
`not as pure as silicones. The latter are more easily applied by
`
` SiOz NO, No+ rig Al-Si CONTACT
`
`@639
`
`
`
`N+ SILICON
`
`P-TYPE SILICON
`
`
`
`Figure 7—Sodium Ion Penetration Through Aluminum
`at Oxide Edge of Semiconductor Device With no Overlap
`of Silicon Nitride Layer in Contact Cut Region.
`
`66
`
`CERAMIC LID
`
`WI/I/I/l/l/l/l/I/I/I/
`
`l
`
`W
`
`PACKAGE
`
`METAL
`IEEmE
`
`DEV'CE
`CH'P
`
`SPLATTERED
`GLASS OR
`CONTAMINATION
`
`CERAMIC
`
`Figure 8—Example of Possible Glass Splattering or Con-
`tamination From Sealing Class in Ceramic Package.
`
`transfer—molding techniques which lend themselves to automatic
`packaging. Other plastics used to a
`lesser extent have been
`phenolics and polyesters. As mentioned above,
`the various com—
`ponents that have to be added to the plastic for required physical
`and other properties can adversely affect device performance and
`reliability. An informative discussion of these effects is presented
`by Olberg.m
`so—called
`are
`the outer plastic packages
`Often used under
`“barrier” or “junction” organic coatings. These are of particular
`importance because of
`the ability of
`these films to protect
`the
`device against
`the less-pure outer package. Barrier coatings,
`ap—
`plied over the metallized chip by dipping, spraying. eye-dropper.
`etc, are for the most part high—purity silicones.
`In addition, recent
`work has been devoted to the use of “Parylene” polymer films
`for the protection of device circuits against moisture and other
`contaminants.”
`
`Chip Protcclion
`The above discussions indicate two important failure modes for
`devices encapsulated in a nonhermetic material
`such as plastic
`or subjected to contamination during high temperature scaling
`in ceramic packages. One is the migration of impurity ions into the
`passivating dielectric over the active device region. which causes
`degradation of device characteristics. This failure mode can be
`minimized by the use of a dense dielectric such as silicon nitride
`over
`the surface and contact cut edges of passivating thermal
`oxide.
`The second major failure mechanism involves the metallization
`system-usually aluminum. The metal may fail due to mechanical
`damage during assembly. due to corrosion by the action of moisture
`and/or components in the packaging material or due to electro—
`migration at high current densities.
`In addition.
`impurity ions
`may migrate through the contact pad areas if the oxide cuts have
`not been overlapped with the dense dielectric. These and other
`failure mechanisms involving the metallized circuit have led to the
`concept of chip protection. A relatively thick (1—2 M.) dielectric
`film is deposited over
`the entire chip after metallization, and
`Openings are then etched for the contacts. Methods of deposition
`have included sedimentationJ-‘tTH sputtering,”’1“ vapor depOsi—
`tion “"17 and others such as evaporation,” and spin-on tech—
`niques.“ Dielectrics
`that have been used are silicon dioxide,
`Pb—Zn—B and other sedimented glasses. phosphosilicate, borosilicate.
`and aluminosilicate glass and aluminum oxide, Silicon nitride has
`not yet found much use for
`this application due to the higher
`temperature required for its deposition and because thicker films
`tend to craze,
`The most commonly used chip protection scheme involves the
`use of SiO: or Pgos-SIO: depOsited by the reaction of Sth (and
`PH;;) with O:.“‘"” A typical structure is shown in Figure 9. The
`chip protection dielectric, especially the phosphosilicate glass. can
`provide mechanical protection, corrosion protection and mask
`against
`ionic impurities, The one problem area is
`in the open
`bonding pad area. especially if
`the metal
`is aluminum and the
`package is plastic. Proposals have been made to deposit other
`metals such as gold in the pad, as well as to use varnishes and
`other plastics as barriers.
`Mention should be made of aluminum oxide as a chip protection
`dielectric. It was originally proposed to be deposited by the vapor
`deposition technique ‘7 but more recently selective anodization
`has been reportedJI’T-m In the latter case, aluminum is deposited
`over the entire circuit, a
`thick anodic A120” coating is prepared
`in the field regions, and the resulting defined aluminum intercon—
`nections are protected by a barrier—type anodization,
`Another interesting method for depositing silicon oxides or other
`
`

`

`WIRE
`BOND
`
`
`
`MW
`
`
`
`
`
`
`\
`
`
`
` 10.
`
`Figure 9—Typical Chip Protection Scheme of Semi-
`conductor Device Structure. Note Edge-Sealed Contact Cut
`and Deposited Oxide Over Entire Structure. Aluminum
`Bonding Pad Area is Expoesd, However.
`
`dielectrics over the metallized device is a “spin-on” technique.“
`In this case.
`the oxide if
`formed by the low temperature de—
`composition ot an organic compound deposited from solution by
`the conventional spin-0n process normally associated with photo-
`masking technology.
`
`Conclusions
`in
`semiconductor devices
`to providing reliable
`Approaches
`non-hermetic packages has been reviewed and several conclusions
`are evident. First,
`the thermal silicon dioxide which is required
`for stable and controllable device characteristics must be pro-
`tected by an outer. dense dielectric. Fortunately, both phospho—
`silicate glass and silicon nitride are available for this purpose, and
`these are being used successfully.
`The second conclusion that may be drawn is that the metalliza—
`tion is subject
`to mechanical damage during fabrication as well
`as chemical attack by the packaging materials and moisture. The
`latter is especially true if
`the metal
`is a reactive one such as
`aluminum, Ways of minimizing this attack include improving
`the purity and processing of the sealing material used for ceramic
`packages and providing high purity plastic packages with low
`permability to moisture. Also, additional benefits may be obtained
`by the use of organic barrier coatings between the outer package
`and the device.
`The most
`important consideration, however, will be the selec-
`tion of a suitable chip protection dielectric film. This is de-
`posited over
`the metallized circuit by one of several possible
`methods and may be one of a variety of compounds It must have
`the ability to provide mechanical protection of the metallization
`during assembly,
`to protect the metal against corrosion or other
`chemical attack due to the packaging material and environment
`and to offer some masking against ionic contamination. A secondary
`problem of chip protection is the protection of the binding pad
`areas and lead wire material against corrosion. This may be ac—
`complished by the choice of metal and possibly the additional
`organic coatings.
`In summary, device reliability of the future will depend in part
`on the best processing and control
`techniques of the passivating
`dielectric over the active device, the proper choice of the metalliza—
`tion system and the use of
`the highest purity, most moisture
`resistant packaging material. The best
`insurance, however,
`for
`the ultimate in device stability will be an optimum chip protection
`system which protects the semiconductor circuit from the package
`and any other form of mechanical or chemical attack.
`
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