throbber
Yusuf Leblebici
`
`Sung-Mo Rang-:1”
`
`TSMC 1011
`
`Third Editin‘n
`
`Anafysfs and Design
`
`

`

`Physical and Materials Constants
`
`Boltzmann's constant
`
`Electron charge
`
`Thermal voltage
`,
`
`k
`
`q
`
`1.38 x 10‘23
`
`1.6 x 10‘19
`
`kT/q
`’
`
`V
`0.026
`(at T = 300 K)
`
`Energy gap of silicon (Si)
`
`Eg
`
`Intrinsic carrier
`
`concentration of silicon (Si)
`
`n'.
`
`1.12
`(at T = 300 K)
`
`1.45 x 1010
`(at T = 300 K)
`
`Dielectric constant
`
`of vacuum
`
`Dielectric constant
`
`of silicon (Si)
`
`Dielectric constant
`
`60
`
`651.
`
`8.85 x 10‘14
`
`11.7 x 60
`
`of silicon dioxide (SiOz)
`
`60x
`
`3.97 x 60
`
`J/K
`
`C
`
`V
`
`eV
`
`cm‘3
`
`F/cm
`
`F/cm
`
`F/cm
`
`Commonly Used Prefixes for Units
`
`giga
`mega
`kilo
`milli
`
`micro
`nano
`
`pico
`femto
`
`G
`M
`k
`m
`
`p.
`n
`
`p
`f
`
`109
`106
`103
`10‘3
`
`10'6
`10'9
`
`10‘12
`10'15
`
`

`

`second ieditinn
`
`CMOS
`
`DIGITAL
`
`INTEGRATED
`CIRCUITS
`
`Analysis and Design
`
`SUNG-Mo (STEVE) KANG
`University of Illinois at Urbana—‘ Champaign
`
`YUSUF LEBLEBICI
`
`Worcester Polytechnic Institute
`
`Swiss Federal Institute of Technology-Lausanne
`
`' I
`gr“, WCB
`n? McGraw-HIII .
`
`Boston Burr Ridge,IL Dubuque,IA Madison,WI New York San Francisco St. Louis
`Bangkok Bogota Caracas Lisbon London Madrid
`Mexico City Milan New Delhi Seoul Singapore Sydney Taipei Toronto
`
`

`

`Copyrighted Material
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`McGraw-Hill Higher Education :7\
`A
`of'fiv fiter-HfliComMie;
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`
`'
`
`CMOS DIGITAL INTEGRATE. CIRCUITS: ANALYSIS AND DESIGN
`(cid:50)(cid:78)(cid:89)(cid:239)(cid:56)(cid:65)(cid:59)(cid:65)(cid:103)(cid:239)(cid:115)(cid:51)(cid:60)(cid:41)(cid:52)(cid:58)(cid:37)(cid:61)(cid:41)(cid:53)(cid:183) (cid:44)(cid:59)(cid:86)(cid:44)(cid:100)(cid:60)(cid:98)(cid:88)(cid:33)(cid:206)(cid:40)(cid:75)(cid:40)(cid:71)(cid:102)(cid:88)(cid:61)(cid:89)(cid:206)(cid:40)(cid:76)(cid:48)(cid:206)(cid:49)(cid:202)(cid:93)(cid:59)(cid:56)(cid:75)(cid:206)
`'UIJRI EDITION
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`
`Nutshod by McGraw-Hi]l.a business unit 0! “We MchwJ-{ill Compani‘s- Inn. l22] Avenue
`(cid:94)(cid:122)(cid:165)(cid:166)(cid:142)(cid:239)(cid:67)(cid:176)(cid:183)(cid:83)(cid:60)(cid:201)(cid:111)(cid:7)(cid:232)(cid:63)(cid:162)(cid:109)(cid:23)(cid:239)(cid:64)(cid:183)(cid:68)(cid:170)(cid:156)(cid:97)(cid:136)(cid:183)(cid:169)(cid:130)(cid:98)(cid:107)(cid:183) (cid:125)(cid:3)(cid:36)(cid:55)(cid:183)(cid:50)(cid:69)(cid:52)(cid:152)(cid:174)(cid:179)(cid:43)(cid:97)(cid:113)(cid:109)(cid:183)(cid:53)(cid:103)(cid:127)(cid:6)(cid:134)(cid:114) (cid:145)(cid:5)(cid:183)(cid:43)(cid:52)(cid:47)(cid:54)(cid:7)(cid:6)(cid:54) (cid:13)(cid:17)(cid:17)(cid:54)(cid:60)(cid:206)(cid:18)(cid:176)(cid:67)(cid:171)(cid:56)(cid:183)
`of the Aancricas. New York. NY [0020. Copyrigth 200}. IS”. [9‘96 by The Mchaw-Hill
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`(cid:19)(cid:126)(cid:127)(cid:41)(cid:114)(cid:84)(cid:58)(cid:145)(cid:4)(cid:183)(cid:108)(cid:142)(cid:10)(cid:183) (cid:37)(cid:113)(cid:109)(cid:183) (cid:141)(cid:88)(cid:75)(cid:79)(cid:158)(cid:150)(cid:183)(cid:236)(cid:117)(cid:20)(cid:239) (cid:75)(cid:166)(cid:206)(cid:70)(cid:71)(cid:173)(cid:239)(cid:125)(cid:72)(cid:183) (cid:97)(cid:80)(cid:86)(cid:145)(cid:183)(cid:127)(cid:168)(cid:45)(cid:97)(cid:93)(cid:39)(cid:161)(cid:125)(cid:114)(cid:183)(cid:112)(cid:172)(cid:181)(cid:183)(cid:121)(cid:239)(cid:31)(cid:26)(cid:36)(cid:125)(cid:134)(cid:183) (cid:15)(cid:23)(cid:56)(cid:46)(cid:42)(cid:24)(cid:9)(cid:39)(cid:51)(cid:20)(cid:57)
`Companies. inc. All righls named. No pm: of Ihis publication any be Wad or distributed
`in any form or by any means. or slated in udiuubascor muicval SWCOL M11me Wm M itlw
`(cid:87)(cid:115)(cid:183)(cid:26)(cid:181)(cid:183)(cid:148)(cid:239)(cid:125)(cid:135)(cid:183)(cid:111)(cid:197)(cid:206) (cid:104)(cid:156)(cid:198)(cid:206)(cid:111)(cid:58)(cid:41)(cid:114)(cid:145)(cid:6)(cid:183)(cid:21)(cid:34)(cid:145)(cid:162)(cid:55)(cid:54)(cid:183)(cid:134)(cid:156)(cid:206)(cid:35)(cid:34)(cid:52)(cid:25)(cid:33)(cid:9)(cid:27)(cid:6)(cid:47)(cid:57)(cid:11)(cid:21)(cid:52)(cid:157)(cid:60)(cid:99)(cid:155)(cid:95)(cid:58)(cid:178)(cid:43)(cid:96)(cid:183)(cid:155)(cid:178)(cid:158)(cid:163)(cid:82)(cid:132)(cid:114)(cid:7)(cid:183)(cid:28)(cid:135)(cid:219)(cid:170)(cid:180)(cid:206)(cid:218)(cid:239)(cid:128)(cid:139)(cid:84)(cid:125)(cid:134)(cid:183)(cid:193)(cid:175) (cid:135)(cid:157)(cid:194)(cid:206)
`comm: ot‘lhc Mmew—Hiil Companics- It:.. intluding. but ml limiictl M in any Acka aroma
`(cid:115)(cid:167)(cid:163)(cid:179)(cid:123)(cid:159)(cid:180)(cid:206)(cid:125)(cid:3)(cid:35)(cid:80)(cid:55)(cid:183)(cid:81)(cid:126)(cid:52)(cid:198)(cid:226)(cid:62)(cid:161)(cid:170)(cid:171)(cid:239)(cid:38)(cid:138)(cid:11)(cid:131)(cid:145)(cid:65)(cid:133)(cid:105)(cid:155)(cid:5)(cid:183) (cid:59)(cid:161)(cid:117)(cid:206)(cid:5)(cid:6)(cid:183)(cid:98)(cid:131)(cid:72)(cid:113)(cid:170)(cid:77)(cid:102)(cid:8)(cid:183)(cid:9)(cid:53)(cid:48)(cid:57)(cid:20)(cid:25)(cid:34) (cid:96)(cid:98)(cid:104)(cid:25)(cid:12)(cid:1)(cid:52)(cid:183)(cid:24)(cid:2)(cid:34)(cid:24)(cid:115)(cid:183)(cid:44)(cid:181)(cid:183)(cid:123)(cid:164)(cid:94)(cid:183) (cid:125)(cid:135)(cid:183)(cid:12)(cid:239)
`electronic W or Lwnsrrussion. «r bmmlcasl for dislmcc teaming.
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`
`Sm amiUun'ex. including clncuouic and paint components. may not be available '0 enscomcrs
`(cid:102)(cid:140)(cid:239)(cid:8)(cid:49)(cid:24)(cid:12)(cid:14)(cid:26)(cid:18)(cid:43)(cid:1)(cid:52)(cid:136)(cid:158)(cid:118)(cid:189)(cid:120)(cid:139)(cid:158)(cid:128)(cid:206)(cid:66)(cid:63)(cid:163)(cid:125)(cid:115)(cid:84)(cid:46)(cid:183)(cid:41)(cid:121)(cid:53)(cid:183)(cid:131)(cid:84)(cid:105)(cid:183)(cid:50)(cid:103)(cid:127)(cid:125)(cid:22)(cid:21)(cid:114)(cid:156)(cid:151)(cid:12)(cid:183)(cid:185)(cid:14)(cid:239)(cid:131)(cid:2)(cid:160)(cid:183) (cid:9)(cid:50)(cid:57) (cid:46)(cid:152)(cid:6)(cid:46)(cid:179)(cid:180)(cid:45)(cid:66)(cid:239)(cid:153)(cid:125)(cid:183) (cid:56)(cid:175)(cid:125)(cid:109)(cid:47)(cid:134)(cid:145)(cid:183)
`oulsidc ahc United States.
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`
`'l‘hiz boot is Winscd on arid-[rec paper.
`(cid:7)(cid:26)(cid:57)(cid:11)(cid:12)(cid:57)(cid:5)(cid:45)(cid:57)(cid:197)(cid:97)(cid:154)(cid:11)(cid:77)(cid:183)(cid:19)(cid:34)(cid:64)(cid:72)(cid:100)(cid:77)(cid:180)(cid:93)(cid:151)(cid:143)(cid:183)(cid:31)(cid:130)(cid:135)(cid:8)(cid:183)
`
`International
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`Domain
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`
`23¢567890QPFXQPF0987 65 43
`(cid:18)(cid:54)(cid:44)(cid:28)(cid:54)(cid:31)(cid:32)(cid:54)(cid:36)(cid:54) (cid:38)(cid:54)(cid:28)(cid:13)(cid:183)(cid:57)(cid:54)(cid:42)(cid:12)(cid:57)(cid:54)(cid:18)(cid:1)(cid:14)(cid:29)(cid:183)(cid:26)(cid:24)(cid:23)(cid:22)(cid:183)(cid:24)(cid:206)(cid:23)(cid:54)
`23¢567890QPWQPFI9376543
`(cid:17)(cid:54)(cid:24)(cid:3)(cid:16)(cid:54)(cid:31)(cid:34)(cid:54)(cid:37)(cid:54)(cid:38)(cid:54)(cid:40)(cid:239)(cid:27)(cid:239)(cid:8)(cid:7)(cid:2)(cid:8)(cid:7)(cid:36)(cid:8)(cid:54)(cid:29)(cid:183)(cid:39)(cid:239)(cid:36)(cid:54)(cid:33)(cid:54)(cid:45)(cid:54)(cid:27)(cid:54)(cid:25)(cid:54)
`
`JSCN "7-246053-9
`(cid:62)(cid:90)(cid:41)(cid:76)(cid:206) (cid:42)(cid:36)(cid:1)(cid:17)(cid:28)(cid:35)(cid:30)(cid:24)(cid:4)(cid:54)
`ISBN 0-07.: I‘M-44:3 (ISIS)
`(cid:63)(cid:91)(cid:42)(cid:77)(cid:206)(cid:203)(cid:12)(cid:22)(cid:23)(cid:32)(cid:25)(cid:14)(cid:29)(cid:5)(cid:89)(cid:52)(cid:6)(cid:206)
`
`WMislics: 6?!th A June:
`(cid:96)(cid:153)(cid:145)(cid:43)(cid:239)(cid:58)(cid:177)(cid:44)(cid:212)(cid:151)(cid:239)(cid:47)(cid:239)(cid:67)(cid:189)(cid:144)(cid:239)
`Senior msoring «dim: Cadiz: Imam
`(cid:34)(cid:55)(cid:117)(cid:83)(cid:125)(cid:134)(cid:183)(cid:46)(cid:47)(cid:10)(cid:11)(cid:40)(cid:27)(cid:34)(cid:45)(cid:2)(cid:52)(cid:19)(cid:16)(cid:24)(cid:32)(cid:6)(cid:52)(cid:51)(cid:206)(cid:234)(cid:138)(cid:239)(cid:95)(cid:181)(cid:239)
`Dcvclopmcnlalcdiwc: Midwife L. Fu’mflt‘M
`(cid:23)(cid:177)(cid:56)(cid:96)(cid:125)(cid:127)(cid:110)(cid:55)(cid:122)(cid:96)(cid:42)(cid:96)(cid:183)(cid:83)(cid:77)(cid:104)(cid:140)(cid:149)(cid:32)(cid:183)(cid:79)(cid:168)(cid:178)(cid:216)(cid:239)(cid:34)(cid:35)(cid:239)(cid:16)(cid:14)(cid:15)(cid:36)
`Eucusisc marketing manager; John “(2Mer
`(cid:52)(cid:196)(cid:124)(cid:114)(cid:188)(cid:181)(cid:135)(cid:191)(cid:121)(cid:206)(cid:16)(cid:115)(cid:146)(cid:114)(cid:94)(cid:183)(cid:30)(cid:14)(cid:34)(cid:13)(cid:21)(cid:18)(cid:39)(cid:4)(cid:54)(cid:7)(cid:36)(cid:23)(cid:33)(cid:54)(cid:110)(cid:137)(cid:183)(cid:136)(cid:194)(cid:239)
`Senior pmij manager: Rme Koo:
`(cid:33)(cid:55)(cid:117)(cid:83)(cid:125)(cid:136)(cid:183)(cid:41)(cid:43)(cid:40)(cid:28)(cid:19)(cid:46)(cid:57)(cid:154)(cid:105)(cid:159)(cid:106)(cid:130)(cid:127)(cid:34)(cid:206)(cid:98)(cid:186)(cid:24)(cid:239)(cid:73)(cid:74)(cid:239)
`Production super visor: Mrn)‘ I- Name
`(cid:85)(cid:174)(cid:168)(cid:188)(cid:125)(cid:156)(cid:206)(cid:145)(cid:173)(cid:130)(cid:134) (cid:2)(cid:84)(cid:14)(cid:15)(cid:183)(cid:101)(cid:213) (cid:125)(cid:195)(cid:196)(cid:230)(cid:239)(cid:30)(cid:31)(cid:34)(cid:7)(cid:10)(cid:34)
`Media projecth iodi 1!: Human“:
`(cid:50)(cid:89)(cid:97)(cid:64)(cid:183)(cid:145)(cid:153)(cid:82)(cid:19)(cid:183)(cid:32)(cid:41)(cid:2)(cid:54)(cid:8)(cid:37)(cid:24)(cid:54) (cid:72)(cid:239)
`(cid:137)(cid:159)(cid:183)
`(cid:34)(cid:55)(cid:122)(cid:88)(cid:125)(cid:134)(cid:183) (cid:106)(cid:65)(cid:83)(cid:40)(cid:183)(cid:26)(cid:149)(cid:158)(cid:125)(cid:24)(cid:36)(cid:146)(cid:141)(cid:80)(cid:173)(cid:76)(cid:147)(cid:31)(cid:183)(cid:55)(cid:123) (cid:121)(cid:122)(cid:110)(cid:144)(cid:183)(cid:77)(cid:86)(cid:167)(cid:239)
`Senior HMS} technology jurduccr: map Meek
`Cooodinato r o! (instance Main; Kink 0. Nat!
`(cid:19)(cid:190)(cid:132) (cid:114)(cid:64)(cid:180)(cid:125) (cid:135) (cid:183)(cid:187)(cid:239)(cid:10)(cid:15)(cid:174)(cid:13)(cid:114)(cid:56)(cid:183)(cid:17)(cid:20)(cid:43)(cid:25)(cid:23)(cid:36)(cid:7)(cid:52)(cid:99)(cid:154)(cid:130)(cid:239)(cid:55)(cid:19)(cid:239)(cid:85)(cid:91)(cid:1)(cid:239)
`Owe: designer: Sheéfoh 8mm!
`(cid:46)(cid:127)(cid:206)(cid:77)(cid:16)(cid:155)(cid:134)(cid:94)(cid:18)(cid:147)(cid:4)(cid:34)(cid:100)(cid:150)(cid:215)(cid:239)(cid:48)(cid:49)(cid:221)(cid:239)
`Cm: image; DEC Alpha mimopmceyw th phaogmph. cum“? Midwei’ Davidson. Fianna Seam
`(cid:54)(cid:127)(cid:239)(cid:134)(cid:155)(cid:108)(cid:19)(cid:35)(cid:206)(cid:57)(cid:239)(cid:36)(cid:119)(cid:166)(cid:126)(cid:183)(cid:128)(cid:129)(cid:90)(cid:183)(cid:71)(cid:124)(cid:111)(cid:144)(cid:183)(cid:39)(cid:33)(cid:44)(cid:1)(cid:52)(cid:233)(cid:184)(cid:137)(cid:210)(cid:229)(cid:239)(cid:25)(cid:160)(cid:133)(cid:225)(cid:143)(cid:175)(cid:176)(cid:22)(cid:239)(cid:20)(cid:22)(cid:1)(cid:25)(cid:48)(cid:3)(cid:54)(cid:11)(cid:50)(cid:44)(cid:17)(cid:54)
`UniwrsiirNariom High Magnetic Firm We"):
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`CoonpOtSilu: Mariam Widen Cavnmm‘on
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`'Iypefacc 1002 7mm: Rmmm
`(cid:1)(cid:132)(cid:71)(cid:165)(cid:61)(cid:62)(cid:183)(cid:68)(cid:88)(cid:32)(cid:37)(cid:33)(cid:158)(cid:69)(cid:237)(cid:239)(cid:97)(cid:188)(cid:239)
`Printtr. mm Mm’d thr‘dl‘cht 8%
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`
`Library of Cong-t3; Cntalcging-ln-Publficatiou Dana
`(cid:75)(cid:157)(cid:118)(cid:203)(cid:207)(cid:239)(cid:191)(cid:239)(cid:20)(cid:125)(cid:118)(cid:77)(cid:11)(cid:142)(cid:148)(cid:183)(cid:38)(cid:130)(cid:107)(cid:117)(cid:118)(cid:113)(cid:3)(cid:182)(cid:112)(cid:132)(cid:182)(cid:180)(cid:109)(cid:131)(cid:4)(cid:56)(cid:171)(cid:67)(cid:109)(cid:106)(cid:66)(cid:162)(cid:103)(cid:183)(cid:90)(cid:128)(cid:239)
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`LeblebicL —3rd ed.
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`ISBN 047-24me — ISBN 0m." 964 4-7 035)
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`T3037 1 910/146 K36 2003
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`IN'I‘ERNA'I'IONA L EDITION ISBN M7-1I9644-7
`(cid:145)(cid:77)(cid:99)(cid:2)(cid:54)(cid:87)(cid:75)(cid:40)(cid:97)(cid:66)(cid:81)(cid:75)(cid:40)(cid:70)(cid:206)(cid:55)(cid:65)(cid:95)(cid:61)(cid:82)(cid:78)(cid:206) (cid:61)(cid:89)(cid:43)(cid:75)(cid:206)(cid:11)(cid:36)(cid:1)(cid:14)(cid:15)(cid:40)(cid:29)(cid:27)(cid:1)(cid:36)(cid:54)
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`(cid:104)(cid:239)(cid:113)(cid:131)(cid:164)(cid:87)(cid:125)(cid:66)(cid:163)(cid:98)(cid:137)(cid:134)(cid:35)(cid:181)(cid:109)(cid:183)(cid:9)(cid:16)(cid:24)(cid:31)(cid:25)(cid:38)(cid:35)(cid:52)(cid:4)(cid:43)(cid:52) (cid:159)(cid:83)(cid:138) (cid:182)(cid:151)(cid:103)(cid:1)(cid:142)(cid:136)(cid:153)(cid:201)(cid:113)(cid:152)(cid:122)(cid:206)(cid:146)(cid:158)(cid:206)(cid:75)(cid:110)(cid:131)(cid:206)(cid:40)(cid:164)(cid:165)(cid:177)(cid:114) (cid:36)(cid:37)(cid:17)(cid:206)
`
`www.mbhcoam
`(cid:180)(cid:180)(cid:180)(cid:10)(cid:103)(cid:79)(cid:82)(cid:10)(cid:51)(cid:183)
`
`Copyrighted Material
`(cid:3)(cid:25)(cid:28)(cid:19)(cid:17)(cid:18)(cid:34)(cid:12)(cid:11)(cid:36)(cid:5)(cid:10)(cid:33)(cid:12)(cid:30)(cid:19)(cid:10)(cid:23)(cid:36)
`
`

`

`CONTENTS
`
`
`
`PREFACE
`
`1
`
`INTRODUCTION
`
`3"
`1.1 ' Historical Perspective .
`1.2
`Objective and Organization of the Book
`' 1.3
`A Circuit Design Example
`
`2
`
`FABRICATION OF MOSFETs
`
`2. 1
`
`2.2
`2.3
`
`2.4
`2.5
`
`Introduction
`
`Fabrication Process Flow: Basic Steps
`The CMOS n.w’e11 Process
`
`Layout Design Rules
`Full—Custom Mask Layout Design
`References
`Exercise Problems
`
`3
`
`MOS TRANSISTOR
`
`3.1
`3.2
`3.3
`
`The Metal Oxide Semiconductor (MOS) Structure
`The MOS System under External Bias
`Structure and Operation of MOS
`Transistor (MOSFET)
`3.4 MOSFET Current-Voltage Characteristics
`3.5 MOSFET Scaling and Small-Geometry Effects
`3.6 MOSFET Capacitances
`References
`Exercise Problems
`
`xi
`
`(Jr
`
`20
`
`20
`21
`29
`37
`40
`'44
`45
`
`47
`
`48
`52
`
`55
`66
`81
`97
`110
`111
`
`

`

`vi~
`
`Contents
`
`MODELING OF MOS TRANSISTORS
`USING SPICE
`
`‘
`Basic Concepts
`4.1
`The LEVEL 1 Model Equations
`4.2
`4.3 \ The LEVEL 2 Model Equations
`4.4
`The LEVEL 3 Model Equations
`4.5
`Capacitance Models
`4.6
`Comparison of the SPICE MOSFET Models
`References
`A
`
`Appendix: Typical SPICE Model Parameters
`Exercise Problems
`
`MOS INVERTERS: STATIC CHARACTERISTICS
`
`5. 1
`5.2
`
`5.3
`5.5
`
`Introduction
`Resistive-Load Inverter
`
`Inverters with n-Type MOSFET Load
`CMOS Inverter
`References
`Exercise Problems
`
`MOS INVERTERS: SWITCHING CHARACTERISTICS
`AND INTERCONNECT EFFECTS
`
`6. 1
`
`6.2
`6.3
`6.4
`6.5
`
`6.6
`6.7
`
`Introduction
`
`Delay-Time Definitions
`Calculation of Delay Times
`Inverter Design with Delay Constraints
`Estimation of Interconnect Parasitics
`
`Calculation of Interconnect Delay
`Switching Power Dissipation of CMOS Inverters ‘
`References
`
`Appendix: Super Buffer Design
`Exercise Problems
`
`COMBINATIONAL MOS LOGIC CIRCUITS
`
`7. 1
`
`Introduction
`
`7.2 MOS Logic Circuits with Depletion nMOS Loads
`7.3
`CMOS Logic Circuits
`7.4
`C0mplex Logic Circuits
`7.5
`CMOS Transmission Gates (Pass Gates)
`References
`Exercise Problems
`
`117
`
`118
`119
`123
`130
`131
`135
`137
`138
`139
`
`141
`
`141
`149
`160
`. 172
`
`190
`191
`
`196
`
`196
`198
`200
`210
`222
`234
`242
`250
`251
`254
`
`259
`
`259
`260
`274
`281
`295
`305
`306
`
`

`

`vii
`
`Contents
`
`SEQUENTIAL MOS LOGIC CIRCUITS
`
`8.1
`8.2
`8.3
`8.4
`8.5
`
`Introduction
`
`Behavior of Bistable Elements
`The SR Latch Circuit
`
`Clocked Latch and Flip-Flop Circuits
`CMOS D-Latch and Edge—Triggered Flip-Flop
`Appendix: Schmitt Trigger Circuit
`Exercise Problems
`
`DYNAMIC LOGIC CIRCUITS
`
`9.
`
`9.2
`9.3
`9.4-
`9.5
`
`Introduction
`
`Basic Principles of Pass Transistor Circuits
`Voltage Bootstrapping
`Synchronous Dynamic Circuit Techniques
`High-Performance Dynamic CMOS Circuits
`References
`‘
`Exercise Problems
`
`10
`
`SEMICONDUCTOR MEMORIES
`
`10.1
`10.2
`10.3
`10.4
`
`Introduction
`
`Read—Only Memory (ROM) Circuits
`Static Read-Write Memory (SRAM) Circuits
`Dynamic Read-Write Memory (DRAM) Circuits
`References
`Exercise Problems '
`
`11
`
`LOW-POWER CMOS LOGIC CIRCUITS
`
`11.1
`
`11.2
`11.3
`11.4
`11.5
`11.6
`
`Introduction
`
`Overview of Power Consumption
`Low-Power Design Through Voltage Scaling
`Estimation and Optimization of Switching Activity
`Reduction of Switched Capacitance
`Adiabatic Logic Circuits
`References
`
`Exercise Problems _
`
`12
`
`BiCMOS LOGIC CIRCUITS
`
`12.1
`
`Introduction
`
`'
`
`12.2 Bipolar Junction Transistor (BJT):
`Structure and Operation
`
`312 '
`
`312
`314
`320
`326
`i 334
`341
`345
`
`350
`
`350
`352
`365
`368
`378
`395
`396
`
`402
`
`402
`405
`417
`435
`447
`447
`
`I 451
`
`451
`452
`463
`474
`480
`482
`489
`490
`
`491
`
`491
`
`494
`
`

`

`viii
`
`Contents
`
`‘ 12.3
`12.4
`12.5
`12.6
`
`Dynamic Behavior of BJTs
`Basic BiCMOS Circuits: Static Behavior
`
`SWitching Delay in BiCMOS Logic Circuits
`BiCMOS Applications
`References
`Exercise Problems
`
`13-
`
`CHIP INPUT AND OUTPUT (I/O) CIRCUITS
`
`13.1
`13.2
`
`Introduction
`ESD Protection
`
`13.3_\
`13.4 ‘
`13.5
`13.6
`
`Input Circuits
`Output Circuits and L(di/dt) Noise
`On-Chip Clock Generation and Distribution
`Latch-Up and Its Prevention
`References
`Exercise Problems
`
`14
`
`VLSI DESIGN METHODOLOGIES
`
`14.1
`1 14.2
`14.3
`14.4
`14.5
`14.6
`14.7
`14.8
`
`Introduction
`
`VLSI Design Flow
`Design Hierarchy
`Concepts of Regularity, Modularity and Locality
`VLSI Design Styles
`Design Quality
`Packaging Technology
`Computer-Aided Design Technology
`References
`Exercise Problems
`
`15
`
`. DESIGN FOR MANUFACTURABILITY
`
`15.1
`15.2
`15.3
`15.4
`15.5
`15.6
`15.7
`15.8
`
`Introduction
`Process Variations
`
`Basic Concepts and Definitions
`Design of Experiments and Performance Modeling
`Parametric Yield Estimation
`Parametric Yield Maximization
`
`Worst-Case Analysis
`Performance Variability Minimization
`References
`
`I Exercise Problems
`
`509
`516
`519
`
`524 y
`529 ‘
`530
`
`534
`
`534
`535
`538
`543
`549
`555
`562
`563
`
`566
`
`566
`569
`/ 570
`573
`576
`586
`589
`592
`593
`594
`
`598
`
`598
`599
`601
`608
`615
`621
`622
`628
`633
`633
`
`

`

`<16
`
`DESIGN FOR TESTABILITY
`
`16.1
`16.2
`16.3
`16.4
`16.5
`16.6
`16.7
`
`Introduction
`
`V
`
`Fault Types and Models
`Controllability and Observability
`Ad Hoc Testable Design Techniques
`Scan-Based Techniques
`Built-In Self Test (BIST) Techniques
`Current Monitoring IDDQ Test
`References
`Exercise Problems
`
`'
`
`QINDEX
`
`ix
`
`Contents
`
`638
`
`638
`638
`642
`644
`646
`648
`65 1
`653
`653
`
`655
`
`

`

`ABOUTTHE AUTHORS
`
`
`
`Sung-Mo (Steve) Kang received the Ph.D.‘ degree in electrical engineering from the
`University of California at Berkeley. He has worked on CMOS VLSI design at AT&T
`Bell Laboratories at Murray Hill, NJ. as supervisor and member of technical staff of
`high-end CMOS VLSI microprocessor design. Currently, he is professor and head of the
`department of electrical and computer engineering at the University of Illinois at Urbana-
`Champaign. He was the founding editor-in-chief of the IEEE Transactions on Very Large
`Scale Integration (VLSI) Systems and has served on editorial boards of several IEEE and
`international journals: He has received a Humboldt Research Award for Senior US
`Scientists, IEEE Graduate Teaching Technical Field Award, IEEE Circuits and Systems
`Society Technical Achievement Award, SRC Inventor Recognition Awards, IEEE CAS
`Darlington Prize Paper Award and other best paper awards. He has also co-authored
`DesignAutomationfor Timing-Driven Layout Synthesis, Hot- CarrierReliability ofMOS
`VLSI Circuits, Physical Design for Multichip Modules, and Modeling of Electrical
`Overtstress in Integrated Circuits from Kluwer Academic Publishers, and Computer'-
`Aided Design of Optoelectronic Integrated Circuits and Systems from Prentice Hall.
`
`Yusuf Leblebici received the Ph.D. degree in electrical and computer engineering
`from the University of Illinois at Urbana-Champaign. He was a visiting assistant
`professor of electrical and computer engineering at the University of Illinois at Urbana- ,
`Champaign,‘ associate professor of electrical and electronics engineering at Istanbul.
`Technical University, and invited professor of electrical engineering at the Swiss
`Federal Institute of Technology in Lausanne, Switzerland. Currently, he is an associate
`professor of electrical and computer engineering at Worcester Polytechnic Institute.
`Dr. Leblebici is also a member of technical staff at the New England Center for
`Analog and Digital Integrated Circuit Design. His research interests include high-
`performance digital integrated circuit architectures, modeling and simulation of semi-
`conductor devices, computer-aided design of VLSI circuits, and VLSI reliability analy-
`sis. He has received a NATO Science Fellowship Award, has been an Honors Scholar
`of the Turkish Scientific and Technological Research Council, and has received the
`Young Scientist Award of the same council. Dr. Leblebici has co-authored about fifty
`technicalpapers and two books.
`‘
`
`

`

`. PREFACE
`
`Complementary metal oxide semiconductor (CMOS) digital integrated circuits are the
`enabling technology for the modern information age. Because of their intrinsic features
`in low-power consumption, large noise margins, and ease of design,CMOS integrated L
`circuits have been widely used to develop random access memory (RAM) chips,
`microprocessor chips, digital signal processor (DSP) chips, and application- specific
`integrated circuit (ASIC) chips. The popular use of CMOS circuits will grow with the
`increasing demands for low-power, low-noise integrated electronic systems in the
`development of portable computers, personal digital assistants (PDAs), portable phones,
`and multimedia agents.
`>
`p
`‘
`Since the field of CMOS integrated circuits alone is very broad, it is conventionally
`divided into digital CMOS circuits and analog CMOS circuits. This book is focused on
`the CMOS digital integrated circuits. At the University of Illinois at Urbana-Champaign, '
`we have tried some of the available textbooks on digital MOS integrated circuits for our
`senior-level technical elective course, ECE382' ~ Large 'Scale Integrated Circuit Design.
`Students and instructors alike realized, however, that=there was a need for a new book with
`more comprehensive treatment of CMOS digital circuits. Thus, our textbook project was
`initiated several years ago by assembling our own lecture notes. Since 1993, we have used
`evolving versions of this material at the University of Illinois at Urbana-Champaig-n, at
`Istanbul Technical University and at the Swiss Federal Institute Of Technology in
`‘Lausanne. Both authors were very much encouraged by comments from their students,
`colleagues, and reviewers. ' The first edition of CMOS Digital Integrated ‘ Circuits:
`Analysis and Design was published in‘ late 1995.
`
`

`

`xii
`
`Preface
`
`Soon after publishing the first edition, we saw the need for updating the it to reflect
`many constructive comments from instructors and students who used the textbook, to
`include the topic of low-power circuit design and provide more rigorous treatment of
`interconnects in high-speed circuit design as well as the deep submicron circuit design
`issues. We also felt that in a very rapidly developing field such as CMOS digital circuits,
`the quality of a textbook can only be preserved by timely updates reflecting the current
`State-of-the-art. This realization has led us to embark on the extensive project of revising
`our work, to reflect recent advances in technology and in circuit design practices.
`This book, CMOS Digital Integrated Circuits: Analysis and Design, is primarily
`intended as a comprehensive textbook at the senior level and first-year graduate level, as
`well as a reference for practicing engineers inthe areas of integrated circuit design, digital
`design, and VLSI. Recognizing that the area of digital integrated circuit design is
`evolving at an increasingly faster pace, we have made éverypossible effort to present up-
`to-date materials on all subjects covered. This book ’contains sixteen chapters; and we
`recognize that it would not be possible to cover rigorously all of this material in one
`semester. Thus, we would propose the following based on our teaching experience: At
`the undergraduate level, coverage of the first ten chapters would constitute sufficient
`material for a one-semester course on CMOS digital integrated circuits. Time permitting,
`some selected topics in Chapter 11, Low-Power CMOS Logic Circuits, Chapter 12,
`BiCMOS Logic Circuits and Chapter 13, Chip Input and Output (I/0) Circuits can also
`be covered. Alternatively, this book can be used for a two-semester course, allowing a
`more detailed treatment of advanced issues, which are presented in the later chapters. At
`the graduate level, selected topics from the first eleven chapters plus the last five chapters
`can be covered in one semester.
`‘
`The first eight chapters of this book are devoted to a detailed treatment of the MOS
`transistor with all its relevant aspects; to the static and dynamic operation principles,
`analysis and design of basic inverter circuits; and to the structure and operation of
`combinational and sequential logic gates. The issues of on-chip interconnect modeling
`‘ and interconnect delay calculation are covered extensively in Chapter 6. Indeed, Chapter
`~ 6 has been significantly extended to provide a more complete view of switching
`characteristics in digital integrated circuits. The coverage of technology-related issues
`has been complemented with the addition of several color plates and graphics, which we
`hope will also enhance the educational value of the text. A separate chapter (Chapter 9)
`has been reserved for the treatment of dynamic logic circuits Which are used in state-of-
`the-art VLSI chips. Chapter 10 offers an in-depth presentation of semiconductor memory
`circuits.
`ReCognizing the increasing importance of low-power circuit design, we decided to
`r add a new chapter (Chapter 11) on low-power CMOS logic circuits. This new chapter
`provides a comprehensive coverage of methodologies and design practices that are used
`to reduce the power dissipation of large-scale digital integrated circuits. BiCMOS digital
`circuit design is examined in Chapter 12, with a thorough coverage of bipolar transistor
`basics. Considering the on- going use of bipolar circuits and BiCMOS circuits, we believe
`that at least one chapter should be allocated to cover the basics of bipolar transistors. Next,
`Chapter 13 provides a clear insight into the important subject of ch

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