(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2002/0145156 A1
`(43) Pub. Date: Oct. 10, 2002
`
`Igarashi et al.
`
`US 20020145156A1
`
`(54) SEMICONDUCTOR DEVICE AND METHOD
`FOR MANUFACTURING THE SAME
`
`Publication Classification
`
`(75)
`
`Inventors: Motoshige Igarashi, Tokyo (JP);
`Hiroyuki Amishiro, Tokyo (JP)
`
`Correspondence Address:
`McDermott, Will & Emery
`600 13th Street, NW.
`Washington, DC 20005-3096 (US)
`
`(73) Assignee: MITSUBISHI DENKI KABUSHIKI
`KAISHA
`
`(21) Appl. No.:
`
`09/971,958
`
`(22)
`
`Filed:
`
`Oct. 9, 2001
`
`(30)
`
`Foreign Application Priority Data
`
`Apr. 6, 2001
`
`(JP) .................................... .. 2001-108720
`
`1m.c1.7 ....................... .. H01L 29/80; H01L 31/112
`(51)
`(52) 11.8.0.
`............................................................ ..257/262
`
`(57)
`
`ABSTRACT
`
`To provide a semiconductor device with reduced parasitic
`capacity in the vicinity of gate electrodes, and a method for
`manufacturing such a semiconductor device. The semicon-
`ductor device comprises a gate electrode formed on a silicon
`semiconductor substrate 1 through a gate oxide film, and a
`pair of impurity diffusion layers formed on the surface
`region of the silicon semiconductor substrate at both sides of
`the gate electrode. A silicon nitride film acting as a sidewall
`spacer is formed so as to cover the sidewall of the gate
`electrode, and the silicon nitride film is allowed to extend to
`the surface of the silicon semiconductor substrate 1 in the
`
`vicinity of the gate electrode in a substantially L-shaped
`profile.
`
`
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`Patent Application Publication Oct. 10, 2002 Sheet 1 0f 12
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`Patent Application Publication
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`Patent Application Publication Oct. 10, 2002 Sheet 10 0f 12
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`Patent Application Publication Oct. 10, 2002 Sheet 11 0f 12
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`Patent Application Publication Oct. 10, 2002 Sheet 12 0f 12
`
`US 2002/0145156 A1
`
`Fig. 18
`
`PRIOR ART
`
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`

`US 2002/0145156 A1
`
`Oct. 10, 2002
`
`SEMICONDUCTOR DEVICE AND METHOD FOR
`MANUFACTURING THE SAME
`
`BACKGROUND OF THE INVENTION
`
`[0001]
`
`1. Field of the Invention
`
`[0002] The present invention relates to a semiconductor
`device, and a method for manufacturing the semiconductor
`device, specifically to the gate structure of an MOS transis—
`tor and the contact structure that contains gate wirings and
`LIC (local interconnect).
`
`[0003]
`
`2. Background Art
`
`[0004] Concurrent with the size reduction of semiconduc-
`tor elements, the margin of the areas for forming contacts
`from the upper layer to the substrate also tends to decrease.
`Therefore, in order to prevent the occurrence of electrical
`short-circuiting from the element-isolating end to the sub-
`strate when a contact is out of an active region, methods for
`forming contacts known as a borderless contact structure or
`a self align contact structure (hereafter referred to as SAC
`structure) are positively adopted.
`
`In the SAC structure, materials that have an etching
`[0005]
`selection ratio with a silicon oxide film often used as an
`interlayer insulating film are required. An example of such
`materials is silicon nitride film. Thcrcforc silicon nitride
`
`films are often used in the vicinity of the gate electrodes of
`MOS transistors of an SAC structure.
`
`[0006] FIG. 16 is a schematic sectional view that shows
`the configuration of an MOS transistor of an SAC structure.
`This MOS transistor is composed of a gate electrode 103
`formed on a silicon semiconductor substrate 101 through a
`gate oxide film 102, and a pair of impurity diffusion layers
`104 formed on the surface region of the silicon semicon-
`ductor substrate 101 at the both sides of the gate electrode
`103. Here, the gate electrode 103 has a salicide structure
`consisting of a lower-layer polysilicon film 103:; and an
`upper-layer silicide film 103b. Another silicide film 105 is
`formed on the surface layers of the impurity diffusion layers
`104 by salicide forming.
`
`[0007] Asidewall spacer 107 is formed on the sidewall of
`the gate electrode 103. Asilicon nitride film 108 is formed
`so as to cover the surface of each of the sidewall spacer 107,
`the silicide film 105, and the silicide film 10313. The silicon
`nitride film 108 functions as the etching stopper film for
`inhibiting the contact hole from reaching the gate electrode
`103 or the clement-isolating end, even if the contact hole of
`the contact electrode 106 connected to the impurity diffusion
`layers 104 is misaligned.
`
`In such a conventional MOS transistor of the SAC
`[0008]
`structure, the places where the silicon nitride film is used
`include 1) the sidewall spacer 107 of the transistor gate, and
`2) the etching stopper film 108 for preventing junction
`leakage or wiring short-circuiting when the contact hole,
`LIC wirings, and the like are disposed in the vicinity of the
`element-isolating film or the gate electrode 103.
`
`[0009] However, since the dielectric constant of the silicon
`nitride film is as high as twice the dielectric constant of the
`silicon oxide film or higher, the silicon nitride film increases
`the capacity between the gate electrode 103 and the impurity
`diffusion layers 104 such as the source/drain, the capacity
`between the gate electrodes 103 of the transistors adjacent to
`
`each other, the capacity between the gate electrode 103 and
`the contact electrode 106, and the capacity between the gate
`electrode 103 and the LIC wiring. Increase in capacity is
`particularly significant when the LIC wirings are formed in
`parallel along the transistor gate in order to lower resistance
`with the source or the drain.
`
`[0010] FIG. 17 is a schematic diagram showing the gate
`overlapping capacity in each generation. It is seen from
`FIG. 17 that with each succeeding generation, the propor-
`tion of the capacity between the gate electrode and the
`contact (C2) increases in comparison with the capacity
`between the gate electrode and the diffused layer (C1). The
`reasons are decrease in pitch of gate electrodes or the
`distance between the gate electrode and the contact hole
`with down sizing, and increase in the proportion of the
`nitride film occupying the insulating film in the vicinity of
`the gate resulting in the elevation of effective dielectric
`constant. Increase in such parasitic capacity has interfered
`with advantages due to down sizing such as high speed and
`low power consumption.
`
`[0011] Furthermore, as FIG. 18 shows, when the pitch of
`transistors is shortened, a problem of dilliculty of forming
`silicide on the impurity diffusion layer 104 surrounded by
`the sidewall spacer 107 arises. This is because the formation
`of a refractory metal layer is difficult by methods such as
`sputtering, since the sidewall spacer 107 fills the space
`between gate electrodes 103. Also, a problem in which the
`stress of the nitride film inhibits the growth of silicide
`between gate electrodes arises. As a result, silicide resistance
`rises, inhibiting the high-speed operation of the device.
`
`[0012] On the other hand, since a contact hole that con-
`nects a gate electrode and an impurity diffusion layer simul-
`taneously (hereafter referred to as a shared contact) can
`reduce the memory cell size, it is used in memories that
`require high integration, such as SRAM cells. FIG. 19 is a
`schematic sectional view showing an example of an MOS
`transistor that has a shared contact electrode 114. Since a
`shared contact is characterized in a structure to connect a
`gate electrode at the upper portion of the electrode, it can
`connect a gate electrode and an impurity diffusion layer
`simultaneously without adding a special mask or an ion
`implantation step.
`
`[0013] However, when a sidewall spacer 107 or an etching
`stoppcr film 108 as shown in FIGS. 16 and 18 is used, the
`portions of the sidewall spacer 107 and the etching stopper
`film 108 cannot contribute to connection to at
`least an
`impurity diffusion layer 105 as FIG. 19 shows. Therefore,
`the shared contact cannot be scaled to meet the requirements
`of down sizing, as FIG. 19 shows, the size reduction and
`high integration of memory cells cannot be achieved.
`
`[0014] Furthermore, with decrease in the width Lg of the
`gate electrode 103 of a transistor, problems of increased
`wiring resistance and unstable resistance when silicide is
`formed arise.
`
`SUMMARY OF THE INVENTION
`
`In order to solve the above-described problems, the
`[0015]
`first object of the present invention is to achieve the further
`reduction of parasitic capacity in the vicinity of the gate
`electrode.
`
`

`

`US 2002/0145156 A1
`
`Oct. 10, 2002
`
`[0016] The second object of the present invention is to
`provide a semiconductor device that has a low-resistance
`silicide layer between gates even if the pitch of the gate is
`reduced.
`
`invention is to
`[0017] The third object of the present
`inhibit
`the occurrence of defective junction leakage and
`increased contact resistance by optimizing shapes of respec-
`tive films constituting a gate.
`
`[0018] The fourth object of the present invention is to
`further reduce the diameter of shared contacts.
`
`invention is to
`[0019] The fifth object of the present
`provide a semiconductor device that has a low—resistance
`gate electrode even if the size of memory cells is reduced,
`and the gate width is narrowed.
`
`[0020] According to one aspect of the present invention, a
`semiconductor device comprises a gate electrode formed on
`a semiconductor substrate through a gate insulating film, a
`pair of impurity diifusion layers formed on the surface
`region of the semiconductor substrate at both sides of the
`gate electrode, and a first insulating film formed so as to
`cover the sidewalls of the gate electrode. The first insulating
`film extends to the surface area of the semiconductor sub-
`
`strate in the vicinity of the gate electrode.
`
`[0021] According to another aspect of the present inven-
`tion, a method for manufacturing a semiconductor device
`comprises the following steps. Firstly a gate electrode is
`formed on a semiconductor substrate through a gate insu-
`lating film. Secondly a first insulating film is formed so as
`to cover the top surface and the sides of the gate electrode,
`and the surface the semiconductor substrate. Thirdly an
`etching mask film for etching the first insulating film is
`formed on the first insulating film. Fourthly the etching mask
`film is removed except from the side of the gate electrode by
`anisotropic etching, and the first insulating film is removed
`by continuing the etching using the etching mask film
`remaining on the sidewalls of the gate electrode as the mask,
`therefore the first insulating film which has a configuration
`to extend from the sidewalls of the gate electrode to the
`surface area of the semiconductor substrate underneath the
`
`remaining etching mask film is made. Fifthly the etching
`mask film is removed. Sixthly a second insulating film is
`formed on the surface of the semiconductor substrate, so as
`to cover the gate electrode and the semiconductor substrate.
`
`[0022] According to the present invention, since the side-
`wall spacer is produced by forming a first insulating film
`having an L-shaped cross section so as to extend from the
`sidewalls of gate electrodes to the surface of the semicon-
`ductor substrate, the thickness and volume of the sidewall
`spacer in the lateral direction of the gate electrodes can be
`minimized, and parasitic capacities between gate electrodes
`and between the gate electrode and the contact electrode can
`be reduced.
`
`[0023] Other and further objects, features and advantages
`of the invention will appear more fully from the following
`description.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0025] FIG. 2 is a schematic sectional view showing the
`details of dimensions of each film constituting the periphery
`of a gate electrode in the semiconductor device of FIG. 1;
`
`[0026] FIG. 3 is a schematic sectional View showing a
`comparative example for illustrating the effect of the semi-
`conductor device according to First Embodiment;
`
`[0027] FIG. 4 is a schematic sectional view showing
`another comparative example for illustrating the effect of the
`semiconductor device according to First Embodiment;
`
`[0028] FIGS. 5A to SE are schematic sectional Views
`showing the sequence of steps for manufacturing the semi-
`conductor device according to First Embodiment;
`
`[0029] FIG. 6 is a schematic sectional view showing a
`semiconductor device according to Second Embodiment of
`the present invention;
`
`[0030] FIG. 7 is a schematic sectional view showing
`another semiconductor device according to Second Embodi-
`ment of the present invention;
`
`[0031] FIGS. 8A to 8D are schematic sectional views
`showing still another semiconductor device according to
`Second Embodiment of the present invention;
`
`[0032] FIG. 9 is a schematic sectional view showing a
`semiconductor device according to Third Embodiment of
`the present invention;
`
`[0033] FIG. 10 is a schematic sectional View showing a
`semiconductor device according to Fourth Embodiment of
`the present invention;
`
`[0034] FIGS. 11A to 11C are schematic sectional Views
`showing the sequence of steps for manufacturing the semi-
`conductor device according to Fourth Embodiment;
`
`[0035] FIG. 12 is a schematic sectional view showing a
`semiconductor device according to Fifth Embodiment of the
`present invention;
`
`[0036] FIGS. 13A and 13B are schematic sectional views
`showing the sequence of steps for manufacturing the semi-
`conductor device according to Fifth Embodiment;
`
`[0037] FIG. 14 is a schematic sectional view showing a
`semiconductor device according to Sixth Embodiment of the
`present invention;
`
`[0038] FIGS. 15A and 15B are schematic sectional views
`showing the sequence of steps for manufacturing the semi-
`conductor device according to Sixth Embodiment;
`
`[0039] FIG. 16 is a schematic sectional View showing the
`configuration of a conventional MOS transistor of an SAC
`structure;
`
`[0040] FIG. 17 is a schematic diagram showing the gate
`overlapping capacity in each generation;
`
`[0041] FIG. 18 is a schematic sectional view showing the
`configuration of another conventional MOS transistor of an
`SAC structure; and
`
`[0024] FIG. 1 is a schematic sectional view showing a
`semiconductor device according to First Embodiment of the
`present invention;
`
`[0042] FIG. 19 is a schematic sectional view showing the
`configuration of another conventional MOS transistor of an
`SAC structure.
`
`

`

`US 2002/0145156 A1
`
`Oct. 10, 2002
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`[0043] First Embodiment
`
`[0044] FIG. 1 is a schematic sectional view showing a
`semiconductor device according to First Embodiment of the
`present invention. The configuration of the semiconductor
`device of First Embodiment will be described below refer-
`
`ring to FIG. 1. The semiconductor device of First Embodi—
`ment is an example of MOS transistors of an SAC structure
`to which the present invention is applied, and comprises a
`gate electrode 3 formed on a silicon semiconductor substrate
`1 through a gate oxide film 2; a pair of impurity diffusion
`layers 4 of source/drain diffused layers formed on the
`surface region of the silicon semiconductor substrate 1 in the
`both sides of the gate electrode 3; a silicide film 5 formed on
`the surface of the impurity diffusion layers 4; and a contact
`electrode 6 electrically connected to the silicide film 5.
`
`[0045] Silicon nitride films 7 are formed on the sidewalls
`of the gate electrode 3. These silicon nitride films 7 are
`formed so as to extend from the sidewalls of the gate
`electrode 3 to the surface of the silicon semiconductor
`
`substrate 1, and have substantially L-shaped cross section
`along the direction perpendicular to the direction of the gate
`electrode 3 as FIG. 1 shows.
`
`[0046] The gate electrode 3 has a salicide structure con-
`sisting of two layers, a polysilicon film 3a and a silicide film
`3b such as titanium silicide (TiSiZ). The silicide film 5 on the
`impurity diffusion layer 4 and the silicide film 3b constitutes
`the upper portion of the gate electrode 3 is formed in the
`same step by salicidation.
`
`[0047] Asilicon nitride film 8 is formed so as to cover the
`gate electrode 3 and the surface of the silicon semiconductor
`substrate 1. The silicon nitride film 8 is a film that functions
`
`as an etching stopper film when forming the contact hole of
`the contact electrode 6 that reaches the impurity diffusion
`layer 4, and inhibits the contact hole to reach the gate
`electrode 3 or the element-isolating end even if the mask is
`misaligned to some extent when the contact hole is formed.
`
`In the area where silicon nitride films 7 are formed,
`[0048]
`the silicon nitride film 8 covers the sidewall of the gate
`electrode 3 or the surface of the silicon semiconductor
`
`the
`substrate 1 through the silicon nitride films 7. Also,
`silicon nitride film 8 is formed so as to cover the surface of
`
`the silicide film 3b on the gate electrode 3, and the surface
`of the silicide film 5 on the impurity diffusion layer 4.
`
`In the semiconductor device of First Embodiment,
`[0049]
`the silicon nitride film 7 formed on the sidewall of the gate
`electrode 3 functions as a sidewall spacer, and when the
`LDD structure of an MOS transistor is formed as described
`later, the silicon nitride film 7 becomes a mask for forming
`a high—concentration impurity diffusion layer 4b. As FIG. 1
`shows, since the silicon nitride film 7 as a sidewall spacer is
`formed in a substantially uniform thickness so as to cover on
`the sidewall of the gate electrode 3 and the specific range the
`surface of the silicon semiconductor substrate 1, the thick-
`ness and volume of the silicon nitride film 7, particularly
`present on the sides of the gate electrode 3, can be signifi-
`cantly reduced. At the same time,
`the expansion of the
`silicon nitride film 8 formed on the silicon nitride film 7 in
`the lateral direction can be inhibited, minimizing also the
`thickness and volume of the silicon nitride film 8 on the
`
`sides of the gate electrode 3. Thus, the parasitic capacity
`produced between the gate electrode 3 and the contact
`electrode 6, or between gate electrodes 3 adjacent to each
`other can be minimized by decreasing the volume occupied
`by the silicon nitride film of a high dielectric capacity in the
`sidewalls of the gate electrode 3.
`
`[0050] FIG. 2 is a schematic sectional view showing the
`details of dimensions of each film constituting the periphery
`of a gate electrode 3 in the semiconductor device of FIG. 1.
`In First Embodiment, as FIG. 2 shows, the configuration of
`the sidewall spacer of the gate electrode 3 of the MOS
`transistor is determined so as to satisfy the following for-
`mula by constituting the sidewall spacer with the silicon
`nitride film 7, which has a dielectric constant higher at least
`than the dielectric constant of a silicon oxide film (e=3.9) as
`an insulating material:
`T5w§2de
`
`[0051] where Td is the thickness of the silicon nitride film
`7 on the sides of the gate electrode 3 and the surface of the
`silicon semiconductor substrate 1, and Tsw is the length
`(width) of the silicon nitride film 7 that extends horizontally
`on the silicon semiconductor substrate 1 from the sides of
`
`the gate electrode 3 toward the impurity diifusion layer 4.
`
`[0052] Thus, the volume of the silicon nitride film 7 on the
`sides of the gate electrode 3 can be minimized by reducing
`the thickness of the silicon nitride film 7 on the sides of the
`
`gate electrode 3 to 1/z or less the length in the horizontal
`direction (=Td) of the silicon nitride film 7 on the surface of
`the silicon semiconductor substrate 1. Since the thickness of
`
`the sidewall spacer on the sides of the gate electrode 3 can
`be reduced, the parasitic capacity mainly between the gate
`electrodes 3 adjacent to each other, and between the gate
`electrode 3 and the contact electrode 6 can be minimized.
`
`In the structure of FIG. 2, the silicon nitride film 7
`[0053]
`as a sidewall spacer can be substituted by a dual-layer film
`or multi-layer film consisting of silicon nitride and silicon
`oxide films. In the case of the structure that contains a silicon
`
`nitride film in the sidewall spacer, stress with the gate
`electrode 3 can be relieved by reducing the constituting ratio
`of the silicon nitride film.
`
`[0054] Also in the semiconductor device of First Embodi-
`ment, as FIG. 2 show, the configuration of the silicon nitride
`film 8 as a etching stopper film is preferably a device
`configuration that satisfies:
`Tb<TLz, Tb<Tc,
`
`[0055] where Ta represents the thickness of the silicon
`nitride film 8 on the surface of the gate electrode 3, Tb
`represents the thickness of the silicon nitride film 8 on the
`sides of the gate electrode 3, and Te represents the thickness
`of the silicon nitride film 8 on the silicon semiconductor
`substrate 1.
`
`the volume of the silicon
`[0056] As described above,
`nitride film 8 on the sides of the gate electrode 3 can be
`minimized by reducing the thickness Tb of the silicon nitride
`film 8 on the sides of the gate electrode 3 than the thickness
`Ta on the surface of the gate electrode 3 and the thickness
`Tc on the silicon semiconductor substrate 1, and the parasitic
`capacity mainly between the gate electrodes 3 adjacent to
`each other, and between the gate electrode 3 and the contact
`electrode 6 can be minimized.
`
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`Oct. 10, 2002
`
`[0057] Also, since the silicon nitride film 7 is formed
`along the sidewall of the gate electrode 3 in a uniform
`thickness, the silicon nitride film 8 can be formed on the
`sidewall of the gate electrode 3 in a uniform thickness, and
`the surface of the silicon nitride film 8 can be made
`perpendicular to the surface of the silicon semiconductor
`substrate 1. Therefore, even if the contact hole or the LIC
`wiring is misaligned with the gate electrode 3, the contact
`hole or the LIC wiring is prevented from contacting with the
`silicon nitride film 8. Therefore, decrease in the contact area
`of the contact electrode 6 to the impurity diifusion layer 4
`(the silicide film 5) can be prevented, stabilizing the contact
`resistance.
`
`In order to form the silicon nitride film 8 so as to
`[0058]
`satisfy the film thickness conditions of Tb<Ta and Tb<Tc,
`the silicon nitride film 8 is formed using the plasma CVD
`method. Thereby, the silicon nitride film 8 that satisfies the
`film thickness conditions of Tb<Ta and Tb<Tc can be
`formed.
`
`[0059] Furthermore, in the semiconductor device of First
`Embodiment, the device configuration that satisfies Ta>Tc,
`as shown in FIG. 2, is preferable.
`
`In the SAC structure, the film thickness required
`[0060]
`for making the silicon nitride film 8 that acts as an etching
`stopper is determined from the thickness Ta of the silicon
`nitride film 8 on the surface of the gate electrode 3 subjected
`to the heaviest over-etching. In addition, by making the
`thickness Tc smaller than the thickness Ta, the over-etching
`can be reduced when the contact hole is formed in the
`
`impurity diffusion layer 4 for embedding the contact elec-
`trode 6, and therefore, the junction leakage mainly caused by
`over-etching can be suppressed. Therefore, parasitic capac-
`ity can be reduced by decreasing the thickness of the silicon
`nitride film 8 that acts as an etching stopper film to a
`minimum required thickness while satisfying the condition
`of Ta>Tc.
`
`[0061] Furthermore, in the semiconductor device of First
`Embodiment, it is preferable that the device configuration
`satisfies
`Tsw=Tb+Td
`
`[0062] with regard to a structure of the sidewall spacer and
`the etching stopper film of the transistor gate.
`
`[0063] As described above, Tsw represents the length
`(width) of the silicon nitride film 7 in the horizontal direction
`on the silicon semiconductor substrate 1. Tb represents the
`thickness of the silicon nitride film 8 on the sidewall of the
`
`gate electrode 3, and Td represents the thickness of the
`silicon nitride film 7.
`
`[0064] From such configuration, the optimal structure for
`devices that adopt shared contact or borderless structure in
`consideration of size reduction and device performance.
`
`[0065] The advantage of satisfying Tsw=Tb+Td will be
`described referring to comparative examples of FIGS. 3 and
`4. FIG. 3 shows the case where Tsw>Tb+Td.
`In this
`
`configuration, when the contact hole to be filled with the
`contact electrode 6 is misaligned toward the gate electrode
`3, the contact hole reaches the silicon semiconductor sub-
`strate 1 in the state of overlapping with the location of the
`silicon nitride film 7 on the silicon semiconductor substrate
`1. Therefore,
`the contact electrode 6 reaches the low-
`
`concentration impurity diffusion layer 4 underneath the
`silicon nitride film 7, resulting in the defect of junction
`leakage underneath the silicon nitride film 7. Since the
`junction is shallow underneath the silicon nitride film 7,
`junction leakage occurs easily if the contact hole is disposed
`here. Furthermore, if a silicide film 5 is formed on the
`impurity diffusion layer 4 as shown in FIG. 3, since the
`location of the contact hole becomes out of the silicide film
`5,
`the contact electrode 6 is directly connected to the
`impurity diffusion layer 4, and the problem of very high
`contact resistance arises.
`
`[0066] Also as FIG. 4 shows, if Tsw<Tb+Td, since the
`contact electrode 6 interferes with the silicon nitride film 8
`
`unless the location of the contact electrode 6 is sufficiently
`separated from the gate electrode 3, the contacting area of
`the contact electrode 6 to the impurity diffusion layer 4 (the
`silicide film) decreases. Thereby, the resistance of the con-
`tact electrode 6 and the silicide film 5 is elevated.
`
`in the configuration of First
`[0067] On the contrary,
`Embodiment shown in FIG. 2 in which Tsw=Tb+Td, even
`if the contact hole is misaligned toward the gate electrode 3,
`since the silicon nitride film 7 is always located underneath
`the silicon nitride film 8 that covers the sidewall of the gate
`electrode 3,
`the contact hole is prevented from passing
`through the silicon nitride film 7 and reaching the underlying
`silicon semiconductor substrate 1. Also, since the distance
`between the contact electrode 6 and the silicon nitride film
`8 can be maximized, the interference between the contact
`electrode 6 and the silicon nitride film 8 can be prevented,
`and decrease in contact resistance between the contact
`electrode 6 and the silicide film 5 can be minimized.
`
`[0068] Next, the method for manufacturing the semicon-
`ductor device of First Embodiment will be described. In the
`
`the
`following description of the manufacturing method,
`major process for forming the silicon nitride film 7 will be
`described referring to FIGS. 5A to SE, and other processes
`will be described without referring to drawings. First, an
`insulating film for isolating elements is formed on a silicon
`semiconductor substrate 1. Element isolation is performed
`using methods such as the LOCOS method or the trench
`method. Thereafter, ion implantation is performed to the
`active element region for forming the well and controlling
`the threshold value.
`
`[0069] Next, a gate oxide film 2 is formed, then a poly-
`silicon film 3a is deposited as the gate electrode material,
`and the gate electrode is patterned. The gate electrode is
`patterned using a photoresist, or an insulating film such as a
`silicon oxide film and a silicon nitride film as the mask.
`
`are
`ions
`impurity
`low-concentration
`[0070] Next,
`implanted using the gate electrode (the polysilicon film 30)
`as the mask, for forming shallow junction approaching the
`gate electrode. Thereby, a low-concentration impurity dif-
`fusion layer 40 is formed on the both sides of the silicon
`semiconductor substrate 1 on the both sides of the gate
`electrode. This state is shown in FIG. 5A.
`
`[0071] Thereafter, in process steps shown in FIGS. 5B to
`5D, a silicon nitride film 7 that acts as a sidewall spacer is
`formed on the both sides of the gate electrode 3. The
`sidewall spacer is formed by forming a three-layer structure
`consisting of a silicon oxide film 11, a silicon nitride film 7,
`and a silicon oxide film 12, performing anisotropic etching
`
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`

`US 2002/0145156 Al
`
`Oct. 10, 2002
`
`to leave these films only on the sidewall of the gate electrode
`3, forming an MOS transistor by introducing an impurity in
`the silicon semiconductor substrate 1, and then removing the
`outermost silicon oxide film 12.
`
`[0072] First, as FIG. 5B shows, a silicon oxide film 11 is
`formed so as to cover the upper surface and the sides of the
`gate electrode 3, and the surface of the silicon semiconduc-
`tor substrate 1, and then a silicon nitride film 7 is formed on
`the silicon oxide film 11.
`
`[0073] Next, a silicon oxide film 12, such as BPTEOS and
`NSG, is formed on the silicon nitride film 7. Thereafter, as
`FIG. 5C shows, the silicon oxide film 12 on the silicon
`semiconductor substrate 1 is removed by anisotropic etch-
`ing, leaving the silicon oxide film 12 only on the sidewall of
`the gate electrode consisting of a polysilicon film 3a. Then,
`etching is continued using the silicon oxide film 12 as the
`mask to remove the silicon nitride film 7 on the silicon
`semiconductor substrate 1 other than the area underlying the
`silicon oxide film 12, and on the gate electrode. Thereby, as
`FIG. 5C shows, the structure covered with the silicon nitride
`film 7 that has an L-shaped profile from the sidewall of the
`gate electrode 3 to the surface of the silicon semiconductor
`substrate 1 can be formed.
`
`[0074] At this time, by performing etching so as to leave
`the silicon oxide film 11 underlying the silicon nitride film
`7,
`the surface of the silicon semiconductor substrate 1,
`particularly in the impurity diffusion layer 4, can be pre-
`vented from being damaged. The silicon oxide film 11 is a
`film that functions to prevent the surface of the silicon
`semiconductor substrate 1 from being damaged, to be buffer
`layer between the silicon nitride film 7 that has high inter-
`face state and the gate electrode 3, and to relieve the stress
`in the buffer layer between the silicon nitride film 7 and the
`gate electrode 3. In the description of each embodiment
`other than FIGS. 5A to 5E, the description and the illustra-
`tion of the silicon oxide film 11 will be omitted.
`
`[0075] After the sidewall spacer of the silicon nitride film
`7 has been formed, for the purpose of forming deep junction,
`ion implantation of an impurity of a high concentration is
`performed using the gate electrode 3, the silicon nitride films
`7 and the