USOO7893501B2
`
`(12) United States Patent
`US 7,893,501 B2
`(10) Patent N0.:
`Tsutsui et al.
`
`(45) Date of Patent: *Feb. 22, 2011
`
`(54)
`
`(75)
`
`SEMICONDUCTOR DEVICE INCLUDING
`MISFET HAVING INTERNAL STRESS FILM
`
`(56)
`
`Inventors: Masafumi Tsutsui, Osaka (JP);
`Hiroyuki Umimoto, Hyogo (JP); Kaori
`Akamatsu, Osaka (JP)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,023,676 A
`
`6/1991 Tatsuta
`
`(73)
`
`Assignee: Panasonic Corporation, Osaka (JP)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`This patent is subject to a terminal dis-
`claimer.
`
`(21)
`
`Appl. N0.: 12/170,191
`
`(22)
`
`Filed:
`
`Jul. 9, 2008
`
`(65)
`
`(63)
`
`(30)
`Jun.
`
`Prior Publication Data
`
`US 2009/0050981 A1
`
`Feb. 26, 2009
`
`Related US. Application Data
`
`Continuation of application No. 11/730,988, filed on
`Apr. 5, 2007, now Pat. No. 7,417,289, which is a con-
`tinuation of application No. 10/859,219, filed on Jun.
`3, 2004, now Pat. No. 7,205,615.
`
`Foreign Application Priority Data
`
`16, 2003
`
`(JP)
`
`........................... .. 2003-170335
`
`Int. Cl.
`
`(51)
`
`(2006.01)
`H01L 29/76
`(2006.01)
`H01L 29/94
`(2006.01)
`H01L 31/062
`(2006.01)
`H01L 31/113
`(2006.01)
`H01L 31/119
`US. Cl.
`.................................................... .. 257/369
`Field of Classification Search ................ .. 257/369
`
`(52)
`(58)
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`52-120776
`
`10/1977
`
`(Continued)
`OTHER PUBLICATIONS
`
`Shimizu, A., et 31., “Local Mechanical-Stress Comtrol (LMC): A
`New Technique for CMOS7Perf0rmance Enhancement”, 2001,
`IEDM 01, p. 19.41-19.44.
`
`(Continued)
`
`Primary ExamineriHoward Weiss
`(74) Attorney, Agent, or FirmiMcDermott Will & Emery
`LLP
`
`(57)
`
`ABSTRACT
`
`A semiconductor device includes a first-type internal stress
`film formed of a silicon oxide film over source/drain regions
`of an nMISFET and a second-type internal stress film formed
`of a TEOS film over source/drain regions of a pMISFET. In a
`channel region of the nMISFET, a tensile stress is generated
`in the direction of movement of electrons due to the first-type
`internal stress film, so that the mobility of electrons is
`increased. In a channel region ofthe pMISFET, a compressive
`stress is generated in the direction of movement of holes due
`to the second-type internal stress film, so that the mobility of
`holes is increased.
`
`See application file for complete search history.
`
`25 Claims, 9 Drawing Sheets
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`Rn
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`TSMC 1001
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`TSMC 1001
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`US 7,893,501 B2
`Page 2
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`U.S. PATENT DOCUMENTS
`
`9/2005 Chan et a1.
`2005/0194596 A1
`FOREIGN PATENT DOCUMENTS
`60-236209
`11/1985
`01-042840 A
`2/1989
`2003-086708
`3/2003
`2004-193166
`7/2004
`OTHER PUBLICATIONS
`
`JP
`JP
`JP
`JP
`
`Japanese Office Action, with English translation, issued in Japanese
`Patent Application No. 2003-170335, mailed Dec. 22, 2009.
`Japanese Office Action, with English translation, issued in Japanese
`Patent Application No. 2003-170335, mailed Mar. 23, 2010.
`
`6,437,404
`6,573,172
`6,870,230
`6,977,194
`6,982,465
`7,022,561
`7,205,615
`7,417,289
`2003/0040158
`2004/0075148
`
`B1 *
`B1
`B2 *
`B2
`B2
`B2
`B2 *
`B2 *
`A1
`A1
`
`8/2002
`6/2003
`3/2005
`12/2005
`1/2006
`4/2006
`4/2007
`8/2008
`2/2003
`4/2004
`
`Xiang et al.
`En et al.
`Matsuda et al.
`
`.............. .. 257/347
`
`........... .. 257/365
`
`Belyansky et al.
`Kumagai et al.
`Huang et al.
`Tsutsui et al.
`Tsutsui et al.
`Saitoh
`
`............. .. 257/369
`............. .. 257/369
`
`Kumagai et al.
`
`* cited by examiner
`
`

`

`US. Patent
`
`Feb. 22, 2011
`
`Sheet 1 019
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`US 7,893,501 B2
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`FIG.1
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`US. Patent
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`Feb. 22, 2011
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`Sheet 2 019
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`US 7,893,501 B2
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`FIG.2A
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`US. Patent
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`Feb. 22, 2011
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`Sheet 3 019
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`US 7,893,501 B2
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`US. Patent
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`Feb. 22, 2011
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`Feb. 22, 2011
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`US. Patent
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`Feb. 22, 2011
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`U.S. Patent
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`US 7,893,501 B2
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`US 7,893,501 B2
`
`1
`SEMICONDUCTOR DEVICE INCLUDING
`MISFET HAVING INTERNAL STRESS FILM
`
`RELATED APPLICATIONS
`
`This application is a Continuation of US. application Ser.
`No. 11/730,988, filedApr. 5, 2007, now US. Pat. No. 7,417,
`289, which is a Continuation of US. application Ser. No.
`10/859,219, filed Jun. 3, 2004, now US. Pat. No. 7,205,615,
`and claiming priority of Japanese Application No. 2003-
`170335, filed Jun. 16, 2003, the entire contents of each of
`which are hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a semiconductor device
`including an MISFET and a method for fabricating the same,
`and more particularly relates to a measure for increasing the
`mobility of carriers.
`When a stress is generated in a semiconductor crystal layer,
`a crystal-lattice constant varies and a band structure is
`changed, so that the mobility of carriers is changed. This
`phenomenon has been known as the “piezo resistivity effect”.
`Whether the carrier mobility is increased or reduced differs
`depending on the plane direction of a substrate, the direction
`in which carriers move, and whether the stress is a tensile
`stress or a compressive stress. For example, in an Si (100)
`substrate, i.e., a silicon substrate of which the principal sur-
`face is the { 100} plane, assume that carriers move in the [01 1]
`direction. When carriers are electrons, with a tensile stress
`generated in the direction in which electrons in a channel
`region move, the mobility of the carriers is increased. On the
`other hand, when carriers are holes, with a compressive stress
`generated in the direction in which holes in a channel region
`move, the mobility of the carriers is increased. The increase
`rate of carrier mobility is proportional to the size of a stress.
`In this connection, conventionally, there have been propos-
`als for increasing carrier mobility by applying a stress to a
`semiconductor crystal layer to increase the operation speed of
`transistors and the like. For example, in Reference 1 , an entire
`semiconductor substrate is bent using an external device,
`thereby generating a stress in an active region of a transistor.
`
`SUMMARY OF THE INVENTION
`
`in the above-described known structure, an
`However,
`external device is needed in addition to a semiconductor
`
`substrate and a stress can be generated only in the same
`direction in an entire region ofthe semiconductor substrate in
`which active regions of a transistor and the like are provided
`and which is located in the principal surface side. For
`example, when an Si (100) substrate is used, neither the
`mobility of electrons nor the mobility of holes can be
`increased.
`
`It is therefore an object of the present invention to provide,
`by generating a stress which increases the mobility of carriers
`in a semiconductor layer without using an external device, a
`semiconductor device including a pMISFET and an nMIS-
`FET ofwhich respective operation speeds are increased and a
`method for fabricating the same.
`A semiconductor device according to the present invention
`includes an internal stress film for generating a stress in a gate
`length direction in a channel region of an active region in
`which a MISFET is formed.
`
`the mobility of carriers in the MISFET can be
`Thus,
`increased by using the piezo resistivity effect.
`
`2
`
`The internal stress film is capable of covering one or both
`of source/drain regions. In an nMISFET, the internal stress
`film generates a tensile stress substantially in the parallel
`direction to a gate length direction in a channel region (i.e.,
`the direction of movement of electrons). In a pMISFET, the
`internal stress film generates a compressive stress substan-
`tially in the parallel direction to a gate length direction in a
`channel region (i.e., the direction of movement of holes).
`Covering both side surfaces or both side and upper surfaces
`of a gate electrode, the internal stress film can generate a
`stress in the longitudinal direction of the channel region
`through the gate electrode, thereby increasing the mobility of
`carriers.
`
`Moreover, covering a side surface of the gate electrode and
`an upper surface of the semiconductor substrate in two
`regions of the substrate sandwiching part of the gate elec-
`trode, whether the MISFET is an nMISFET or a pMISFET,
`the internal stress film can generate a tensile stress substan-
`tially in the parallel direction to the gate width direction ofthe
`MISFET, thereby increasing the mobility of carriers.
`A first method for fabricating a semiconductor device
`according to the present invention is a method in which an
`nMISFET and a pMISFET are formed in first and second
`active regions of a semiconductor substrate, respectively, and
`then first and second internal stress films which cover source/
`
`drain regions ofthe nMISFET and source/drain regions ofthe
`pMISFET, respectively, and generate a tensile stress and a
`compressive stress, respectively, substantially in the parallel
`directions to respective gate length directions of the channel
`regions are formed.
`According to this method, a CMOS device of which the
`operation speed is increased can be obtained.
`A second method for fabricating a semiconductor device
`according to the present invention is a method in which an
`internal stress film is formed first, a groove is formed in the
`internal stress film, a gate insulating film and a buried gate
`electrode are formed in the groove, and then the internal stress
`film is removed.
`
`According to this method, a stress which increases the
`mobility of carriers in the channel region can be generated
`using a remaining stress in the gate insulating film.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a cross-sectional view illustrating a semiconduc-
`tor device according to a first embodiment of the present
`invention.
`
`FIG. 2A through 2C are cross-sectional views illustrating
`first half ofrespective steps for fabricating the semiconductor
`device of the first embodiment.
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`FIG. 3A through 3C are cross-sectional views illustrating
`latter half of respective steps for fabricating the semiconduc-
`tor device of the first embodiment.
`
`55
`
`FIGS. 4A through 4C are cross-sectional views illustrating
`first, second and third modified examples of the first embodi-
`ment.
`
`FIGS. 5A through 5D are cross-sectional views illustrating
`respective steps for fabricating a semiconductor device
`according to the first modified example of the first embodi-
`ment.
`
`FIGS. 6A through 6C are cross-sectional views illustrating
`respective steps for fabricating a semiconductor device
`according to the third modified example of the first embodi-
`ment.
`
`60
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`

`

`US 7,893,501 B2
`
`3
`FIGS. 7A through 7D are cross-sectional views illustrating
`first half of respective steps for fabricating a semiconductor
`device according to a second embodiment of the present
`invention.
`
`FIGS. 8A through 8D are cross-sectional views illustrating
`latter half of respective steps for fabricating the semiconduc-
`tor device of the second embodiment.
`
`FIGS. 9A and 9B are a plane view of an MISFET of a
`semiconductor device according to a third embodiment ofthe
`present invention and a cross-sectional view illustrating a
`cross-sectional structure taken along the line IX-IX (a cross
`section in the gate width direction), respectively.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`First Embodiment
`
`FIG. 1 is a cross-sectional view illustrating a semiconduc-
`tor device according to a first embodiment of the present
`invention. As shown in FIG. 1, a surface region of a semicon-
`ductor substrate 1, i.e., an Si (100) substrate is divided into a
`plurality of active regions 1a and 1b by an isolation region 2.
`The semiconductor device includes an nMISFET formation
`
`region Rn which includes the active region 1a and in which an
`nMISFET is to be formed and a pMISFET formation region
`Rp which includes the active region 1b and in which a pMIS-
`FET is to be formed.
`
`The nMISFET includes n-type source/drain regions 3a and
`4a each of which includes an n-type lightly doped impurity
`region, an n-type heavily doped impurity region and a silicide
`layer such as a CoSi2 layer, a gate insulating film 5 formed on
`the active region 111 and made of a silicon oxide film, a silicon
`oxynitride film or the like, a gate electrode 6a formed on the
`gate insulating film 5 and made of polysilicon, aluminum or
`the like, and a sidewall 7 covering a side surface of the gate
`electrode 611 and made of an insulating film. Part ofthe active
`region 1a located under the gate electrode 6a is a channel
`region 1x in which electrons move (travel) when the nMIS-
`FET is in an operation state.
`The pMISFET includes p-type source/drain regions 3b and
`4b each of which includes a p-type lightly doped impurity
`region, a p-type heavily doped impurity region and a silicide
`layer such as a CoSi2 layer, a gate insulating film 5 formed on
`the active region 1b and made of a silicon oxide film, a silicon
`oxynitride film or the like, a gate electrode 6b formed on the
`gate insulating film 5 and made of polysilicon, aluminum or
`the like, and a sidewall 7 covering a side surface of the gate
`electrode 6b and made of an insulating film. Part ofthe active
`region 1b located under the gate electrode 6b is a channel
`region ly in which holes move (travel) when the pMISFET is
`in an operation state.
`Moreover, provided are a first-type internal stress film 8a
`formed on the source/drain regions 3a and 4a of the nMIS-
`FET, made of a silicon nitride film or the like, and having a
`thickness ofabout 20 nm, a second-type internal stress film 8b
`formed on the source/drain regions 3b and 4b of the pMIS-
`FET, made of a TEOS film or the like, and having a thickness
`of about 20 nm, an interlevel insulating film 9 covering the
`nMISFET and pMISFET and having a surface flattened, a
`lead electrode 10 formed on the interlevel insulating film 9,
`and a contact 11 connecting each of the source/drain regions
`3a, 3b, 4a and 4b with the lead electrode 10 through the
`interlevel insulating film 9.
`Herein, an “internal stress film” is a film characterized in
`that where the internal stress film is directly in contact with
`some other member or faces some other member with a thin
`
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`film interposed therebetween, a stress is generated in the film
`itself. As for stress, there are tensile stress and compressive
`stress. In this embodiment and other embodiments, an inter-
`nal stress film in which a tensile stress is generated substan-
`tially in the parallel direction to the direction in which carriers
`move (i.e., the gate length direction) in a channel region of an
`MISFET is referred to as a “first-type internal stress film” and
`an internal stress film in which a compressive stress is gen-
`erated substantially in the parallel direction to the direction in
`which carriers move (the gate length direction) in a channel
`region of an MISFET is referred to as a “second-type internal
`stress film”.
`Herein, the semiconductor substrate 1 is an Si substrate of
`which the principal surface is the {100} plane and is referred
`to as an Si (100) substrate for convenience. However, the
`{ 100} plane is a general name for the (1100) plane, the (0110)
`plane and the (0011) plane, and therefore, even a plane which
`is not exactly the {100} plane and is tilted from the {100}
`plane by a less angle than 10 degree is considered to be
`substantially the { 100} plane. Moreover, in this embodiment,
`the direction in which electrons move in the nMISFET and
`
`the direction in which holes move in the pMISFET (i.e., the
`gate length direction of each MISFET) is the [01 1] direction.
`However, in this embodiment, the “[011] direction on the
`principal surface of an Si (100) substrate” includes equivalent
`directions to the [01 1] direction, such as the [01-1] direction,
`the [0-1 1] direction, and the [0-1-1] direction, i.e., directions
`within the range of the <011> direction. That is, even a
`direction which is not exactly the [011] direction and tilted
`from the <011> direction by a less angle than 10 degree is
`considered to be substantially the [011] direction.
`According to this embodiment, the following effects can be
`obtained.
`
`In the nMISFET, when the first-type internal stress film 8a
`is brought into a direct contact with a semiconductor layer or
`made to face a semiconductor layer with a thin film interposed
`therebetween, a stress for compressing the first-type internal
`stress film itself, i.e., a compressive stress is generated in the
`first-type internal stress film 8a. As a result, by the first-type
`internal stress film 8a, the semiconductor layer adjacent to the
`first-type internal stress film 8a can be stretched in the vertical
`direction to a boundary surface. Specifically, the first-type
`internal stress film 8a applies a compressive stress to the
`source region 3a and the drain region 4a in the active region
`1a of the nMISFET in the parallel direction to the principal
`surface. As a result, a tensile stress is applied to a region ofthe
`substrate located between the source region 3a and the drain
`region 411, i.e., the channel region 1x in the gate length direc-
`tion (the direction in which electrons move when the nMIS-
`FET is in an operation state). Then, with this tensile stress,
`electrons are influenced by the piezo resistivity effect, so that
`the mobility of electrons is increased. Herein, “substantially
`in the parallel direction” also means in a direction tilted by an
`angle of less than 10 degree from the direction in which
`electrons move.
`
`For example, assume that the substrate 1 is an Si (100)
`substrate and the direction in which electrons move is the
`
`[011] direction. When the internal stress of the first-type
`internal stress film 8a adjacent to the semiconductor layer is
`a general level for a silicon nitride film, i.e., 1.5 GPa, the
`thickness of the first-type internal stress film 8a is 20 nm, a
`space between respective parts ofthe source and drain regions
`3a and 4a being in contact with the first-type internal stress
`film 811, i.e., the length of the channel region 1x, is 0.2 pm, a
`tensile stress in the gate length direction generated at a depth
`of 10 nm from the surface of the substrate is 0.3 GPa (J. Appl.
`Phys., vol. 38-7, p. 2913, 1967) and the improvement rate of
`
`

`

`US 7,893,501 B2
`
`5
`the mobility of electrons is +10% (Phys. Rev., V01. 94, p. 42,
`1954). To obtain a larger change in the mobility than this, the
`tensile stress of a semiconductor can be increased. Thus, a
`film having a large internal stress can be used as the first-type
`internal stress film 811, the thickness of the first-type internal
`stress film 8a can be increased, or the space between the parts
`ofthe source and drain regions 3a and 4a being in contact with
`the first-type internal stress film 8a, i.e., the length of the
`channel region 1x, can be reduced for a larger change in the
`mobility. For example, when the thickness of the first-type
`internal stress film 8a is doubled, the space between the parts
`ofthe source and drain regions 3a and 4a being in contact with
`the first-type internal stress film 8a, i.e., the length of the
`channel region be is reduced to half, the improvement rate of
`the mobility of electrons is +40%. As another way to obtain a
`large mobility,
`the direction in which electrons move is
`changed from the [011] direction to the [010] direction to
`change the improvement rate ofthe mobility of electrons with
`respect to a tensile stress. As a result, with the same tensile
`stress, the improvement rate of the mobility becomes about
`3 .5 times large. Although the source and drain regions 3a and
`4a receive compressive stresses by the first-type internal
`stress film 8a, influence of the piezo resistivity effect is small
`because a low-resistant heavily doped semiconductor device
`and a silicide film are used. Moreover, influence of the inter-
`nal stress of the interlevel insulating film 9 on the channel
`region can be neglected. This is because with the substrate
`covered by the interlevel insulating film 9, internal stresses in
`the interlevel insulating film 9 are cancelled off with each
`other, so that the function of applying stress to the active
`regions 1a and 1b is small.
`In the pMISFET, when the second-type internal stress film
`8b is brought into a direct contact with the semiconductor
`layer or made to face a semiconductor layer with a thin film
`interposed therebetween, a stress for stretching the second-
`type internal stress film itself, i.e., a tensile stress is generated
`in the second-type internal stress film 8b. As a result, by the
`second-type internal stress film 8b, the semiconductor layer
`adjacent to the second-type internal stress film 8b is com-
`pressed in the vertical direction to a boundary surface. Spe-
`cifically, the second-type internal stress film 8b applies a
`tensile stress to the source region 3b and the drain region 4b in
`the active region 1b of the pMISFET in the parallel direction
`to the principal surface. As a result, a compressive stress is
`applied to a region ofthe substrate located between the source
`region 3b and the drain region 4b, i.e., the channel region 1y
`substantially in the parallel direction to the gate length direc-
`tion (the direction in which holes move when the pMI SFET is
`in an operation state). Then, with this compressive stress,
`holes are influenced by the piezo resistivity effect, so that the
`mobility of holes is increased. Herein, “substantially in the
`parallel direction” also means in a direction tilted by an angle
`of less than 10 degree from the direction in which electrons
`move.
`
`Note that, instead of the internal stress films 8a and 8b, the
`semiconductor film itself in which the source and drain
`
`regions 3a, 4a, 3b and 4b are formed may be a film having an
`internal stress, for example, an uppermost semiconductor
`layer in an SOI substrate.
`Furthermore, each of the internal stress films 8a and 8b
`does not have to be a single layer but may include multiple
`layers, as long as each of the internal stress films 8a and 8b
`can apply a stress to the substrate as a whole.
`Moreover, in this embodiment, an Si (100) substrate is
`used. However, even if an Si (11 1) substrate is used, with the
`direction in which electrons move set to be the [001] direc-
`tion, the mobility of electrons is increased by a tensile stress.
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`In general, in any substrate plane directions, there is a direc-
`tion ofmovement of electrons or holes, which allows increase
`in the mobility of electrons or holes according to the direction
`of a stress.
`In this embodiment, the internal stress films 8a and 8b exist
`on the source/drain regions 3a and 4a and the source/drain
`regions 3b and 4b, respectively. However, even when the
`internal stress film 8a exists only on one of the source/drain
`regions 3a and 4a and the internal stress film 8b exists only on
`one of the source/drain regions 3b and 4b, the effect of
`increasing the mobility of carriers can be obtained. In this
`case, the improvement rate of the mobility is reduced to half.
`In each ofthe following embodiments, when an internal stress
`film exits only on one of source/drain regions, the improve-
`ment rate of the mobility is reduced to half, compared to the
`case where internal stress films exist on source/drain regions,
`but the mobility is increased.
`FIGS. 2A through 2C and FIGS. 3A through 3C are cross-
`sectional views illustrating respective steps for fabricating a
`semiconductor device according to the first embodiment of
`the present invention.
`First, in the process step of FIG. 2A, a trench and a buried
`oxide film are formed in part of a semiconductor substrate 1,
`i.e., an Si (100) substrate, thereby forming an isolation region
`2 for dividing the substrate into active regions 1a, 1b and so
`on. Thereafter, after a gate insulating film 5 has been formed
`by thermal oxidation of respective surfaces of the active
`regions 1a and 1b and a polysilicon film for forming gate
`electrodes has been deposited, the polysilicon film and the
`gate insulating film 5 are etched by patterning using lithog-
`raphy and anisotropic dry etching, thereby forming gate elec-
`trodes 6a and 6b. The gate length direction of each ofthe gate
`electrodes 6a and 6b is the [011] direction. Next, using the
`gate electrode 6a ofthe nMISFET as a mask, ion implantation
`of an n-type impurity (e. g., arsenic) at a low concentration is
`performed to an nMISFET formation region Rn at an injec-
`tion energy of 1 0 keV and a dose of 1 x 1 013/cm2, andusing the
`gate electrode 6b ofthe pMISFET as a mask, ion implantation
`of a p-type impurity (e.g., boron) at a low concentration is
`performed to a pMISFET formation region Rp at an injection
`energy of 2 keV and a dose of 1x1015/cm2. Thereafter, an
`insulating film which is for forming a sidewall and has a
`thickness of about 50 nm is deposited on the substrate and
`then a sidewall 7 is formed on side surfaces of the gate
`electrodes 6a and 6b by etch back. Next, using the gate
`electrode 611 ofthe nMISFET and the sidewall 7 as masks, ion
`implantation of an n-type impurity (e.g., arsenic) at a high
`concentration is performed to the nMI SFET formation region
`Rn at an injection energy of20 keV and a dose of 1 x1014/cm2,
`and ion implantation of a p-type impurity (e.g., boron) at a
`high concentration is performed to the pMISFET formation
`region Rp at an injection energy of 5 keV and a dose of
`1x1016/cm2. Thereafter, thermal treatment (RTA) for activat-
`ing impurities is performed. By the above-described process-
`ing, source/drain regions 3a and 4a including an n-type
`lightly doped impurity region and an n-type heavily doped
`impurity region are formed in the nMISFET formation region
`Rn and source/drain regions 3b and 4b including a p-type
`lightly doped impurity region and a p-type heavily doped
`impurity region are formed in the pMISFET formation region
`Rp.
`Next, in the process step of FIG. 2B, a silicon nitride film 8x
`is formed on the substrate so that the silicon nitride film 8x has
`
`a relatively large thickness and a surface thereof is flatted. At
`this point of time, the silicon nitride film 8x covers respective
`upper surfaces of the gate electrodes 6a and 6b of the MIS-
`FETs. Thereafter, a resist film 12 is formed on the silicon
`
`

`

`US 7,893,501 B2
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`7
`nitride film 8x by lithography and the silicon nitride film 8x is
`patterned using the resist film 12 as a mask so that the silicon
`nitride film 8x is left only on the nMISFET formation region
`Rn.
`
`Next, in the process step of FIG. 2C, after the resist film 12
`has been removed, the silicon nitride film 8x is etched back,
`part of the silicon nitride film 8x located on the gate electrode
`6a is removed and the thickness of the silicon nitride film 8x
`
`is further reduced. Thus, a first-type internal stress film 8a is
`formed. That is, the first-type internal stress film 8a does not
`exist on the gate electrode 6a of the nMISFET but exits only
`on the source/drain regions 3a and 411.
`Next, in the process step of FIG. 3A, a TEOS film 8y is
`formed on the substrate so that the TEOS film 8y has a
`relatively large thickness and a surface thereof is flatted. At
`this point of time, the TEOS film 8y covers respective upper
`surfaces of the gate electrodes 6a and 6b of the MISFETs.
`Thereafter, a resist film (not shown) is formed on the TEOS
`film 8y by lithography and the TEOS film 8y is patterned
`using the resist film as a mask so that the TEOS film 8y is left
`only on the pMISFET formation region Rp.
`Next, in the process step of FIG. 3B, after the resist film has
`been removed, the TEOS film 8y is etched back, parts of the
`TEOS film 8y located on the gate electrodes 6a and 6b are
`removed and the thickness of the TEOS film 8y is further
`reduced. Thus, a second-type internal stress film 8b having
`substantially the same thickness as that of the first-type inter-
`nal stress film 8a is formed. That is, the second-type internal
`stress film 8b does not exist on the gate electrode 6b of the
`pMISFET and the first-type internal stress film 8a but exists
`only on the source/drain regions 3b and 4b.
`By the above-described process steps, the internal stress
`films 8a and 8b for applying stresses in opposite directions to
`each other are formed on the source/drain regions 3a and 4a
`ofthe nMISFET and the source/drain regions 3b and 4b ofthe
`pMISFET, respectively.
`Next, in the process step of FIG. 3C, on the substrate, an
`interlevel insulating film 9 is formed and then contact holes
`are formed so as to pass through the interlevel insulating film
`9 and reach the source/drain regions 3a and 4a of the nMIS-
`FET by lithography and dry etching, the source/drain regions
`3b and 4b, and the gate electrodes 6a and 6b, respectively.
`Thereafter, each of the contact holes is filled with metal (e.g.,
`tungsten), thereby forming contact plugs 11. Furthermore, a
`metal film such as an aluminum alloy film is deposited on the
`interlevel insulating film 9 and then the metal film is pat-
`terned, thereby forming a lead electrode 10 connected to each
`of the contact plugs 11. Thus, the respective source/drain
`regions 3a, 4a, 3b and 4b of the MISFETs and the gate
`electrodes 6a and 6b are made to be electrically connectable
`from the outside.
`In the fabrication method ofthis embodiment, either one of
`the two types of internal stress films 8a and 8b may be formed
`first. And the internal stress films 8a and 8b may overlap with
`each other over the isolation region 2 and the source/drain
`regions 3a, 4a, 3b and 4b.
`
`First Modified Example of First Embodiment
`
`FIGS. 4A through 4C are cross-sectional views illustrating
`first through third modified examples ofthe first embodiment.
`A semiconductor device according to a first modified
`example shown in FIG. 4A has a structure in which the
`sidewall 7 ofthe first embodiment is omitted. Moreover, each
`ofthe source/drain regions 3a, 4a, 3b and 4b does not include
`a lightly doped impurity region and includes only a heavily
`doped impurity region. Other part has the same structure as
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`that of the semiconductor device of the first embodiment. In
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`this modified example, no sidewall exists in forming an inter-
`nal stress film, so that a space between respective parts of the
`source/drain regions 3a and 4a being in contact with the
`first-type internal stress film 8a is small. Thus, a stress applied
`to each of the channel regions 1x and 1y is increased, so that
`the effect of improving the carrier mobility becomes larger
`than that of the first embodiment.
`
`A semiconductor device according to a second modified
`example shown in FIG. 4B has a structure in which instead of
`the sidewall 7 of the first embodiment, which is made of a
`silicon oxide film, the first-type internal stress film 8a made of
`a silicon nitride film covers a side surface ofthe gate electrode
`6a ofthe nMISFET and the second-type internal stress film 8b
`made of a TEOS film covers a side surface of the gate elec-
`trode 6b of the pMISFET. Moreover, each ofthe source/drain
`regions 3a, 4a, 3b and 4b does not include a lightly doped
`impurity region and includes only a heavily doped impurity
`region. Other part has the same structure as that of the semi-
`conductor device of the first embodiment.
`
`In this modified example, in addition to the effect of the
`first modified example, the following effect can be obtained.
`In the nMISFET, the first-type internal stress film 8a and the
`gate electrode 6a are in contact with each other substantially
`at the entire side surface of the gate electrode 6a, so that the
`gate electrode 6a is compressed downwardly by the first-type
`internal stress film 8a. With the gate electrode 6a compressed
`downwardly, then, in the channel region 1x, a compressive
`stress is generated in the vertical direction to the principal
`surface and the mobility of electrodes in the nMISFET is
`further improved.
`Moreover, in the pMISFET, the second-type internal stress
`film 8b and the gate electrode 6b are in contact with each other
`substantially at the entire side surface ofthe gate ele