(12) United States Patent
`(10) Patent N0.:
`Tsutsui et a1.
`(45) Date of Patent:
`
`US 7,893,501 32
`*Feb. 22, 2011
`
`1.181303189350132
`
`1541
`
`(751
`
`SEMICONDUCTOR DEVICE INCLUDING
`.V'HSFET HAVING INTERNAL STRESS FILM
`
`(56)
`
`Inventors: Masafumi Tsutsui, Osaka (JP);
`lenynki Umlmotn. I-lyngo (JP); Kauri
`Akamatsu, Osaka (JP)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5.023.61’6 A
`
`531991
`
`'l'aIsuta
`
`
`
`(73) Assignee: Panasonic Corporation, Osaka (JP)
`
`[ "' } Notice:
`
`Subject to any disclaimer. the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(1)) by 0 days.
`
`This patent is subject to a terminal dis-
`claimer.
`
`{21)
`
`App]. No: 121170.191
`
`(221
`
`Filed:
`
`Jul. 9, 2008
`
`(65)
`
`(531
`
`(30)
`Jun.
`
`(51 )
`
`(52)
`[58}
`
`Prior Publication Data
`
`US 20091005098] Al
`
`Feb. 26, 2009
`
`Related US. Application Data
`
`1 11730383. filed on
`Continuation of application No.
`Apr. 5. 2007. now Pat. No. 7.411289, which is a con-
`tinnation of application No. 101859319. filed on Jun.
`3, 2004, now Pat. No. 7.205.615.
`
`Foreign Application Priority:r Data
`
`16, 2003
`
`(JP)
`
`.. 2003470335
`
`Int. Cl.
`HML 29176
`HML 29/94
`H011. 31/062
`{1011. 31/113
`HML 31/119
`257.1369
`US. Cl.
`Field of ClassificationSearch. 2571369
`See application file for complete search history.
`
`(2006.01)
`(2006.01)
`{2006.01}
`(2006.01)
`(2006.01)
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`52~l20??fi
`
`101197?
`
`{Continued}
`OTHER PUBLICATIONS
`
`Shimizu. A" et 31.. “Local Mechanical-Stress Comtrol (LMC): A
`New Technique for CMOS_Performnnce Enhancement". 2001.
`113th 01. p. 19.4.1-19.4.4.
`
`(Continued)
`
`thinner;F Examiner—Howard Weiss
`[74] Attornqt-L Agent, or Hmr- ~McDermott Will & Emery
`LLP
`
`(57)
`
`ABSTRACT
`
`A semiconductor device includes a first—type internal stress
`film formed Ufa silicon oxide film over sonrcefdrain regions
`ot'ananSFET and a second—type internal stress film formed
`ofa TEOS film over mmroetdrain regions o la pMISFF.T. In a
`channel region ot'tlie nMJSl-‘b’l', a tensile stress is generated
`in the direction ofmovement ol'eleelruns due to the first-type
`internal stress film. so that
`the mobility of electrons is
`increased. In a channel region oftlze pMISFE’l‘, a compressive
`stress is generated in the direction of movement of holes due
`to the second-type internal stress film. so that the mobility of
`holes is increased.
`
`25 Claims, 9 Drawing Sheets
`
`RnA
`
`\/
`
`Rp
`
`
`
`IP Bridge Exhibit 2021
`IP Bridge Exhibit 2021
`TSMC v. Godo Kaisha IP Bridge 1
`TSMC V. Godo Kaisha IP Bridge 1
`IPR2017-01841
`IPR2017-01841
`
`

`

`US 1893,50] B2
`Page 2
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`U.S. PATBN'I‘ DOCUMENTS
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`Xiugel a].
`Eneial.
`Matsuda et al.
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`OTHER PUBLICATIONS
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`Belyausky ct a].
`Kinnagai et al.
`Huang at a].
`Tslltsuiet a].
`Tsutsuict 0L
`Snitch
`
`Kmnagai et al.
`
`. ZST’SO‘J
`.. 2573369
`
`Japanese (mice Action. with English translation. issued in Japanese
`Patent Application No. 2003-170335, mailed Dec. 22, 2009.
`Japanese OFfice Action. with English translation issued in Japanese
`Palent Application No. 2003-170335. mailed Mar. 23. 2010.
`* cited by examiner
`
`

`

`US. Patent
`
`Feb. 22, 2011
`
`Sheet 1 01'9
`
`US 7,893,501 B2
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`FIG.1
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`U.S. Patent
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`Feb. 22, 2011
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`Sheet 2 of 9
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`US 7,893,501 B2
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`FIG. 2A
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`US. Patent
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`Feb. 22, 2011
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`Sheel 3 uf9
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`US 7,893,501 B2
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`U.S. Patent
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`Feb. 22, 2011
`
`Sheet 4 of9
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`US 7,893,501 132
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`US. Patent
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`Feb. 22, 2011
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`US 7,893,501 B2
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`US. Patent
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`Feb. 22, 2011
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`US 7,893,501 B2
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`US 7,893,501 B2
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`US. Patent
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`Feb. 22, 2011
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`Slleel 9 of9
`
`US 7,893,501 32
`
`FIG. 9A
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`
`
`
`
`

`

`US 7,893,501 B2
`
`1
`SEMICONDUCTOR DEVICE INCLU DING
`MISFET HAVING INTERNAL STRESS FILM
`
`RELATED APPLICATIONS
`
`This application is a Continuation ot‘IlS. application Ser.
`No. Ill730,988, filed Apr. 5, 2007, now U.S. Pat. No. 7,417,
`289, which is a Continuation of U.S. application Ser. No.
`10.859319, tiled Jun. 3, 2004, new US. Pat. No. 7,205,615,
`and claiming priority of Japanese Application] No. 2003-
`170335, filed Jun. I6, 2003, the entire contents of each of
`which are hereby incorporated by reference.
`
`10
`
`2
`The intentai stress film is capable of covering one or both
`of sottrccl'draiit regions. In an nMISFET, the internal stress
`film generates a tensile stress substantially in the parallel
`direction to a gate length direction in a channel region He,
`the direction of movement of electrons). In a leSFET, the
`internal stress film generates a compressive stress substati—
`tially in the parallel direction to a gate length direction in a
`channel region [i.e., the direction of tnovement of holes).
`Covering both side surfaces or both side and upper surfaces
`of a gate electrode, the internal stress film can generate a
`stress ill the longitudinal direction of the channel region
`through the gate electrode, thereby increasing the [nobility of
`carriers.
`
`BACKGROUND OF THE INVENI‘ION
`
`The present invention relates to a semiconductor device
`including an MISFET and a method for fabricating the same,
`and more particularly relates to a measure for increasing the
`mobility of carriers.
`When a stress is generated in a semiconductorcrystal layer,
`a crystal—lattice constant varies and a band structure is
`changed, so that the mobility of carriers is changed. This
`phenomenon has been known as the “piezo resistivity etfect".
`Whether the carrier mobility is increased or reduced difl‘ers
`depending on the piano direction of a substrate, the direction
`in which carriers move, and whether the stress is a tensile
`stress or a compressive stress. For example, in on Si [100)
`substrate, i.e., a silicon stibstrate of which the principal sur-
`face is the {100} plane, assume that terriers move in the [0] 1]
`direction. When carriers are eleclmns, with a tensile stress
`generated in the direction in which electrons in a channel
`region move, the mobility of the carriers is incl-cased. On the
`other hand, when carriers are holes, with a compressive stress
`generated in the direction in which holes in a channel region
`move, the mobility of the carriers is inertutsed. The increase
`rate of carrier mobility is proportional to the size ofa stress.
`In this connection, conventionally, there have been propos—
`ais for increasing carrier mobility by applying a stress to a
`semiconductorcrystal layer to increase the operation speed of
`transistors and the like. For example, in Reference 1, an entire
`semiconductor substrate is bent using an external device,
`thereby generating a stress in an active region oi‘a Lransislor.
`
`SUMMARY OF THE INVENTION
`
`15
`
`20
`
`30
`
`4f!
`
`Moreover, covering a side surface of the gate electrode and
`an upper surface of the semiconductor substrate iti two
`regions of the substrate sandwiching part of the gate elec-
`trode, whether the MISFET is an anSFl-ITI‘ or a leSFE’I‘,
`the internal stress film can generate a tensile stress substan-
`tiallyr in the parallel direction to the gate width direction ofthe
`MISFET, thereby increasing the mobility ofcarriers.
`A first method for fabricating a semiconductor device
`according to the present invention is a method in which an
`anSl-‘E’l‘ and a pMISFET are formed iii first atld second
`_ active regions ofa semiconductor substrate, respectively, and
`then first and second interim] stress films which cover source!
`drain regions ofthe nMISFET and sourcet’drnin regions ofthe
`pMISFET, respectively, and generate a tensile stress and a
`compressive stress, respectively, substantially in the parallel
`directions to respective gate length directions of the channel
`regions are formed.
`According to this method, a CMOS device of which the
`operation speed is increased can be obtained.
`A second method for fabricating a semiconductor device
`according to the present invention is a method in which an
`internal stress film is formed first, a groove is formed in the
`internal stress fihn, a gale insulating film and a buried gate
`eieetrode are formed in the groove, and then the internal stress
`film is removed.
`
`According to this mediod, a stress which increases the
`mobility of carriers in the channei region can be generated
`using a remaining stress in the gate insulating film.
`
`BRIEF DESCRIPTION OF TIIE DRAWINGS
`
`in the above-described known structure, an
`However,
`external device is needed in addition to a semiconductor
`substrate and a stress can be generated only in the same
`direction in an entire region of the semiconductor su bstratc in
`which active regions of a transistor and the like are provided
`and which is located in the principal surface side. For
`example, when an Si (100) substrate is used, neither the
`mobility of electrons nor the mobility of holes can be
`increased.
`
`It is therefore an object ofthe present invention to provide,
`by generating a stress which increa sea the mobility ofcarriers
`in a semiconductor layer Without using an external device, a
`semiconductor device inciuding a pMISFET and an anS-
`FET ofwhich respective operation speeds are increased and a
`method for fabricating the same.
`A semiconductor device according to the present invention
`includes an internal stress film for generating a stress in a gate
`length direction in a channel region of an active region in
`which a MlSF ET is formed.
`
`thus, the mobility of carriers in the MlSl—‘El' can be
`increased by using the pie'no resistivity effect.
`
`50
`
`60
`
`FIG. 1 is a cross-swtional view illustrating a semiconduc—
`tor dwice according to a first embodiment of the present
`invention.
`
`FIG. 2A through 2C are cross-sectional vich illustrating
`first half ofrcspcctive steps for fabricating the semiconductor
`device of the first embodiment.
`
`FIG. 3A through 3C are cross—sectional views illustrating
`latter halfofrespective steps for fabricating the semiconduc—
`tor device of the first embodiment.
`
`FIGS. 4A through 4C are cross-sectiona] views illustrating
`first, second and third modified examples ofthe first embodi-
`ment.
`
`FIGS. 5A thmngh 5]) a re cross-sectional views illustrating
`respective steps for fabricating a semiconductor device
`according to the first modified example of the first embodi—
`tnent.
`
`'
`
`FIGS. 6A through 6C are eroSSusectional views illustrating
`respective steps for
`fabricating a semiconductor device
`according to the third modified example of the first embodi—
`ment.
`
`

`

`US ?,893,501 B2
`
`3
`HUS. 7A through 713 are cross-sectional views illustrating
`first half of respective steps for fabricating a semiconductor
`device according to a second embodiment of the present
`invention.
`FIGS. 8A through 8D are crosswsectionai views illustrating
`latter half of respective steps for fabricating the semiconduc-
`tor device of the second embodiment.
`
`FIGS. 9A and 9B are a plane view of an WSFET of a
`semiconductor device according to a third embodiment oI'the
`present invention and a cross-sectional view illustrating a
`cross-sectional structure taken along the line lX-IX (a cross
`section in the gate width direction), respoctivcly.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`First Embodiment
`
`10
`
`.
`
`20
`
`23'
`
`3D
`
`3
`
`FIG. I is a cross-sectional view illustrating a semiconduc—
`tor device according to a first embodiment of the present
`invention. As shown in FIG. 1 , a surface region of a semicon-
`ductor substrate 1, i.c., an Si (100) substrate is divided into a
`plurality ofactive regions 1a and 1!; by an isolation region 2.
`The semiconductor device includes an nMISFET formation
`region Rn which includes the active region In and in which an
`nMiSFl-Z'l‘ is to be formed and a pMISFET formation region
`Rp which includes the active region lb and in which a pMIS-
`PET is to he fooned.
`Tile nhflSFET includes n—type sou rceldrain regions 30 and
`do each of which includes an rr—lype lightly doped impurity
`region, an n—typc heavily doped impurity region and a silicide
`layer such as a CoSi2 layer, a gate insulating film 5 Ionrred on
`the active region la and made ofa siliconoxide film, a silicon
`oxynitride film or the like= a gate electrode 6a formed on the
`gate insulating film 5 and made ofpolysilicon, aluminum or 3
`the like, and a sidewall 7 covering a side surface of the gate '3.
`electrode 6:: and made ol'au insulating film. Part ofthe active
`region lo located under the gate electrode 6a is a clrarmel
`region 1x in which electrons move (travel) when the nMIS-
`FET is in an operation state.
`The pMIISFET includes p—type sourcetdrain regions 3!: and
`4!) each of which includes a p-type lightly doped impurity
`region, a p-type heavily doped impurity region and a silicide
`layer such as a CcSi2 layer, a gate insulating film 5 formed on
`the active region 1b and madeofa silicon oxide film, a silicon
`oxynitride film or the titre, a gate electrode at; formed on the
`gate insulating film 5 and made ofpolysilicon, aluminum or
`the like, and a sidewall 7 covering a side surface of the gate
`electrode 6b and made ol'an insulating Iilrn. Part ofthe active
`region to located under the gate electrode 6!: is a channel
`region I}: in which holes move (travel) when the leSFET is
`in an operation state.
`Moreover, provided are a first-type internal stress film 8::
`formed on the sourceidrain regions 30 and 4a of the nMIS—
`FET, ruade of a silicon nitride I'ilru or the like, and having a
`thickness ofabout 20 nm, a second—type internal stress film 8};
`formed on the sourcefdrain regions 3b and 4}) of the leS-
`FE’I', made of a 'I‘EOS film or the like, and having a thickness
`of aboul 20 run, an inlerlevel insulating film 9 covering the
`anSFET and pMISFET and having a surface flattened, a
`lead electrode ll] formed on the interlevel insulating film 9,
`and a contact 1] connecting each ol‘the sourcez‘drain regions
`3a, 3b, 4a and 4b with the lead electrode 10 through the
`interlevcl insulating film 9.
`llercin, an “internal stress [ilm" is a film characterived in
`that where the internal stress film is directly in contact with
`some other member or faces some other member with a [hill
`
`4
`film interposed therebehveen, a stress is generated in the film
`itself. As for stress, there are tensile stress and compressive
`stress. In this embodiment and other embodiments, an inter-
`nal stress film in which a tensile stress is generated substan»
`tially in the parallel direction to the direction in which carriers
`move (i.c., the gate length direction) in a channel region oi'an
`M] SEE’l‘ is referred to as a "first-type internal stress film" and
`an internal stress film in which a compressive stress is gen-
`erated substantially in the parallel direction to the direction in
`which carriers move [the gate length direction) in a charmel
`region ofan MISFET is referred to as a “second-type internal
`stress film”.
`Herein, the semiconductor substrate 1 is an Si substrate of
`which the principal surface is the {im} plane and is referred
`to as an Si (100) substrate for convenience. However, the
`{100] plane is a general name i'orthe (:1 00) plane, the {0:1 0)
`plane and the (001 1) plane, and therefore, even a pin ne which
`is not exactly the {100} plane and is tilted from the { 100}
`plane by a less angle than to degree is considered to be
`substantially the { 100} plane. Moreover, inthis embodiment,
`the direction in which electrons move in the nMZSFE’F and
`the direction in which holes move in the thSlr‘E‘l' (i.c., the
`gate length direction ofeach MISFET) is the {0! l 1 direction.
`IIowwer, in this embodiment, the “[011] direction on the
`principal surface ofan Si (100) substrate” inchtdes equivalent
`directions to the [01 1] direction, such as the [01- i] direction,
`the [0—11] direction, and the {0-1-1 ] direction, i.c., directions
`within the range of the <0] l> direction. "that
`is, even a
`direction which is not exactly the [01]] direction and tilted
`from the <011> direction by a less angle titan it] degree is
`considered to be substantially the [01 1] direction.
`Accordingtothis embodiment, the followingctl'ects can be
`obtained.
`In the anSFET, when the first—type internal stress film 8a
`is brought into a direct contact with a semiconductor layer or
`made to face a scrniconductorlayer with a thin film interposed
`therehetween, a stress for compressing the first-type internal
`stress film itself, i.c., a compressive stress is generated in the
`first-type internal stress film 80. As a result, by the first—type
`internal stress film 80, the semiconductor layer adjacent to the
`first—type internal stress [ilm 80 can be stretched in the vertical
`direction to a boundary surface. Specifically, the first—type
`internal stress film 8a applies a compressive stress to the
`source region 3:: and the drain region 4:: in the active region
`Jr: of the anSFH1‘ in the parallel direction to the principal
`surfiacc. As a result, a tensile stress is applied to a region of the
`substrate located between the source region 3n and the drain
`region 41:, i.c., the channel region ]x in the gate length direcA
`tion (the direction in which electrons move when the MIS-
`FE'l‘ is in an operation state). Then, with this tensile stress,
`electrons are influenced by the piezo resistivity effect, so that
`the mobility of electrons is increased. Herein, “substantially
`in the parallel direction” also means in a direction tilted by an
`angle of less than 10 degree from the direction in which
`. electrons move.
`For example. assume that the substrate 1 is an Si (100}
`substrate and the direction in which electrons move is the
`{011} direction. When the internal stress of the first—type
`internal stress film 80 adjacent to the semiconductor layer is
`a general level for a silicon nitride film, i.c., 1.5 GPa, the
`thickness ol'the first-type internal stress film So is 20 run, a
`space betweenrespective parts oi'the source and druinregions
`3a and 40 being in contact with the first—type internal stress
`[ilru 8a, i.c., the length ol‘t'he channel region ]x, is 0.2 pm, a
`tensile stress in the gate length direction generated at a depth
`of l 0 mn [tom the surface ot‘the su bstrate is 0.3 GPa (J. Appl.
`l’lrys., vol. 38—7, p. 2913, 1967) and the improvement rate of
`
`4!)
`
`45
`
`50
`
`ISO
`
`ES
`
`

`

`the mobilityr of electrons is +10% (Phys. Rev, vol. 94, p. 42,
`1954). To obtain a larger change in the Inability than this. the
`tensile stress of a semiconductor can be increased. Thus, a
`film having a large internal stress can be used as the first-type
`internal stress film So, the thickness of the first-type internal
`stress film So can be increased, or the space between the parts
`ofthe source and drain regions 30 and 4a being in contact with
`the first-type irlterttal stress ['ilm 8a. to, the length of the
`channel region l_r, can be reduced for a larger change iti the
`mobility. For example. when the thickness of the first—type
`internal stress film 8a is doubled, the space between the parts
`ofthc source and drain regions 3a and 4a being in contact with
`the first—type internal stress film So, Le, the length of the
`channel region 1x is reduced to half, the improvement rate of
`the mobility of electrons is +40%. As another way to obtain a
`large mobility,
`the direction in which electrons move is
`changed from the [til 1] direction to the [[110] direction to
`clulngc the improvement rate oftlte mobility ot'electrons with
`respect to a tensile stress. As a result, with the same tensile
`stress, the improvement rate of the mobility becomes about
`3.5 times large. Although the source and drain regions 3:: and
`do receive compressive stresses by the first—type internal
`stress fihn 8r), influence of the piezo resistivity effect is small
`because a low—resistant heavily doped semiconductor device
`and a silicidc film are used. Moreover, influence of the inter—
`no] stress of the interlevel insulating film 9 on the channel
`region can be neglected. This is because with the substrate
`covered by the interlevel insulating film 9, internal stresses ill
`the interlevel insulating film 9 are cancelled off with each
`other, so that the function of applying stress to the active
`regions In and lb is small.
`in the leSFET, when the second-type intcmai stress film
`so is brought into a direct contact with the semiconductor
`layer or made to face a semiconductor layer with a thin film
`interposed thcrcbctwccn, a stress for stretching the second-
`Iype internal stress film itself, i.e., a tensile stress is generated
`in the second—type internal stress film 81). As a result, by the
`second-type internal stress filtn 8b, the semiconductor layer
`adjacent to the second-type internal stress film 8b is colu-
`presscd in the vertical direction to a boundary surface. Spe—
`cifically, the second-type internal stress lilln Sb applies a
`tensile stress to the source region 3!) and the drain region 4!? in
`the act ivc region lb of the leSFl—s’l' in the parallel direction
`to the principal surface. As a result, a compressive stress is
`applied to aregion of the substrate located between the source
`region Sb and the drain region 4b, i.e., the chatuiel region 1y
`substantially in the parallel direction to the gate length direc-
`tion [the direction in which holes tnovewhen the pMI SFE’I‘ is
`in an operation state). Then, with this compressive stress,
`holes are influenced by the piezo resistivity effect, so that the
`mobility of holes is increased. Herein, “substantially in the _
`parallel direction” also means in a direction tilted by an angle
`of less than 10 degree from the direction in which electrons
`move.
`
`Note that, instead ofthe internal stress films 8a and 8b, the
`semiconductor film itself in which the source and drain
`regions 3a, 4a, 3.6 and 4b are formed may be a film having an
`internal stress, for example, an uppermost semiconductor
`‘_ la Fr in an $01 substrate.
`Furthermore, each of the internal stress films 8a and so
`does not have to he a single layer but may include multiple
`layers, as long as each of the internal stress films 8a and 8b
`nun-.m-
`can apply a stress to the substrate as a whole.
`Moreover,
`in this embodimem, an Si (100) substrate is
`used. However, even ifan Si (1 l l)suhslrale is used, with the
`direction in which electrons move set to be the [00]] direc-
`tion, the mobility ul'clectrons is increased by a tensile stress.
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`In general, in any substrate plane directions, there is a direc-
`tion of movement ofelectrons or holes, which allows increase
`in the mobility of electrons orholes according to the direction
`of a stress.
`In this embodiment, the internal stress films 8a and 8!) exist
`on the sourccldtain regions 3a and 4a and the sourcefdrain
`regions 3!: and 4!), respectively. However, even when the
`internal stress film so exists only on one of the sourcefdrain
`regions 3a and 4a and the internal stress film so exists only on
`one of the sourceldrain regions 35 zmd 4b, the effect of
`increasing the mobility of carriers can be obtained. In this
`case, the improvement rate of the mobility is reduced to half.
`In each ofthc follow ing embodiments, when an intemal stress
`film exits only on one of sourcet'drain regions, the improve—
`.' ment rate of the mobility is reduced to half, compared to the
`case where internal stress films exist on sourcefdruin regions,
`but the mobility is increased.
`FIGS. 2A through 2E“ and FIGS. 3A through 3C are cross—
`soclional vietvs illustrating respective steps for fabricating a
`semiconductor device according to the first embodiment of
`the present invention.
`First, in the procch step oil-'16. 2A, a trench and a buried
`oxide film are formed in part of a semiconductor substrate 1.
`i.c., an Si (100) substrate, thereby forming an isolation region
`2 for dividing the substrate into active regions la, lb and so__
`on. Thereaiier, aftera gate insulating film 5 has been formed
`by thermal oxidation of respective surfaces of the-active
`regions in and 1b and a polysilicon film for forming gate
`electrodes has been deposited, the polysilicon filtn and the
`gate insulating film 5 are etched by patterning using lithog—
`raphy and anisotropic dry etching, thereby forming gate elcc-
`trodcs Ga aild as. The gate length direction ofeach ofthe gate
`electrodes 6a and 6!; is the [011] direction. Next. using the
`gate electrode 6a of the nMISFET as a mask, ion implantation
`of an n-typc impurity (0.3., arsenic) at a low concentration is
`performed to an nMISI-‘ET formation region Rn at an injec-
`tion energy of lOch andadosc of 1x1013t'cm2,and using the
`gate electrode 6!) of the pMISFET as a mask, ion implantation
`of a p—type impurity (cg, boron) at a low concentration is
`performed to a pM'ISPFi'I‘ formation region Rp at an injection
`energy of 2 keV and a dose of lxlOlsrcmZ. Tltereatter, an
`insulating film which is for forming a sidewall and has a
`thickness of about 50 run is deposited on the substrate and
`then a sidewall
`'7 is formed on side surfaces of the gate
`electrodes 6a and tab by etch back. Next, using the gate
`electrode 6:: of the nMISFET and the sidewall 7 as masks, ion
`implantation of an n-type impurity (cg, arsenic) at a high
`concentration is performed to the 11MISFE'I‘ formation region
`Rn at an injection energy of 20 keV and a dose of l x10‘4tcn12,
`and ion implantation of a p—type impurity (cg, boron) at a
`high concentration is performed to the leSFl-IT formation
`region Rp at an injection enisrgy of 5 keV and a dose of
`1 24101610313. Thereafter, thermal treatment [R'l‘A] for activat—
`ing impurities is performed. By the above~described process~
`ing, sourcefdrain regions 3;: and do including an n-type
`lightly doped impurity region and an n-type heavily doped
`impurity region are formed in the nMJSFET formation region
`Ru and soureer‘drain regions 3b and 4!; including a p-type
`lightly doped impurity region 3an a p-typc heavily doped
`impurity region are formed in the lesl-‘E'I' formation rcgi on
`Rp.
`Next, in the process step ofFlG. ZB, rt silicon nitride film fix
`is formed on the substrate so that the silicon nitride liltn 8.1- has
`a relatively large thickness and a surtace thereot'is llatted. At
`this point oftimc, the silicon nitride film 81- covers respective
`upper surfaces of the gate electrodes 64: and 6b of the MIS—
`FETs. Thereafler, a resist flint 12 is formed on the silicon
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`nitride tilm fix by lithography and the si | icon nitride film 81- is
`patterned using tltc resist film 12 as a mask so that the silicon
`nitride film 8x is left only on the 11MISFET formation region
`R11.
`Next, in the process step ofFIG. 2C, alter the resist Iiltn 12
`has been removed, the silicon nitride film Sr is etched back,
`part ofthe silicon nitride filnt 8x located on the gate electrode
`6:: is removed and the thickness of the silicon nitride film fix
`is tin-flier reduced. Thus, a first—type internal stress film So is
`formed. That is. the first—type internal stress filtn So does not
`exist on the gate electrode 6a of the 11MISFET but exits only
`on the sonrcefdrain regions 3n and 40.
`Next, in the process step of FIG. 3A, a ”11505 film 8)! is
`formed on the substrate so that the TEDS filnt 8y has a
`relatively large thickness and a surface thereof is fiatted. At
`this point of time, the TEOS film 8y covers respective upper
`surfaces of the gate electrodes on and 6b of the MlSFFiTs.
`Thereafter, a resist film {not shown) is formed on the 'fLiOS
`film 8y by lithography and the TEOS film By its patterned
`using the racist film as a mask so that the T1308 film 8y is left
`only on the pMISFE'l‘ formation region Rp.
`Next, in the process step ofh'ltl. SB, afierthe resist film has
`been removed, the TEOS film 8}: is etched back, parts oftlte
`TEOS Iilm 8)! located on the gate electrodes 60 and tub are
`removed and the thickness of the TEOS film 8)! is fiirther
`reduced. Thus, a second-type internal stress film so having
`substantially the saute thickness as that of the first-typo litter-
`nal stress film 8a is formed. That is. the second-type internal
`stress filln 8!) does not exist on the gate electrode 6b of the
`thSFET and the first-type internal stress film 8:: but exists
`only on the sourcet'drain regions 36 and 411
`By the above-described process steps, the internal stress
`films 8a and so for applying stresses in opposite directions to
`each other are lbrmed on the sottttcet'drain regions 3a and do
`ofthc nMISFET and thc sonroca’drain regions Sb and 4b oftltc
`pMISFET, respectively.
`Next, in tile process step of FIG. 3C, on tile substrate. all
`interleve] insulating film 9 is formed and then contact holes
`are formed so as to pass through the interlevcl insulating film
`9 attd reach the sonroet’drain regions 3n and 40 ofthe anS-
`PET by lithography and dry etching, the sourcct’drain regions
`3!) and 4b, and the gate electrodes 60 and 6b, respectively.
`'1 hernfter, each ol‘the contact holes is filled with metal (cg,
`tungsten), thereby forming contact plugs 11. Furtliennorc, a
`metal film such as an aanninLun alloy film is deposited on the
`interlcvel insulating film 9 and then the metal film is put—
`tcrned, thereby forming a lead electrode 1 I] cotutected to each
`of the contact plugs 11. Thus, the respective sourcei’drain
`regions 3a, 4a, 3b and 4b of the MlSFETs and the gate
`electrodes 6a and 62; are made to be electrically connectable
`from the outside.
`In the fabrication method ofthis embodiment. oitheronc of
`the two types ofinternal stress films 8a and 8!) may be formed
`first. And the internal stress films 8a and so may overlap with
`each other over the isolation region 2 and the sourcetdrain
`regions 30, 4a, 3b and 421
`
`First Modified Example of First Embodiment
`
`FIGS. 4A through 4C are cross—sectional views illustrating
`first through third modified examples ofthe first embodiment.
`A semiconductor device according to a first modified
`example shown itt FIG. 4A has a structure in which the
`sidewall 7 ot'thc first embodiment is omitted. Moreover, each
`n ftlte stiurtrt‘dtain regions 3a, 40, 3b and 4!) does not include
`a lightly doped impurity region and includes only a heavily
`doped impurity region. Other parl has the same structure as
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`mat of the semiconductor device of the first embodiment. [n
`this modified example, no sidewall exists in forming an inter-
`nal stress film, so that a space between respective parts of the
`sourcel’drain regions 3:: and 4o being in contact with the
`first-type internal stress film So is small. Thus, a stress applied
`to each of the chamtcl regions 1x and 1y is increased, so that
`the effect of in'lpmving the carrier mobility becomes larger
`than that of the first embodiment.
`
`A semiconductor device according to a second modifed
`example shownin 1:19.43has a structure in which instead of
`the!sidewall 7 of the first embodiment, whichIs made of a
`'slltconoxtdc film the first—type internal stress film 80 made of
`a silicon nitride filnt covers3£192 surface ofthe gal;electrode
`6:: ofthe 11MISFET<and the second--type internal stress fillnso
`made of a TEOSfilm covers a side surface of the gate elec-
`trode 6b oftlte leSFET. Moreover. each ofthe sourcel‘drain
`regions 36, 4a, 3}: and 4!) does not include a lightly doped
`impurity region and includes only a heavily doped impurity
`region. Other part has the same structure as that ot‘the semi—
`conductor dcviee of the first embodiment.
`
`In this modified example, in addition to the effect of the
`first modified example, the following cfliect can be obtained.
`In the tiMlSFE'l‘, the first-type internal stress film 8:: and the
`gate electrode 60 are in contact with each other substantially
`at the en1ire side surface of the gate electrode 6o. so that the
`gate electrode 6a is compressed downwardly by the first-type
`internal stress film 80. With the gate electrode 6a compressed
`downwardly, then, in the channel region 1x, a compressive
`stress is generated in the vertical direction to the pri