(12) Unlted States Patent
`(10) Patent N0.:
`US 6,870,230 132
`
`Matsuda et al.
`(45) Date of Patent:
`Mar. 22, 2005
`
`U5006870230B2
`
`(54) SEMICONDUCTOR DEVICE UTILIZING
`DUMMY FEATURES TO FORM UNIFORM
`SIDEWALL STRUCTURES
`
`(75)
`
`Inventors: Takayuki Matsuda, Kyoto (JP);
`Mizuki Segawa, Osaka (JP)
`
`(73) Assignee: Matsushita Electric Industrial C0.,
`Ltd” Osaka (JP)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term Of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`7/1999 Oyamatsu ................... 438/183
`5,923,969 A *
`8/2000 Kunikiyo .......
`438/653
`6,096,641 A *
`
`................... 438/305
`3/2001 Teo et a1.
`6,204,137 B1 *
`6,306,755 B1 * 10/2001 Zheng ........................ 438/631
`6,384,450 B1 *
`5/2002 Hidaka et a1.
`..
`.. 257/321
`
`........
`.. 438/183
`2001/0055842 A1 * 12/2001 Uh et a1.
`................... 438/183
`2002/0076867 A1 *
`6/2002 Lee et a1.
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`11330427 A * 11/1999
`
`......... H01L/27/115
`
`* cited by examiner
`
`(21) Appl. No.: 10/300,798
`
`(22)
`
`Filed:
`
`NOV. 21, 2002
`
`(65)
`
`Prior Publication Data
`
`US 2003/0098473 A1 May 29, 2003
`
`(30)
`
`Foreign Application Priority Data
`
`NOV. 27, 2001
`
`(JP)
`
`....................................... 2001—361244
`
`(51)
`(2:)
`(
`)
`
`(56)
`
`Int. Cl.7 ................................................ H01L 23/52
`
`E'-8111le S""""h"""""" 25795652027827:
`1e
`0
`ear357/508513623774 775/ 438/639’
`’
`’
`’
`’
`’
`926
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`Primary Examiner—Stephen W. Smoot
`(74) Attorney, Agent, or Firm—McDermott Will & Emery
`LLP
`
`(57)
`
`ABSTRACT
`
`An inventive semiconductor device includes: a substrate; a
`plurality of first projections each including at least a gate
`electrode and formed on the substrate; and a plurality of
`second projections formed on the substrate. When a contour
`surface constituted by the uppermost face of the substrate
`and by side and upper faces of the first and second projec-
`tions is measured for every partial area per unit area of the
`substrate, the maximum partial area of the contour surface is
`1.6 or less times larger than the minimum partial area of the
`contour surface.
`
`5,883,436 A *
`
`3/1999 Sadjadi et a1.
`
`.............. 257/760
`
`12 Claims, 11 Drawing Sheets
`
`
`
`
`/ N
`L «113
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`,V 1
`
`
`
`
`
`
`
` 71“}
`
`
`
`
`
`
`
`
`ii
`(an
`
`
`
`
`17
`17 16b
`l7
`
`
`
`
`
`
`IP Bridge Exhibit 2017
`IP Bridge Exhibit 2017
`TSMC v. Godo Kaisha IP Bridge 1
`TSMC V. Godo Kaisha IP Bridge 1
`IPR2017-01841
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`IPR2017-01841
`
`

`

`US. Patent
`
`Mar. 22, 2005
`
`Sheet 1 0f 11
`
`US 6,870,230 B2
`
`FIG. 1
`
`5-.—4
`(1.4—4
`
`120
`'
`
`on?
`c a
`-.—1CD
`+41:
`(fin-45:.
`.—+mo
`314-35 1.00
`320(1)
`".4
`5..
`U]
`
`:13 3 0 80
`NEH ‘
`3.x m
`C0094
`3'2"”
`mug 0.60
`tch
`0.: E
`+Jr—l
`U3
`‘v—1
`88‘“ 0.40
`C.
`b0
`.x c c
`.323
`53953 0.20
`5-43
`(D
`U)
`£333
`”HE
`2C
`
`”4-H
`
`
`
`0.00
`O.81.01.21.41.61.8 2.0 2.2 2.4 2.6
`
`'E
`
`ratio of surface area per unit area
`in dense region to surface area per
`unit area in sparse region
`
`

`

`US. Patent
`
`hdar.22,2005
`
`Sheetz 0f11
`
`US 6,870,230 132
`
`
`
`

`

`US. Patent
`
`hdar.22,2005
`
`Sheet3 0f11
`
`US 6,870,230 132
`
`.V
`
`31.?
`
`1““!
`
`.r"§
`
`
`

`

`US. Patent
`
`hdar.22,2005
`
`Sheet4 0f11
`
`US 6,870,230 132
`
`
`
`

`

`US. Patent
`
`hdar.22,2005
`
`Sheets 0f11
`
`US 6,870,230 132
`
`vnu-fiv
`
`3.
`
`'1'.
`
`

`

`US. Patent
`
`hdar.22,2005
`
`Sheet6 0f11
`
`US 6,870,230 132
`
`
`
`

`

`US. Patent
`
`hdar.22,2005
`
`Sheet7 0f11
`
`US 6,870,230 132
`
`
`
`3
`
`3V
`
`

`

`US. Patent
`
`Mar. 22, 2005
`
`Sheet 8 0f 11
`
`US 6,870,230 B2
`
`A
`
`E:
`
`3.V
`
`O
`Si
`
`O r—i
`a:
`
`or:
`53c:
`z s:
`o 30
`oo
`m-H
`mm
`H33
`
`0 b
`
`-
`
`3;:
`c.""
`a)
`a “”3
`“*3
`0>
`o 138
`$53.
`L”
`g:
`on
`0
`«1’3
`<14
`EM
`0-5-3
`“D
`C) ch
`r-i
`m
`mm
`o a)
`5-H
`c:
`N +4!!!
`mm"—1
`>5
`1:
`E:s
`1:
`
`o.
`
`_.
`
`OO
`I
`(.5
`1—4
`m:
`
`.1
`
`no
`<14
`ca
`c:
`00
`cow4
`(N
`o
`o
`o
`o
`on
`03o:
`<3:
`—3
`Pi
`F;
`vi
`c5
`chi
`<5
`1Q UOIBBJ esuep go pua ue 13 p812001 ap0110319 @128 JO
`308; epys uo pamxo;
`[IBMBPIS go qqum sq; 01 1Q uo1891
`asuap JO 91pp1w sq; IBBU p818001 9p0113319 9198 go 909;
`apps uo pemlog {Temepys g0 qqppm eq1 JO 01121
`
`O
`
`C
`2‘"
`
`

`

`US. Patent
`
`5mm
`
`
`
`<@.0:
`
`m
`
`m
`
`9_t_
`
`fl_Mmefi.mmfiNQH"NHnmfiPHNH
`
`_
`
`N
`
`Hmflgwmmu,mmmfi‘mmfl
`“III-Illu-
`5wfi‘ex.
`mgum.m
`
`
`
`m%mfifl
`
`mmd:
`
`US 6,870,230 132
`
`v-4
`
`.‘
`
`
`
`a!$5g§a
`,
`47‘"
`_@§«
`
`’11:! l
`
`ll/I/I/I/I/
`
`:l
`
`A
`[Ill/Il/Ill
`”ar;I:I:a”ll1.a..,
`fl
`III/ll/I/l
`
`gfia
`.EIV
`
`
`
`
`
`
`
`
`

`

`US. Patent
`
`hdar.22,2005
`
`Sheet10 0f11
`
`US 6,870,230 132
`
`
`
`.53QOEQ
`
`

`

`US. Patent
`
`Mar. 22, 2005
`
`US 6,870,230 132
`
`2maaaaw.3figaEEQEMm.m:m:a:mU
` .53QOEQ
`
`
`
`
`
`um§_y_§_‘s"K.“—V\...'‘~&_§n"\.WI:-WI}.1W4.\.§\\\\\\.ANNE.
`
`
`.Il.I,
`
`uV
`
`
`
`
`
`
`

`

`US 6,870,230 B2
`
`1
`SEMICONDUCTOR DEVICE UTILIZING
`DUMMY FEATURES TO FORM UNIFORM
`SIDEWALL STRUCTURES
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to semiconductor devices
`and methods for fabricating the same, and more particularly
`relates to improving reliability of the semiconductor
`devices.
`
`Recently, as semiconductor devices have been downsized,
`spacing between gate electrodes has been reduced.
`However, it is extremely difficult to reduce the thickness of
`the gate electrodes because this reduction increases the
`resistance and also prolongs the delay time. Accordingly, the
`reduction in thickness of the gate electrodes has not
`advanced. As a result, the aspect ratio of the gate electrodes
`(which is herein the ratio of the height of the gate electrodes
`to the spacing between the gate electrodes) increases so that
`it is difficult to bury an interlevel dielectric film in the gap
`between the gate electrodes by a known method.
`If a void is present in part of the interlevel dielectric film
`through which a contact hole is to be formed and which is
`located between the gate electrodes, there arises a problem
`that deposition components created by dry etching are
`attached to the bottom of the contact hole to cause a contact
`failure.
`
`As a method for solving this problem, a sacrificial side-
`wall process was proposed (in the 61st Japan Society of
`Applied Physics, Annual Meeting No.2, p. 781 [5p-ZE-3]).
`In this process, a sidewall is removed after source and drain
`are defined so that the spacing between gate electrodes
`becomes wider and then an interlevel dielectric film is
`
`buried in a gap between the gate electrodes.
`The sacrificial sidewall process will be hereinafter
`described with reference to FIGS. 10A through 11B.
`First,
`in a process step shown in FIG. 10A, isolation
`regions 2 each made of a trench isolation are formed in a
`semiconductor substrate 1, and then gate electrodes 6 are
`formed on the substrate. Each of the gate electrodes 6
`includes: a gate insulating film 3 of a silicon oxynitride film;
`a lower gate electrode 4a of polysilicon; an upper gate
`electrode 4b of a multilayer metal film; and a gate protective
`layer 5 of a silicon nitride film, in that order from below.
`Thereafter, impurity ions are implanted into the semicon-
`ductor substrate 1 using the gate electrodes 6 as a mask,
`thereby defining first doped regions 7 to be LDD regions or
`extension doped regions.
`Next, in a process step shown in FIG. 10B, an underlying
`insulating film 8 of an NSG film (a silicon oxide film
`containing no impurities), a protective insulating film 9 of a
`silicon nitride film, and a sidewall insulating film 10 of a
`BPSG film are formed in this order over the substrate. In this
`
`case, the sidewall insulating film 10 is formed by an atmo-
`spheric or a subatmospheric CVD process so as to have a
`sufficient etch selectivity with respect
`to the underlying
`insulating film 8 and the protective insulating film 9 during
`a subsequent wet etching process.
`Then, in a process step shown in FIG. 11A, the sidewall
`insulating film 10, the protective insulating film 9 and the
`underlying insulating film 8 are etched in this order by
`anisotropic dry etching, thereby forming sidewalls 11 each
`having a multilayer structure including an underlying insu-
`lating film 8a, a protective insulating film 9a and a sidewall
`insulating film 10a. Subsequently,
`impurity ions are
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`implanted into the semiconductor substrate 1 using the gate
`electrodes 6, the sidewalls 11 and the isolation regions 2 as
`a mask, thereby defining second doped regions 12 to be
`heavily-doped source/drain regions.
`the
`Thereafter,
`in a process step shown in FIG. 11B,
`sidewall
`insulating film 10a made of a BPSG film and
`included in the sidewalls 11 is selectively removed by wet
`etching, thereby forming L-shaped sidewalls 11a including
`the underlying insulating film 8a and the protective insulat-
`ing film 9a so that
`the spacing between the L-shaped
`sidewalls 11a formed on side faces of the gate electrodes 6
`is sufficiently wide. Subsequently, an interlevel dielectric
`film 13 of a BPSG film is deposited by a CVD process over
`the substrate so as to fill in the gap between the L-shaped
`sidewalls 11a. Then, the surface of the interlevel dielectric
`film 13 is planarized by a CMP process.
`SUMMARY OF THE INVENTION
`
`in a situation
`In the known method described above,
`where a dense region D1 in which the gate electrodes 6 are
`densely formed and a sparse region D2 in which the gate
`electrodes 6 are sparsely formed are present on the semi-
`conductor substrate 1 as shown in FIG. 10A, if the sidewall
`insulating film 10 such as a BPSG film to be sidewalls is
`deposited by, for example, an atmospheric or a subatmo-
`spheric CVD process in the process step shown in FIG. 10B,
`the sidewall insulating film 10 is made thick in the sparse
`region D2 sparsely including the gate electrodes 6, while the
`sidewall insulating film 10 is made thin in the dense region
`D1 densely including the gate electrodes 6. This is because
`the deposition rate is determined by the feeding rate during
`an atmospheric or a subatmospheric CVD process so that the
`thickness of the deposited sidewall insulating film 10 varies
`depending on the area of the region on which the film is
`deposited.
`Accordingly, in the process step shown in FIG. 11A, when
`the sidewalls 11 are formed by anisotropic dry etching, the
`width d1 of the sidewalls 11 located in the dense region D1
`densely including the gate electrodes 6 and the width d2 of
`the sidewalls 11 located in the sparse region D2 sparsely
`including the gate electrodes 6 have a relationship where
`d1<d2. That is to say, the variation in the thickness of the
`deposited sidewall insulating film 10 directly leads to the
`variation in the width of the sidewalls 11.
`
`If the width d2 of the sidewalls 11 located in the sparse
`region D2 sparsely including the gate electrodes 6 increases,
`residues R2 of the underlying insulating film 8 and of the
`protective insulating film 9 become larger than residues R1
`in the dense region D1. Accordingly, when contact holes
`reaching the second doped regions 12 are formed and then
`filled with plugs, contact failures between the plugs and the
`second doped regions 12 are likely to occur. That is to say,
`the reliability of the resultant semiconductor device might be
`degraded.
`In addition, since the thickness of the sidewall insulating
`film 10 varies depending on the area of the region on which
`the film is deposited, the width of the sidewalls 11 might also
`vary depending on the types of semiconductor devices.
`Therefore, even if the semiconductor devices have the same
`design rule, their transistor performances might differ.
`It is therefore an object of the present invention to provide
`a highly reliable semiconductor device.
`Specifically, an inventive semiconductor device includes:
`a substrate; a plurality of first projections each including at
`least a gate electrode and formed on the substrate; and a
`plurality of second projections formed on the substrate. In
`
`

`

`US 6,870,230 B2
`
`3
`this device, when a contour surface constituted by the
`uppermost face of the substrate and by side and upper faces
`of the first and second projections is measured for every
`partial area per unit area of the substrate,
`the maximum
`partial area of the contour surface is 1.6 or less times larger
`than the minimum partial area of the contour surface.
`In a sacrificial sidewall process, the thickness of sidewalls
`formed on side faces of first projections varies depending on
`partial areas of a contour surface per unit area of a substrate.
`On the other hand, according to the present invention, when
`the contour surface is measured for every partial area per
`unit area of the substrate, the maXimum partial area of the
`contour surface is 1.6 or less times larger than the minimum
`partial area of the contour surface. That is to say, the area of
`the contour surface per unit area of the substrate is substan-
`tially uniform. Accordingly, the sidewalls formed on side
`faces of the first projections have substantially the same
`thickness between a region where the first projections are
`densely arranged and a region where the first projections are
`sparsely arranged. As a result, a semiconductor device is
`obtained with variation in the width of the sidewalls sup-
`pressed.
`Each of the first projections may include a gate including
`a gate insulating film and a gate electrode formed on the gate
`insulating film, and a sidewall formed on a side face of the
`gate, while each of the second projections may be a dummy
`gate including a gate including a gate insulating film and a
`gate electrode formed on the gate insulating film, and a
`sidewall formed on a side face of the gate.
`Alternatively, each of the first projections may include a
`gate including a gate insulating film and a gate electrode
`formed on the gate insulating film, and a sidewall formed on
`a side face of the gate, while each of the second projections
`may be an isolation portion.
`Another inventive semiconductor device includes: a sub-
`
`strate; a plurality of first projections each including at least
`a gate electrode and formed on the substrate; and a plurality
`of second projections formed on the substrate. Each of the
`first projections and an adjacent one of the first or second
`projections are spaced 10 pm or less apart from one another.
`In this device, the sidewalls formed on side faces of the
`first projections have substantially the same thickness. As a
`result, a semiconductor device is obtained with variation in
`the width of the sidewalls suppressed.
`Another inventive semiconductor device includes: a sub-
`
`strate; a plurality of M18 transistors, each of the MIS
`transistor being formed on the substrate and including a gate
`insulating film, a gate electrode and a doped region; a
`plurality of isolation regions formed in the substrate; an
`interlevel dielectric film provided at least over the MIS
`transistors and the isolation regions; a plurality of contact
`holes formed through the interlevel dielectric film, each of
`the contact holes reaching the doped region or the gate
`electrode of a corresponding one of the MIS transistors; a
`plurality of dummy contact holes formed through the inter-
`level dielectric film to reach the isolation regions; and
`sidewalls formed on side faces of the contact holes and of
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`the dummy contact holes.
`The thickness of the sidewalls formed on side faces of the
`
`60
`
`contact holes varies depending on partial areas of a contour
`surface constituted by the uppermost face of the interlevel
`dielectric film and by side and bottom faces of the contact
`holes and of the dummy contact holes, per unit area of the
`substrate. According to the present invention, the presence
`of the dummy contact holes enables an adjustment for
`making partial areas of the contour surface per unit area of
`
`65
`
`4
`the substrate substantially uniform. As a result, a semicon-
`ductor device is obtained with variation in the thickness of
`
`the sidewalls suppressed.
`When a contour surface constituted by the uppermost face
`of the interlevel dielectric film and by side and bottom faces
`of the contact holes and of the dummy contact holes is
`measured for every partial area per unit area of the substrate,
`the maXimum partial area of the contour surface is prefer-
`ably 1.6 or less times larger than the minimum partial area
`of the contour surface.
`
`In this device, the partial areas of the contour surface per
`unit area of the substrate are substantially uniform.
`Accordingly, the sidewalls formed on side faces of the first
`projections have substantially the same thickness between a
`region where the contact holes are densely arranged and a
`region where the contact holes are sparsely arranged. As a
`result, a semiconductor device is obtained with variation in
`the thickness of the sidewalls suppressed.
`An inventive method for fabricating a semiconductor
`device includes the steps of: a) preparing a substrate; b)
`forming, on the substrate, a plurality of first projections and
`a plurality of second projections, each of the first projections
`including at least a gate electrode; c) implanting impurity
`ions into the substrate using the first and second projections
`as a mask, thereby forming doped regions; and d) forming
`a sidewall
`film on side faces of the first and second
`
`projections, and then forming sidewalls by anisotropic etch-
`ing. In the step b),
`the first and second projections are
`formed such that when the contour surface constituted by the
`uppermost face of the substrate and by side and upper faces
`of the first and second projections is measured for every
`partial area per unit area of the substrate, the maXimum
`partial area of the contour surface is 1.6 or less times larger
`than the minimum partial area of the contour surface.
`In a sacrificial sidewall process, the thickness of sidewalls
`formed on side faces of first projections varies depending on
`partial areas of a contour surface per unit area of a substrate.
`On the other hand, according to the inventive method for
`fabricating a semiconductor device, when the contour sur-
`face is measured for every partial area per unit area of the
`substrate, the maXimum partial area of the contour surface is
`1.6 or less times larger than the minimum partial area of the
`contour surface. That is to say, partial areas of the contour
`surface per unit area of the substrate are substantially
`uniform. Accordingly, the sidewalls formed on side faces of
`the first projections have substantially the same thickness
`between a region where the first projections are densely
`arranged and a region where the first projections are sparsely
`arranged. As a result, a semiconductor device is obtained
`with variation in the width of the sidewalls suppressed.
`Each of the first projections may be a gate including a gate
`insulating film and a gate electrode formed on the gate
`insulating film, while each of the second projections may be
`a dummy gate including a gate insulating film and a gate
`electrode formed on the gate insulating film.
`Alternatively, each of the first projections may be a gate
`including a gate insulating film and a gate electrode formed
`on the gate insulating film, while each of the second pro-
`jections may be an isolation region.
`Another inventive method for fabricating a semiconduc-
`tor device includes the steps of: a) preparing a substrate; b)
`forming, on the substrate, a plurality of first projections and
`a plurality of second projections, each of the first projections
`including at least a gate electrode; c) implanting impurity
`ions into the substrate using the first and second projections
`as a mask, thereby forming doped regions; and d) forming
`
`

`

`US 6,870,230 B2
`
`5
`film on side faces of the first and second
`a sidewall
`projections, and then forming sidewalls by anisotropic etch-
`ing. In the step b),
`the first and second projections are
`formed such that each of the first projection and an adjacent
`one of the first or second projections are spaced 10 pm or
`less apart from one another.
`With the inventive method for fabricating a semiconduc-
`tor device, the sidewalls formed on side faces of the first
`projections have substantially the same thickness. As a
`result, a semiconductor device is obtained with variation in
`the width of the sidewalls suppressed.
`Another inventive method for fabricating a semiconduc-
`tor device includes the steps of: a) preparing a substrate; b)
`forming, on the substrate, a plurality of isolation regions, a
`plurality of MIS transistors each including a gate insulating
`film, a gate electrode and a doped region, and an interlevel
`dielectric film provided over at least the MIS transistors and
`the isolation regions; c) forming a plurality of contact holes
`and a plurality of dummy contact holes through the inter-
`level dielectric film, each of the contact holes reaching the
`doped region or the gate electrode, each of the dummy
`contact holes reaching one of the isolation regions; and d)
`forming a sidewall film on the substrate, and then forming
`sidewalls on side faces of the contact holes and of the
`
`dummy contact holes by anisotropic etching. In the step c),
`the contact holes and the dummy contact holes are formed
`such that when a contour surface constituted by the upper-
`most face of the interlevel dielectric film and by side and
`bottom faces of the contact holes and of the dummy contact
`holes is measured for every partial area per unit area of the
`substrate, the maXimum partial area of the contour surface is
`1.6 or less times larger than the minimum partial area of the
`contour surface.
`The thickness of the sidewalls formed on side faces of the
`
`contact holes varies depending on partial areas of the
`contour surface constituted by the uppermost face of the
`interlevel dielectric film and by side and bottom faces of the
`contact holes and of the dummy contact holes, per unit area
`of the substrate. According to the inventive method for
`fabricating a semiconductor device, by providing the
`dummy contact holes,
`the maXimum partial area of the
`contour surface is 1.6 or less times larger than the minimum
`partial area of the contour surface, when the contour surface
`is measured for every partial area per unit area of the
`substrate. That is to say, the partial areas of the contour
`surface can be made uniform. Accordingly, the sidewalls
`formed on side faces of the contact holes have substantially
`the same thickness between a region where the contact holes
`are densely arranged and a region where the contact holes
`are sparsely arranged. As a result, a semiconductor device is
`obtained with variation in the thickness of the sidewalls
`
`suppressed.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a graph showing the relationship between the
`surface area of a region of a substrate on which a sidewall
`insulating film is deposited and the thickness of the sidewall
`insulating film deposited on side faces of a gate electrode.
`FIGS. 2A and 2B are cross-sectional views showing
`respective process steps for fabricating a semiconductor
`device according to a first embodiment of the present
`invention.
`
`FIGS. 3A and 3B are cross-sectional views showing
`respective process steps for fabricating the semiconductor
`device of the first embodiment.
`
`FIGS. 4A and 4B are cross-sectional views showing
`respective process steps for fabricating the semiconductor
`device of the first embodiment.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`FIGS. 5A and 5B are cross-sectional views showing
`respective process steps for fabricating a semiconductor
`device according to a second embodiment of the present
`invention.
`
`FIGS. 6A and 6B are cross-sectional views showing
`respective process steps for fabricating a semiconductor
`device using a known sacrificial sidewall process.
`FIGS. 7A and 7B are cross-sectional views showing
`respective process steps for fabricating a semiconductor
`device according to a third embodiment of the present
`invention.
`
`FIG. 8 is a graph showing the relationship between the
`distance from an end of a dense region D1 where gate
`electrodes are arranged most densely to one of dummy gate
`electrodes in a region D3 and the ratio of the thickness of a
`sidewall formed on a side face of one of the gate electrodes
`located near the middle of the dense region D1 to the
`thickness of a sidewall formed on a side face of one of the
`
`gate electrodes located at the edge of the dense region D1.
`FIGS. 9A and 9B are cross-sectional views showing
`respective process steps for fabricating a semiconductor
`device according to a fourth embodiment of the present
`invention.
`
`FIGS. 10A and 10B are cross-sectional views showing
`respective process steps for fabricating a semiconductor
`device using the known sacrificial sidewall process.
`FIGS. 11A and 11B are cross-sectional views showing
`respective process steps for fabricating a semiconductor
`device using the known sacrificial sidewall process.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`As has been described above, in the known method for
`fabricating a semiconductor device, if there are the dense
`region where the gate electrodes are densely arranged and
`the sparse region where the gate electrodes are sparsely
`arranged on the semiconductor substrate, the width of the
`sidewalls varies.
`
`To prevent this variation, the present inventors thought
`that the width of the sidewalls varies because the deposition
`rate is determined by the feeding rate of a reactive gas during
`a CVD process for forming the sidewall insulating film, and
`they investigated the relationship between the surface area
`of the substrate on which the sidewall insulating film is
`deposited and the thickness of the deposited sidewall insu-
`lating film. The result is shown in FIG. 1.
`FIG. 1 is a graph showing the relationship between the
`surface area of the region of the substrate on which the
`sidewall insulating film (a BPSG film) is deposited and the
`thickness of the sidewall insulating film deposited on side
`faces of the gate electrodes. The surface area in this case is
`the area of the upper face (i.e., a contour surface) of the
`substrate eXposed before the sidewall
`insulating film is
`formed. The surface area includes upper and side faces of the
`gate electrodes, upper faces of the isolation regions, and side
`faces of the steps between the semiconductor substrate and
`the isolation regions.
`The abscissa of FIG. 1 represents the ratio of the surface
`area of a sparsest region (a region with fewer steps, in which
`the gate electrodes are arranged most sparsely) in the sub-
`strate to the surface area of a densest region (a region with
`more steps, in which the gate electrodes are arranged most
`densely), when the upper face of the semiconductor sub-
`strate is divided into regions of 10x10 Mmz. The ordinate
`represents the ratio of the thickness of the sidewall insulat-
`
`

`

`US 6,870,230 B2
`
`7
`ing film in a sparse region to the thickness of the sidewall
`insulating film in a dense region.
`The result shown in FIG. 1 is that when the ratio of the
`surface area of a dense region per unit area to the surface
`area of a sparse region per unit area is 1.6 or less,
`the
`variation in the thickness of the sidewall insulating film is
`reduced. Accordingly, if the upper face of the semiconductor
`substrate is divided into regions of 10x10 Mmz, the surface
`areas of these divided regions are compared with each other,
`and the projecting gate electrodes and the isolation regions,
`for example, are formed on the semiconductor substrate such
`that the maximum surface area is 1.6 times as large as the
`minimum surface area, then the variation in the thickness of
`the sidewalls can be suppressed. The following first and
`second embodiments are based on this result.
`
`Hereinafter, preferred embodiments of the present inven-
`tion will be described with reference to the accompanying
`drawings, in which each member with substantially the same
`function will be identified by the same reference numeral for
`the sake of simplicity of description.
`Embodiment 1
`
`FIGS. 2A through 4B are cross-sectional views showing
`respective process steps for fabricating a semiconductor
`device according to a first embodiment of the present
`invention.
`
`isolation
`in a process step shown in FIG. 2A,
`First,
`regions 2 each made of a trench isolation are formed in a
`semiconductor substrate 1. Then, thermal oxidation is per-
`formed in an NO/O2 atmosphere, thereby forming a silicon
`oxynitride film with a thickness of about 3 nm to be a gate
`insulating film. Thereafter, an undoped polysilicon film is
`deposited to a thickness of about 100 nm over the silicon
`oxynitride film. Subsequently, phosphorus (P) or boron (B)
`is implanted into part of the polysilicon film. Then, heat
`treatment is performed at 800° C. for 30 minutes so that
`phosphorus or boron is uniformly diffused in the polysilicon
`film, thereby making the polysilicon film p- or n-type. Then,
`after a natural oxide film formed on the polysilicon film has
`been removed, a multilayer metal film made of titanium
`(Ti)/titanium nitride (TiN)/tungsten (W) (having thicknesses
`of 10 nm (Ti), 20 nm (TiN) and 50 nm (W), respectively) in
`that order from below is formed by sputtering. Then, a
`silicon nitride film is deposited by an LP-CVD process to a
`thickness of about 120 nm over the multilayer metal film.
`Thereafter, the silicon nitride film, the multilayer metal film,
`the polysilicon film and the silicon oxynitride film are
`patterned by photolithography and dry etching,
`thereby
`forming a gate insulating film 3 of the silicon oxynitride
`film, a lower gate electrode 4a of polysilicon, an upper gate
`electrode 4b of the multilayer metal film, and a gate pro-
`tective layer 5 of the silicon nitride film, in that order from
`below. Hereinafter, a stacked structure including: the gate
`insulating film 3; the lower gate electrode 4a; the upper gate
`electrode 4b; and the gate protective layer 5 is referred to as
`a gate electrode 6a.
`In this embodiment, in the process step shown in FIG. 2A,
`the upper face of the semiconductor substrate 1 is divided
`into regions of 10x10 Mmz, and the dummy gate electrodes
`6b having completely the same structure as that of the gate
`electrodes 6a are formed in a sparse region D2 where the
`gate electrodes 6a are arranged most sparsely, concurrently
`with the formation of the gate electrodes 6a, such that the
`ratio of the surface area of a dense region D1 where the gate
`electrodes 6aare arranged most densely to the surface area of
`the sparse region D2 is 1.6 or less.
`Next, in a process step shown in FIG. 2B, impurity ions
`are implanted into the semiconductor substrate 1 using the
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`gate electrodes 6a and the isolation regions 2 as a mask,
`thereby defining first doped regions 7 to be LDD regions or
`extension doped regions.
`Next, in a process step shown in FIG. 3A, an underlying
`insulating film 8 of an NSG film (a silicon oxide film
`containing no impurities) with a thickness of about 20 nm,
`a protective insulating film 9 of a silicon nitride film with a
`thickness of about 20 nm, and a sidewall insulating film 10
`of a BPSG film with a thickness of about 100 nm are formed
`by a CVD process in this order over the substrate.
`Then, in a process step shown in FIG. 3B, the sidewall
`insulating film 10, the protective insulating film 9 and the
`underlying insulating film 8 are etched in this order by
`anisotropic dry etching, thereby forming sidewalls 11 each
`having a multilayer structure including an underlying insu-
`lating film 8a, a protective insulating film 9a and a sidewall
`insulating film 10a. Subsequently,
`impurity ions are
`implanted into the semiconductor substrate 1 using the gate
`electrodes 6a, the sidewalls 11 and the isolation regions 2 as
`a mask, thereby defining second doped regions 12 to be
`heavily-doped source/drain regions.
`the
`Thereafter,
`in a process step shown in FIG. 4A,
`sidewall
`insulating film 10a made of a BPSG film and
`included in the sidewalls 11 is selectively removed by wet
`etching, thereby forming L-shaped sidewalls 11a including
`the underlying insulating film 8a and the protective insulat-
`ing film 9a.
`Subsequently, in a process step shown in FIG. 4B, an
`interlevel dielectric film 13 of a BPSG film is deposited by
`a CVD process over the substrate, and then the surface of the
`interlevel dielectric film 13 is planarized by a CMP process.
`At this time, since the sidewall insulating film 10a used as
`a mask for forming the second doped regions 12 has been
`removed, the gate electrode 6a-to-gate electrodes 6a spacing
`and the gate electrode 6a-to-dummy gate electrode 6b
`increase. Therefore, the interlevel dielectric film 13 fills the
`gate electrode 6a-to-gate electrodes 6a spacing and the gate
`electrode 6a-to-dummy gate electrode 6b completely with-
`out creating any void.
`In the method for fabricating the semiconductor device
`according to this embodiment, in the process step shown in
`FIG. 2A, the upper face of the semiconductor substrate 1 is
`divided into regions of 10x10 ymz, and the dummy gate
`electrodes 6b are formed in the sparse region D2 where the
`density of the gate electrodes 6a is at the minimum such that
`the ratio of the surface ar