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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`IPR2017-018411
`Patent 7,893,501
`____________
`
`DECLARATION OF ALEXANDER D. GLEW
`
`
`1 Case IPR2017-01842 has been consolidated with this proceeding(cid:15916)
`IP Bridge Exhibit 2007
`TSMC v. Godo Kaisha IP Bridge 1
`IPR2017-01841
`
`
`
`

`

`
`
`TABLE OF CONTENTS
`
`C.
`
`PERSONAL AND PROFESSIONAL BACKGROUND ............................... 1
`I.
`II. MATERIALS REVIEWED AND CONSIDERED ........................................ 4
`III. MY UNDERSTANDING OF PATENT LAW ............................................... 6
`A. Obviousness ........................................................................................... 8
`IV. THE ‘501 PATENT ......................................................................................... 9
`A.
`The Protruding Gate Electrode ............................................................19
`B.
`The Protruding Gate Electrode Reduces Parasitic Capacitance
`Between the Gate Electrode and the Source/Drain Contacts ..............22
`The Claims Were Narrowed to Distinguish Gate Electrodes that
`Do Not Protrude ..................................................................................27
`THE CHALLENGED CLAIMS ...................................................................28
`V.
`VI. LEVEL OF ORDINARY SKILL IN THE ART ...........................................29
`VII. CLAIM INTERPRETATION .......................................................................30
`A.
`“wherein the MISFET includes: an active region made of a
`semiconductor substrate” (claim 1) .....................................................30
`1.
`The Petitions and Petitioner’s Expert Consistently
`Characterize the Active Region as an Area of the
`Semiconductor Substrate Defined by an Isolation Region
`Where the Transistor Is Formed ...............................................30
`The ‘501 Patent Specification Describes an Active
`Region as an Area of the Semiconductor Substrate
`Defined by an Isolation Region Where the Transistor is
`Formed ......................................................................................33
`The Specification’s Use Is Consistent with the Ordinary
`Meaning of a Transistor’s “Active Region” .............................39
`VIII. THE CHALLENGED CLAIMS WOULD NOT HAVE BEEN
`OBVIOUS ......................................................................................................45
`A. Overview of Igarashi ...........................................................................45
`B.
`Overview of Woerlee ..........................................................................49
`C.
`The Igarashi/Woerlee Device Does Not Comprise a MISFET
`that Includes an “Active Region” ........................................................51
`
`2.
`
`3.
`
`i
`
`

`

`
`
`1.
`
`2.
`
`3.
`
`b.
`
`c.
`
`d.
`
`Igarashi’s Fifth Embodiment Does Not Disclose Isolation
`Regions ......................................................................................51
`a.
`Igarashi Does Not Teach that the Fifth
`Embodiment (Fig. 12) Includes Isolation Regions ......... 51
`Isolation Regions Would Not Have Been Inherent
`in the Fifth Embodiment of Igarashi .............................. 59
`The Rationale in the Institution Decision Has Two
`Critical Mistakes ............................................................. 62
`Igarashi’s Fifth Embodiment Could Not Have
`Been Modified to Achieve Isolation of Each
`Transistor as Taught for Igarashi’s First
`Embodiment .................................................................... 67
`e. Woerlee Does Not Teach Where in the Horizontal
`Direction to Place Isolation Regions around a
`Multi-Transistor Device Like Igarashi’s Fifth
`Embodiment .................................................................... 69
`Even If Igarashi Is Considered to Teach What the
`Petitions Allege, All Challenged Claims Distinguish
`Over the Petitioner’s Alleged Igarashi/Woerlee
`Combination ..............................................................................71
`a.
`Petitioner Failed to Demonstrate How and Why
`Any MISFET in the Igarashi/Woerlee
`Combination Includes an “Active Region”
`Meeting the Agreed-Upon BRI ...................................... 72
`There Are Not Two Active Regions Bounded by
`the Alleged Isolation Region .......................................... 75
`No Transistor Includes the Region Bounded by the
`Alleged Isolation Region in the Petitions’
`Modified Igarashi Fig. 12, So There Is Not One
`Active Region ................................................................. 80
`Interpreting Claim 1 to Require That the Active
`Region Include Only a Single Transistor Is the
`Only Interpretation Supported by the Record and
`Consistent with the Specification ................................... 85
`Conclusion - Petitioner Fails to Identify a Region That
`Meets the Agreed-Upon BRI of “Active Region” ....................88
`
`b.
`
`c.
`
`d.
`
`ii
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`

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`D. None of Dependent Claims 4-7, 9-12, 14-19, 21, and 23-25
`Would Have Been Obvious Over Igarashi and Woerlee ....................89
`1.
`For the Same Reasons Set Forth Above with Respect to
`Claim 1, the Dependent Claims Would Not Have Been
`Obvious Over Igarashi and Woerlee .........................................89
`Claim 13 Is Not Rendered Obvious by Igarashi, Woerlee, and
`Hokazono. ............................................................................................91
`IX. CONCLUSION ..............................................................................................92
`X.
`SIGNATURE .................................................................................................92
`
`
`
`E.
`
`iii
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`

`

`
`
`I, Alexander D. Glew, declare:
`
`1.
`
`I have been retained by Wolf, Greenfield & Sacks, P.C., counsel for
`
`Patent Owner Godo Kaisha IP Bridge 1 (“IP Bridge”), to submit this declaration in
`
`connection with the Inter Partes Review of claims 1, 4-7, 9-19, 21, and 23-25 of
`
`U.S. Patent No. 7,893,501 (“the ’501 patent”).2 I am being compensated for my
`
`time at a rate of $515.00 per hour, plus actual expenses. My compensation is not
`
`dependent in any way upon the outcome of the Petition.
`
`I.
`
`PERSONAL AND PROFESSIONAL BACKGROUND
`2. My curriculum vitae is provided as Exhibit 2008 to this proceeding.
`
`3.
`
`I earned a B.S. degree in Mechanical Engineering from the University
`
`of California, Berkeley in 1985, a M.S. degree in Mechanical Engineering from the
`
`University of California, Berkeley in 1987, a M.S. degree in Materials Science and
`
`Engineering from Stanford University in 1995, and a Ph.D. in Materials Science
`
`and Engineering from Stanford University in 2003.
`
`
`2 Unless otherwise specified with the “-1842” prefix, references to exhibits and
`
`papers herein are to those filed in IPR2017-01841. Pin cites are not provided for
`
`the -1842 Petition or Dr. Shanfield’s -1842 declaration (Ex.-1102) where the
`
`arguments are the same as for the -1841 Petition or Dr. Shanfield’s -1841
`
`declaration (Ex.-1002).
`
`1
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`

`

`
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`4.
`
`I am the Founder and President of Glew Engineering Consulting, Inc.,
`
`based in Mountain View, California. I have been President of Glew Engineering
`
`Consulting, Inc. since I started the company in 1997. In my role as President, I
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`have provided consulting services to clients in the field of semiconductor
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`manufacturing and materials, as well as to clients in other fields. I have reviewed
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`and analyzed new semiconductor technologies and products and provided advice
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`regarding advanced semiconductor process equipment. My consulting work has
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`involved thin film characterization, process development, project
`
`turnaround/rescue, gas flow and vacuum metrology, design of experiments,
`
`corrosive gas applications, finite element analysis, and related market analysis.
`
`5.
`
`I have approximately 21 years of experience in semiconductor
`
`manufacturing and materials, including in semiconductor equipment and
`
`processing. I implemented numerous manufacturing processes for the formation of
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`semiconductors, including chemical vapor deposition (“CVD”), etch, reactive-ion
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`etching (“RIE”), chemical-mechanical planarization (“CMP”), spin-on dielectrics
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`(“SOD”), epitaxy (“EPI”), molecular beam epitaxy (“MBE”), rapid thermal
`
`processing (“RTP”), and others.
`
`6.
`
`In 1987, before receiving my Ph.D., I began working at Applied
`
`Materials, Inc. in Santa Clara, California. At Applied Materials, Inc., I served in a
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`number of roles, including Engineering Manager, Core-Technologist Project
`
`2
`
`

`

`
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`Manager, CVD Supplier Quality Engineering Manager, Core Technologist, CVD
`
`Engineering Manager, and Systems Engineer. In these roles, I provided
`
`engineering services and supervised other employees on projects related to
`
`technologies used to manufacture semiconductors, including CVD, epitaxy,
`
`physical vapor deposition (“PVD”), rapid thermal processing (“RTP”), etch, and
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`thermal. I oversaw gas, vacuum, and chemical component evaluation, testing, and
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`supplier quality management. I successfully proposed and executed a project to
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`develop industry methods to determine the effects of trace chemicals on
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`semiconductor processing and equipment reliability. I worked on the development
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`and release of the Precision 5000 CVD product, the first cluster tool for
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`semiconductor manufacturing.
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`7.
`
`I am a licensed professional mechanical engineer in the state of
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`California.
`
`8.
`
`I have published articles and presented on topics related to
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`semiconductor manufacturing. My curriculum vitae includes a list of selected
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`publications. Ex. 2008.
`
`9.
`
`I am a co-inventor of four U.S. patents: (a) U.S. Patent No. 6,204,174,
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`directed to a method and apparatus to control the deposition rate of material in a
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`semiconductor fabrication process; (b) U.S. Patent No. 9,224,626, directed to a
`
`method of forming a heater assembly for use in semiconductor processing; and (c)
`
`3
`
`

`

`
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`U.S. Patent Nos. 6,679,476 and 7,118,090, both directed to control valves for use
`
`in ultra pure applications such as semiconductor processing.
`
`10.
`
`I am a member of the American Society of Mechanical Engineers
`
`(“ASME”), International Microelectronics and Packaging Society (“IMAPS”),
`
`Materials Research Society (“MRS”), Institute of Electrical and Electronics
`
`Engineers (“IEEE”), and Semiconductor Equipment and Materials International
`
`(“SEMI”).
`
`11.
`
`I consider myself an expert in the field of semiconductor
`
`manufacturing and materials.
`
`II. MATERIALS REVIEWED AND CONSIDERED
`12. My findings, as explained below, are based on my years of education,
`
`research, experience, and background in the field of semiconductor manufacturing
`
`and materials, as well as my investigation and study of relevant materials for this
`
`declaration.
`
`13.
`
`In forming my opinions, I have studied and considered the following
`
`materials. These materials are the types of materials that an expert would
`
`reasonably consider in forming an opinion as to the validity of patent claims.
`
`(cid:120)
`
`(cid:120)
`
`U.S. Patent No. 7,893,501 to Tsutsui (“the ’501 patent,” Ex. 1001);
`
`Prosecution History for the ’501 Patent;
`
`4
`
`

`

`
`
`(cid:120)
`
`TSMC’s Petitions for Inter Partes Review of U.S. Patent No.
`
`7,893,501 (Paper 2 in IPR2017-01841 and Paper 2 in IPR2017-01842) and all
`
`exhibits filed therewith;
`
`(cid:120)
`
`Declarations of Stanley R. Shanfield (Ex. 1002 in IPR2017-01841 and
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`Ex. 1102 in IPR2017-01842);
`
`(cid:120)
`
`Patent Owner’s Preliminary Responses (Paper 6 in IPR2017-01841
`
`and Paper 6 in IPR2017-01842);
`
`(cid:120)
`
`(cid:120)
`
`Decision on Institution of Inter Partes Review (Paper 10);
`
`Transcripts of the Deposition of Stanley R. Shanfield, March 27-28,
`
`2018 (Exs. 2009, 2010) and associated exhibits (Exs. 2002-2006, 2021);
`
`(cid:120)
`
`Excerpts from Webster’s Third New International Dictionary (2002)
`
`(Ex. 2011);
`
`(cid:120)
`
`(cid:120)
`
`(cid:120)
`
`(cid:120)
`
`Excerpts from Collins English Dictionary (2000) (Ex. 2012);
`
`Excerpts from Chambers 21st Century Dictionary (2000) (Ex. 2013);
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`U.S. Patent No. 64,578,128 to Mundt et al. (“Mundt,” Ex. 2014);
`
`Request for Continued Examination dated March 29, 2010, in U.S.
`
`Patent Application Serial No. 12/170,191 (Ex. 2015);
`
`(cid:120)
`
`(cid:120)
`
`U.S. Patent No. 6,437,404 (“Xiang,” Ex. 2016);
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`U.S. Patent No. 6,870,230 (“Matsuda,” Ex. 2017);
`
`5
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`

`

`
`
`(cid:120)
`
`Office Action dated May 10, 2010, in U.S. Patent Application Serial
`
`No. 12/170,191 (Ex. 2018);
`
`(cid:120)
`
`(cid:120)
`
`U.S. Patent No. 3,390,022 (“Fa,” Ex. 2019); and
`
`Excerpts from McGraw-Hill Dictionary of Scientific and Technical
`
`Terms (2003) (Ex. 2020).
`
`III. MY UNDERSTANDING OF PATENT LAW
`14.
`In developing my opinions, I discussed various relevant legal
`
`principles with Patent Owner’s attorneys. I understood these principles when they
`
`were explained to me and have relied upon such legal principles, as explained to
`
`me, in the course of forming the opinions set forth in this declaration. My
`
`understanding in this respect is as follows:
`
`15.
`
`I understand that in this proceeding Petitioner has the burden of
`
`proving that the challenged claims of the ’501 patent are unpatentable by a
`
`preponderance of the evidence. I understand that “preponderance of the evidence”
`
`means that a fact or conclusion is more likely true than not true.
`
`16.
`
`I understand that for an invention claimed in a patent to be patentable,
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`it must be, among other things, not obvious from the prior art to a person of
`
`ordinary skill in the art (“POSA”) at the time the invention was made.
`
`6
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`

`

`
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`17.
`
`I understand the information that is used to evaluate whether a
`
`claimed invention is patentable is generally referred to as “prior art” and includes
`
`patents and printed publications (e.g., books, journal publications).
`
`18.
`
`I understand that prior art may have made the claim “obvious” to a
`
`POSA at the time the invention was made. My understanding of this legal standard
`
`is set forth below.
`
`19.
`
`I understand that “inter partes review” is a proceeding before the
`
`United States Patent & Trademark Office (“Patent Office”) for evaluating the
`
`patentability of an issued patent claim based on prior art patents and printed
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`publications.
`
`20.
`
`I understand that, during an inter partes review, claims in a patent are
`
`given their broadest reasonable interpretation (BRI) consistent with the patent
`
`specification. I understand that for claim terms not explicitly defined in the
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`specification, the BRI generally refers to the plain and ordinary meaning consistent
`
`with the specification and prosecution history. I understand that the prosecution
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`history must be considered in determining the BRI and that any explanation,
`
`elaboration, or qualification presented by the inventor is relevant because the role
`
`of claim construction is to capture the scope of the actual invention that is
`
`disclosed, described, and patented. I understand that the BRI is not simply an
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`interpretation that is not inconsistent with any specific prohibitions in the
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`7
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`

`

`
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`specification, but rather that the BRI is an interpretation that is affirmatively
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`consistent with the specification and that corresponds with how the invention is
`
`described by the inventor in the specification.
`
`A. Obviousness
`21.
`I understand that the following standards govern the determination of
`
`whether a patent claim would have been “obvious” from the prior art.
`
`22.
`
`I understand that a patent claim may be unpatentable if it is obvious in
`
`view of a single prior art reference or a combination of prior art references.
`
`23.
`
`I understand that a patent claim is obvious if the differences between
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`the subject matter of the claim and the prior art are such that the subject matter as a
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`whole would have been obvious to a person of ordinary skill in the relevant field at
`
`the time the invention was made. Specifically, I understand that the obviousness
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`question involves a consideration of:
`
`(cid:120)
`
`(cid:120)
`
`(cid:120)
`
`(cid:120)
`
`the scope and content of the prior art;
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`the differences between the prior art and the claims at issue;
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`the knowledge of a POSA in the pertinent art; and
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`whatever objective factors indicating obviousness or nonobviousness
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`may be present in any particular case – referred to as “secondary considerations.”
`
`24.
`
`I understand that such objective factors are not at issue here.
`
`8
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`

`

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`25.
`
`I understand that in order for a claimed invention to be considered
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`obvious, a person of ordinary skill in the art must have had a reason for combining
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`teachings from multiple prior art references (or for altering a single prior art
`
`reference, in the case of single-reference obviousness) in the fashion proposed.
`
`26.
`
`I understand that for a single reference or a combination of references
`
`to render the claimed invention obvious, a POSA must have been able to arrive at
`
`the claims by altering or combining the applied references.
`
`IV. THE ‘501 PATENT
`27. The ’501 patent describes and claims an improved semiconductor
`
`device comprising one or more electrically isolated MISFETs, where at least one
`
`MISFET of the device comprises, inter alia, a gate electrode and a silicon nitride
`
`film formed over from side surfaces of the gate electrode, where the gate electrode
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`“protrudes upward from a surface level of parts of the silicon nitride film located at
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`both side surfaces of the gate electrode.” A MISFET is a metal-insulator-
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`semiconductor field-effect transistor. A MOSFET (metal-oxide-semiconductor
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`field-effect transistor, sometimes simply called “MOS”) is a common type of
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`MISFET.
`
`28. A transistor is a semiconductor device that acts as a switch for
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`electronic signals. The transistor has three distinct doped areas. For example, a
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`PNP transistor includes a N-doped area between two P-doped areas, and an NPN
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`9
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`

`

`
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`transistor includes an P-doped area between two N-doped areas. The transistor can
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`be contrasted with the simplest semiconductor device, the diode, which has only
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`two distinct doped areas. The transistor can be further contrasted with a more
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`complicated semiconductor device such as a thyristor, which has four distinct
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`doped areas (such as NPNP or PNPN).
`
`29. The ’501 Patent discloses a number of embodiments. In all the
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`embodiments with multiple transistors, a semiconductor substrate 1 is divided into
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`a plurality of active regions 1a, 1b by isolation region 2, and a single MISFET is
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`formed in each active region. E.g., ’501-patent at 3:19-28. As an illustrative
`
`example, Fig. 1 of the ’501 patent shows a semiconductor device comprising two
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`MISFETs – an nMISFET and a pMISFET. Ex. 1001 (’501 patent) at 3:19-28. Fig.
`
`1 of the ’501 patent has been reproduced below. The nMISFET is shown on the
`
`left and the pMISFET is shown on the right.
`
`Channel Regions
`
`
`
`10
`
`

`

`
`
` ’501 Patent, Ex. 1001, Fig. 1, Annotated
`
`30. The nMISFET is formed in an nMISFET formation region Rn that
`
`includes active region 1a. Id. The pMISFET is formed in a pMISFET formation
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`region Rp that includes active region 1b. Id. As shown in Figure 1, the
`
`semiconductor substrate 1 is divided into a plurality of active regions 1a and 1b
`
`(highlighted in yellow above) by isolation region 2. Id.
`
`31. The nMISFET comprises n-type source/drain regions 3a and 4a (blue
`
`below), each of which comprises an n-type lightly-doped region, an n-type heavily-
`
`doped region, and a silicide layer. Id. at 3:29-32. The nMISFET also comprises a
`
`gate insulating film 5 deposited on semiconductor substrate 1 over active region
`
`1a, a gate electrode 6a (orange below) deposited on gate insulating film 5, and
`
`silicon oxide sidewalls 7 positioned on either side of gate electrode 6a. Id. at 3:32-
`
`37; see id. at 8:10-12, 8:46-49. Silicon nitride film 8 (green below) is formed over
`
`source/drain regions 3a and 4a such that gate electrode 6a protrudes upward from
`
`parts of silicon nitride film 8 located at both side surfaces of gate electrode 6a. Id.
`
`at 3:53-55, 6:62-7:12. An interlevel insulating film 9 covers the MISFET, and
`
`contacts 11 (two of which are highlighted in yellow) pass through the interlevel
`
`insulating film 9, and each connects a lead electrode 10 to one of the source/drain
`
`regions (blue below). ’501-patent at 3:59-64.
`
`11
`
`

`

`
`
`’501-patent (Ex.-1001), Figure 1 (annotated)
`
`
`
`32.
`
`In an NPN transistor such as the nMISFET shown on the left in Fig. 1
`
`of the ’501 patent, the N-type areas (e.g., source/drain regions 3a and 4a in Fig. 1)
`
`have extra negative charges (electrons), and the P-type area (in between the N-
`
`doped areas) has extra positive charges (holes). The gate electrode applies a
`
`positive voltage field to the P-type area to push away the abundant positive holes
`
`in the channel region (e.g., channel region 1x (red box above) in Fig. 1) and attract
`
`the negative electrons to the surface of the channel region. This is why the device
`
`is known as a “field effect transistor.” Consequently, there is a path for current, in
`
`the form of electrons, to flow across the source and drain. Id. at 3:37-40 (“Part of
`
`the active region 1 a located under the gate electrode 6 a is a channel region 1x in
`
`which electrons move (travel) when the nMISFET is in an operation state.”).
`
`33. The pMISFET comprises p-type source/drain regions 3b and 4b, each
`
`of which comprises a p-type lightly-doped region, a p-type heavily-doped region,
`
`12
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`

`

`
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`and a silicide layer. Id. at 3:41-44. The pMISFET also comprises a gate insulating
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`film 5 deposited on semiconductor substrate 1 over active region 1b, a gate
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`electrode 6b deposited on gate insulating film 5, and silicon oxide sidewalls 7
`
`positioned on either side of gate electrode 6b (active regions are highlighted in
`
`yellow above). Id. at 3:44-49; see id. at 8:10-12, 8:46-48. TEOS film 8b is formed
`
`over source/drain regions 3b and 4b such that gate electrode 6b protrudes upward
`
`from parts of TEOS film 8b located at both side surfaces of gate electrode 6b. Id.
`
`at 3:55-59.
`
`34.
`
`In an PNP transistor such as the pMISFET shown on the right in Fig.
`
`1 of the ’501 patent, the P-type areas (e.g., source/drain regions 3b and 4b in Fig.
`
`1) have extra positive charges (holes), and the N-type area (in between the P-doped
`
`areas) has extra negative charges (electrons). The gate electrode applies a negative
`
`voltage field to the N-type area to push away the abundant negative electrons in the
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`channel region (e.g., channel region 1y in Fig. 1) and attract the positive holes to
`
`the surface of the channel region. Consequently, there is a path for current, in the
`
`form of holes, to flow across the source and drain. Id. at 3:49-52 (“Part of the
`
`active region 1 b located under the gate electrode 6 b is a channel region 1y in
`
`which holes move (travel) when the pMISFET is in an operation state.”).
`
`35. The ease of flow across the channel of the transistor is one of the key
`
`factors in determining how fast the transistor operates. The mobility of charge
`
`13
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`

`

`
`
`carriers (electrons for the nMISFET and holes for the pMISFET) through channel
`
`regions 1x and 1y can be increased by the use of “internal stress films.” The ‘501
`
`patent describes types of internal stress films. A “first-type internal stress film”
`
`generates a tensile stress substantially parallel to the direction (referred to as the
`
`“gate length direction”) that carriers move between the source and drain. Id. at
`
`4:3-7. A “second-type internal stress film” generates a compressive stress
`
`substantially parallel to the gate length direction. Id. at 4:8-12. These films can
`
`also generate stress in the vertical direction as described in §IV.A.
`
`36. For example, in the nMISFET, a first-type internal stress film is used
`
`to generate a tensile stress in the gate length direction in the channel region of the
`
`nMISFET between the source and drain. Id. at 4:34-50. This is accomplished by
`
`using a stress film that generates a compressive stress within the film itself, and
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`applying that compressive stress “to the source region 3a and the drain region 4a in
`
`the active region 1a of the nMISFET in the parallel direction to the principal
`
`surface.” Id. A film that is in tension requires that another film be in compression
`
`to balance out the forces. As shown conceptually in the figure below, applying
`
`compressive stresses to the source and drain regions (red arrows) creates the
`
`desired tensile stress (blue arrows) in the channel region between the source and
`
`the drain regions.
`
`
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`
`
`14
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`

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`
`
`
` ‘501 Patent, Ex. 1001, Portion of Fig. 1, Annotated
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`37. For the pMISFET, the second-type internal stress film is used to
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`generate a compressive stress in the gate length direction in the channel region of
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`the pMISFET between the source and drain. Id. at 5:32-51. This is accomplished
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`by using a stress film that generates a tensile stress within the film itself, and
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`applying that tensile stress “to the source region 3b and the drain region 4b in the
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`active region 1b of the pMISFET in the parallel direction to the principal surface.”
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`Id. at 5:40-44. As shown conceptually in the simple figure below, applying tensile
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`stresses (red arrows) above the source and drain regions creates the desired
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`compressive stress (blue arrows) in the underlying channel region between the
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`source and the drain regions.
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` ‘501 Patent, Ex. 1001, Portion of Fig. 1, Annotated
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`38. Due to the piezo resistivity effect, the applied stress in channel regions
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`1x and 1y increases carrier (e.g., electron, hole) mobility within the channel
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`regions. Id. at 4:50-52, 5:49-51. In particular, applying stress to a semiconductor
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`substrate alters the crystal lattice constant and/or band structure of the substrate,
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`which impacts carrier mobility within the substrate. Id. at 1:20-22. When the
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`carriers are electrons, a tensile stress in the direction of electron movement
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`increases electron mobility, and when the carriers are holes, a compressive stress in
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`the direction of hole movement increases hole mobility. Id. at 1:30-35. The
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`increase in carrier mobility, which may be proportional to the magnitude of the
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`applied stress, may permit the device to operate at higher speeds. Id. at 1:35-36,
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`2:32-33.
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`39. Focusing on the nMISFET in the embodiments, the charge carrier
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`mobility through channel region 1x is increased by the use of silicon nitride film 8a
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`which serves as an “internal stress film[].” Id. at 2:9-14.
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`40. The ’501-patent discloses several different spatial configurations of
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`the silicon nitride film 8a that impart stress to the device in different ways. See id.
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`at Figures 1, 4A-4C. In the embodiment of Figure 4B, silicon nitride film 8a
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`(green below) covers the entire side surfaces of gate electrode 6a (orange). This
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`further increases the mobility of carriers in the channel because the gate electrode
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`is compressed downwardly which creates a compressive stress in the vertical
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`direction in the channel region. ’501-patent at 8:22-32. In the embodiment of
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`Figure 4C, silicon nitride film 8a covers the entire side and upper surfaces of gate
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`electrode 6a. In the configuration, the gate electrode is compressed downwardly
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`even more strongly which creates even greater compressive stress in the vertical
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`direction in the channel region and thereby increases carrier mobility in the
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`channel even further than in the Figure 4B embodiment. ’501-patent at 8:59-9:3.
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`’501-patent (Ex.-1001), Figures 4B and 4C (annotated)
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`41.
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`In the Figs. 1 and 4A embodiments, the silicon nitride film is not
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`located on the upper or upper side surfaces of the gate electrode. This is because
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`the silicon nitride film is reduced in thickness to remove the portions of the silicon
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`nitride film located on the upper or upper side surfaces of the gate electrode. ’501-
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`patent at 6:62-7:12, 9:53-10:3. As shown in Figure 2B and 5A, the silicon nitride
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`film 8x covers the side and upper surfaces of the gate electrode. As described in
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`the ’501 specification, a “part of the silicon nitride film 8x located on the gate
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`electrode 6a is removed” resulting in the silicon nitride film 8a not covering the
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`upper and upper side surfaces of the gate electrode in Figures 1 and 4a. ’501-
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`patent at 6:62-7:12, 9:53-10:3. Thus, gate electrode 6a (orange below) protrudes
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`upward from parts of silicon nitride film 8a located at, i.e., closest to, both side
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`surfaces of gate electrode 6a. Id. at 3:29-37, 8:10-14, 3:53-55, 6:62-7:12. In Fig.
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`1, sidewall 7 spaces the silicon nitride film from the gate electrode 6a. In Fig. 4A,
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`there is no spacer which allows silicon nitride film 8a to apply stress to the
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`substrate closer to the channel which increases the tensile stress across channel
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`region 1x in Figure 4A over that of the tensile stress in Figure 1. ’501-patent at
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`4:34-52, 8:1-9. In other words, the embodiment shown in Fig. 4A allows the
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`“space between respective parts of the source and drain regions 3a and 4a being in
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`contact with the [silicon nitride film] 8a” to be small. ’501 patent at 5:6-10. This
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`proximity increases the stress in the channel region 1x compared to the first
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`embodiment, e.g. Fig. 1. Id.
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`’501-patent (Ex.-1001), Figures 1 and 4A (annotated)
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`A. The Protruding Gate Electrode
`42.
`In the prosecution history, the applicant identified that the Fig. 1 and
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`4A embodiments support the protruding gate electrode limitation. Ex.-1003 at 8-9.
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`As discussed above, these embodiments were formed by removing the silicon
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`nitride film covering the upper and upper side surfaces of the gate electrode. ’501-
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`patent at 6:62-7:12, 9:53-10:3.
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`’501-patent (Ex.-1001), Figures 1 and 4A (annotated)
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`43. The protruding gate embodiments are clearly contrasted in the
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`specification with other embodiments where the gate electrode does not protrude
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`(e.g., Figures 4B and 4C). For example, as can be seen in Figures 4B and 4C, the
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`silicon nitride film is located on the upper and upper side surfaces of the gate
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`electrode. ’501-patent at 8:22-33 (Figure 4B increases mobility over Figure 4A
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`where “[I]nternal stress film 8a and the gate electrode 6a are in contact with each
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`other substantially at the entire side surface of the gate electrode 6a.”), 8:59-9:3
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`(Figure 4C increases mobility over Figure 4B where “[I]nternal stress film 8a and
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`the gate electrode 6a are in contact with each other substantially at the entire side
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`and upper surfaces of the gate electrode 6a.”).
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`’501-patent (Ex.-1001), Figures 4B and 4C (annotated)
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`44. The specification further distinguishes between the embodiments
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`where the gate electrode is fully covered by the silicon nitride film (e.g., Figures
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`4B and 4C), and those where it protrudes (e.g., Figures 1 and 4A) based on their
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`different abilities to apply stress to the channel region. As discussed above, the
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`other embodiments (e.g., figures 4B and 4C) have increased mobility over that of
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`the protruding gate electrode embodiments because the silicon nitride located on
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`the upper and upper side surfaces of the gate electrode causes the gate electrode to
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`be compressed downwardly which causes compressive vertical stress in the
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`channel region. ’501-patent at 8:22-32, 8:59-9:3. A POSA would have understood
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`that the increased mobility that comes from fully covering the side surfaces of the
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`gate electrode comes with a cost (increased parasitic capacitance from the silicon
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`nitride film located on the upper and upper side surfaces of the gate electrode) and
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`that the relative “advantage” of the protruding gate electrode embodiments is
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`reduced parasitic capacitance (from the removal of the silicon nitride film located
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`on the upper and upper side surfaces of the gate electrode). See §III.B below.
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`Nonetheless, as noted above, between the protruding gate electrode embodiments,
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`the embodiment shown in Fig. 4A increases carrier mobility over that of Figure 1.
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`B.
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`T