Case 2:17-cv-00100-JRG-RSP Document 6 Filed 02/01/17 Page 1 of 9 PagelD #: 74
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
`
`GODO KAISHA IP BRIDGE 1,
`
`Plaintiff,
`
`v.
`
`XILINX, INC.,
`
`Defendant.
`
`
`
`Case No. 2: 17-cv-00100
`
`JURY TRIAL DEMANDED
`
`PLAINTIFF’8 FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT
`
`Plaintiff Godo Kaisha IP Bridge 1 (“Plaintiff’ or “IP Bridge”) files this First Amended
`
`Complaint for Patent Infringement (“Complaint”) against Defendant Xilinx, Inc. (“Defendant” or
`
`“Xilinx”). Plaintiff alleges as follows:
`
`NATURE OF THE ACTION
`
`1.
`
`This is an action for infringement of US. Patent No. 7,893,501 (the “’501
`
`patent”), and US. Patent No. 7,265,450 (the “’450 Patent”).
`
`2.
`
`IP Bridge is a Japanese corporation having a principal address of c/o Sakura Sogo
`
`Jimusho, 1-11 Kanda Jimbocho, Chiyoda-ku, Tokyo 101—0051 Japan.
`
`3.
`
`Xilinx, Inc. is a Delaware corporation with its principal place of business located
`
`at 2100 Logic Drive, San Jose, California 95154. Xilinx maintains a substantial presence in this
`
`State through its regional sales office located at 5801 Tennyson Parkway, Suite 460, Plano,
`
`Texas 75024. Xilinx can be served via its registered agent for service of process, CT Corporation
`
`System, 1999 Bryan Street, Suite 900, Dallas, Texas 75201. Upon information and belief, Xilinx
`
`is registered with the Texas Secretary of State to conduct business in Texas and has been since at
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT — Page 1
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`TSMC v. Godo Kaisha IP Bridge 1
`|PR2017-01841
`
`TSMC 1021
`
`

`

`Case 2:17-cv—00100—JRG-RSP Document 6 Filed 02/01/17 Page 2 of 9 PagelD #: 75
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`least June 8, 1990. Xilinx conducts business operations within the Eastern District of Texas
`
`through its facilities in Plano, Texas.
`
`JURISDICTION AND VENUE
`
`4.
`
`This action arises under the Patent Laws of the United States, 35 U.S.C. § 1, et
`
`seq., including 35 U.S.C. §§ 271, 281, 283, 284, and 285. This is a patent infringement lawsuit,
`
`over which this Court has subject matter jurisdiction under 28 U.S.C. §§ 1331 and 1338(a).
`
`5.
`
`This Court has general and specific personal jurisdiction over Defendant because
`
`it is present in and transacts and conducts business in and with residents of this District and the
`
`State of Texas. 1P Bridge’s causes of action arise, at least in part, from Defendant’s contacts with
`
`and activities in this State and this District. In addition, upon information and belief, Defendant
`
`has committed acts of infringement within this District and this State by, inter alia, making,
`
`selling, offering for sale, importing, and/or using products that infringe one or more claims of the
`
`patents-in-suit. Defendant, directly and/or through intermediaries, uses, sells, ships, distributes,
`
`offers for sale, and/or advertises or otherwise promotes products in this State and this District.
`
`Defendant regularly conducts and solicits business in, engages in other persistent courses of
`
`conduct in, and/or derives substantial revenue from goods and services provided to residents of
`
`this State and this judicial District.
`
`6.
`
`Upon information and belief, Defendant has purposefully and voluntarily placed
`
`one or more infringing products into the stream of commerce with the expectation that they will
`
`be purchased and/or used by residents of this District and/or incorporated into downstream
`
`products purchased by consumers in this District, including by directly or indirectly working
`
`with subsidiaries, distributors, and other entities located within this District and this State .
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT — Page 2
`
`

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`Case 2:17-cv-OOlOO-JRG-RSP Document 6 Filed 02/01/17 Page 3 of 9 PagelD #: 76
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`7.
`
`Defendant maintains highly interactive and commercial websites, accessible to
`
`residents of Texas and this judicial District, through which Defendant promotes its products and
`
`services, including products that infringe the patents-in-suit.
`
`8.
`
`Venue is proper in this District under 28 U.S.C. §§ 1391 and l400(b) for at least
`
`the reasons set forth above.
`
`COUNT ONE: INFRINGEMENT OF US. PATENT NO. 7,893,501
`
`9.
`
`IP Bridge adopts and restates the allegations in paragraphs 1-8 as if fiilly set forth
`
`herein.
`
`10.
`
`On February 22, 2011, the United States Patent and Trademark Office issued the
`
`’50] Patent, “Semiconductor Device Including MISFET Having Internal Stress Film” A true and
`
`correct copy of the ’501 Patent is attached hereto as Exhibit A.
`
`11.
`
`By assignment, Plaintiff owns the entire right, title, and interest in and to the ’501
`
`patent, including the right to sue and recover damages, including damages for past infringement.
`
`12.
`
`Defendant has had knowledge of the ’501 patent no later than September 21,
`
`2016—the date on which the parties met and Plaintiff IP Bridge provided specific notice that
`
`Defendant was practicing the ’501 patent.
`
`13.
`
`The ’501 patent is valid and enforceable.
`
`l4.
`
`Defendant has at no time, either expressly or impliedly, been licensed under the
`
`’50] patent.
`
`15.
`
`Upon information and belief, Defendant has been and now is directly, literally
`
`under 35 U.S.C. § 271(a), and/or equivalently under the doctrine of equivalents, infringing the
`
`’501 patent by making, using, selling, offering for sale, and/or importing in or into the United
`
`States, without authority, products that fall within the scope of one or more claims of the ’501
`
`PLAINTIFF’8 FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT — Page 3
`
`

`

`Case 2:17—cv—OOlOO—JRG—RSP Document 6 Filed 02/01/17 Page 4 of 9 PageID #: 77
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`patent including, but not limited to, the Kintex-7 28nm FPGA family of programmable
`
`integrated circuits, and devices that perform substantially the same function in substantially the
`
`same way to achieve substantially the same result (the “FPGA devices”). Upon information and
`
`belief, all Xilinx devices employing Xilinx’s 28nm technology, including the FPGA devices
`
`noted above, infringe the ’501 patent because each accused Xilinx product and device comprises
`
`a MISFET with all additional elements recited in at least claims 1, 5-7, 10, 11, 15-19, 21, and 23-
`
`25 of the ’501 patent. In particular, each accused Xilinx product’s and device’s circuit includes
`
`an active region made of a semiconductor substrate, a gate-insulating film formed on the active
`
`region, a gate electrode formed on the gate-insulating film, source/drain regions formed in
`
`regions of the active region located on both sides of the gate electrode, a silicon nitride film
`
`formed over from side surfaces of the gate electrode to upper surfaces of the source/drain regions
`
`wherein the silicon nitride film is not formed on an upper surface of the gate electrode and the
`
`gate electrode protrudes upward from a surface level of parts of the silicon nitride film located at
`
`both side surface of the gate electrode. As an example, Xilinx’s infringement of at least claim 1
`
`of the ’501 patent by the Kintex-7 28nm FPGA is illustrated in the charts attached hereto as
`
`Exhibit B.
`
`16.
`
`Since no later than the date upon which it first learned of the ’501 patent,
`
`Defendant has induced, and is continuing to actively and knowingly induce, with specific intent,
`
`infringement of the ’501 patent by its customers under 35 U.S.C. § 271(b). Defendant further has
`
`contributed to the infringement of the ’501 patent under 35 U.S.C. § 271(c), by making, using,
`
`offering for sale, selling, and/or importing image sensors. Defendant encourages and facilitates
`
`infringing sales and uses of image sensors through the creation and dissemination of promotional
`
`and marketing materials, instructional materials, product manuals, and/or technical materials to
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT - Page 4
`
`

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`Case 2:17-cv-00100—JRG-RSP Document 6 Filed 02/01/17 Page 5 of 9 PagelD #: 78
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`manufacturers and/or distributors. Defendant contributes to infringement by others, including
`
`manufacturers, distributors, resellers, and end users, knowing that its FPGA devices constitute a
`
`material part of the inventions of the ’501 patent, knowing those FPGA devices to be especially
`
`made or adapted to infringe the ’501 patent, and knowing that those FPGA devices are not staple
`
`articles or commodities of commerce suitable for substantial non-infringing use. Defendant
`
`knew, or should have known, that its encouragement would result in infringement of at least one
`
`claim of the ’501 patent.
`
`l7.
`
`Defendant has and is continuing to willfully infringe the ’501 patent by, at
`
`minimum, continuing to engage in infringing activities after Plaintiff notified Defendant of
`
`Defendant’s infringement. For that reason, Defendant has acted despite an objectively high
`
`likelihood that its actions constituted infringement of a valid patent and such objective risk of
`
`infringement was known to Defendant or so obvious that Defendant should have known it.
`
`COUNT TWO: INFRINGEMENT OF US. PATENT NO. 7,265,450
`
`18.
`
`[P Bridge restates the allegations in paragraphs 1-8 as if fully set forth herein.
`
`19.
`
`On September 4, 2007, the United States Patent and Trademark Office issued the
`
`’450 Patent, “Semiconductor Device and Method for Fabricating the Same.” A true and correct
`
`copy of the ’450 Patent is attached hereto as Exhibit C.
`
`20.
`
`By assignment, Plaintiff owns the entire right, title, and interest in and to the ’450
`
`Patent, including the right to sue and recover damages, including damages for past infringement.
`
`21.
`
`Defendant has had knowledge of the ’450 patent no later than September 21,
`
`2016—the date on which the parties met and Plaintiff IP Bridge provided specific notice that
`
`Defendant was practicing the ’450 patent.
`
`22.
`
`The ’450 Patent is valid and enforceable.
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT — Page 5
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`

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`Case 2:17—cv-OOlOO-JRG-RSP Document 6 Filed 02/01/17 Page 6 of 9 PagelD #: 79
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`23.
`
`Defendant has at no time, either expressly or impliedly, been licensed under the
`
`’450 patent.
`
`24.
`
`Upon information and belief, Defendant has been and now is directly, literally
`
`under 35 U.S.C. § 271(a), and/or equivalently under the doctrine of equivalents, infringing the
`
`’450 patent by making, using, selling, offering for sale, and/or importing in or into the United
`
`States, without authority, products that fall within the scope of one or more claims of the ’450
`
`patent including, but not limited to, the Kintex-7 28mm FPGA and Virtex-6 40nm FPGA device
`
`families of programmable semiconductors and devices that perform substantially the same
`
`function in substantially the same way to achieve substantially the same result (the “FPGA
`
`device families”). Upon information and belief, all Xilinx devices employing Xilinx’s 28nm
`
`technology and all devices employing the 40nm technology, including the FPGA devices noted
`
`above, infringe the ’450 patent because each accused Xilinx product and device is a
`
`semiconductor comprising a substrate, a first interlayer dielectric film provided on the substrate,
`
`a first interconnect provided within the first interconnect groove with convex or concave portions
`
`at least at one of its side surfaces and bottom surface, a second interlayer dielectric film provided
`
`over the first interlayer dielectric film and the first interconnect, and a first plug that passes
`
`through the second interlayer dielectric film and comes into contact with a part of the first
`
`interconnect and any and all additional elements recited in at least claims 1, 2, 3, 8, 10,
`
`l l, 13
`
`and 14 of the ’450 patent. As an example, Xilinx’s infiingement of at least claim 1 of the ’450
`
`patent by the Kintex-7 28nm FPGA is illustrated in the charts attached hereto as Exhibit D.
`
`25.
`
`Since no later than the date upon which it first learned of the ’450 patent,
`
`Defendant has induced, and is continuing to actively and knowingly induce, with specific intent,
`
`infringement of the ’450 patent by its customers under 35 U.S.C. § 271(b). Defendant further has
`
`PLAINTIFF’8 FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT — Page 6
`
`

`

`Case 2:17-cv—OOlOO—JRG—RSP Document 6 Filed 02/01/17 Page 7 of 9 PageID #: 8O
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`contributed to the infringement of the ’450 patent under 35 U.S.C. § 271(c), by making, using,
`
`offering for sale, selling, and/or importing image sensors. Defendant encourages and facilitates
`
`infringing sales and uses of image sensors through the creation and dissemination of promotional
`
`and marketing materials, instructional materials, product manuals, and/or technical materials to
`
`manufacturers and/or distributors. Defendant contributes to infringement by others, including
`
`manufacturers, distributors, resellers, and end users, knowing that its FPGA device families
`
`constitute a material part of the inventions of the ’450 patent, knowing those FPGA device
`
`families to be especially made or adapted to infringe the ’450 patent, and knowing that those
`
`FPGA device families are not staple articles or commodities of commerce suitable for substantial
`
`non-infringing use. Defendant knew, or should have known, that its encouragement would result
`
`in infringement of at least one claim of the ’450 patent.
`
`26.
`
`Defendant has and is continuing to willfully infringe the ’450 patent by, at
`
`minimum, continuing to engage in infringing activities after Plaintiff notified Defendant of
`
`Defendant’s infringement. For that reason, Defendant has acted despite an objectively high
`
`likelihood that its actions constituted infringement of a valid patent and such objective risk of
`
`infringement was known to Defendant or so obvious that Defendant should have known it.
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT — Page 7
`
`

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`Case 2:17-cv—00100-JRG-RSP Document 6 Filed 02/01/17 Page 8 of 9 PagelD #: 81
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`PRAYER FOR RELIEF
`
`Plaintiff prays for the following relief:
`
`A.
`
`A judgment that Xilinx has infringed and continues to infringe the ’50] and ’450
`
`patents;
`
`B.
`
`A judgment and order requiring the Xilinx to pay IP Bridge damages under 35
`
`U.S.C. § 284, including treble damages for willful infringement as provided by 35 U.S.C. § 284,
`
`and supplemental damages for any continuing post-verdict infringement up until entry of the
`
`final judgment with an accounting as needed;
`
`C.
`
`A judgment and order requiring Xilinx to pay IP Bridge pre—judgment and
`
`post-judgment interest on the damages awarded;
`
`D,
`
`A judgment and order finding this to be an exceptional case and requiring Xilinx
`
`to pay the costs of this action (including all disbursements) and attorneys’ fees as provided by 35
`
`U.S.C. § 285;
`
`E.
`
`A permanent injunction against Xilinx’s direct infringement, active inducements
`
`of infringement, and/or contributory infringement of the ’501 and ’450 patents, as well as against
`
`each of Xilinx’s agents, employees, representatives, successors, and assigns, and those acting in
`
`privity or in concert with Xilinx;
`
`F.
`
`G.
`
`In the event a final injunction is not awarded, a compulsory on-going royalty; and
`
`Such other and fiirther relief as the Court deems just and equitable.
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT — Page 8
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`

`

`Case 2:17-cv-00100—JRG-RSP Document 6 Filed 02/01/17 Page 9 of 9 PagelD #: 82
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`DATED: February 1, 2017
`
`/s/ Michael W. Shore
`Michael W. Shore, Texas Bar No. 18294915
`Lead Attomey
`mshore@shorechan.com
`Alfonso Garcia Chan, Texas Bar No. 24012408
`achan@shorechan.com
`Jennifer M. Rynell, Texas Bar No. 24033025
`jrynell@shorechan.com
`Christopher L. Evans, Texas Bar No.24058901
`cevans@shorechan.com
`Russell DePalma, Texas Bar No.00795318
`
`redepalma@shorechan.com
`Ari Rafilson, Texas Bar No. 24060465
`arafilson@shorechan.com
`Andrew M. Howard, Texas Bar No. 24059973
`ahoward@shorechan.com
`
`SHORE CHAN DePUMPO LLP
`
`901 Main Street, Suite 3300
`Dallas, Texas 75202
`Telephone: 214-593-91 10
`Facsimile: 214-593-9111
`
`Hiromasa Ohashi*
`
`ohashi@ohashiandhorn.com
`Jeff J. Horn Jr., Texas Bar No. 24027234
`horn@ohashiandhorn.com
`Cody A. Kachel, Texas Bar No. 24049526
`ckachel@ohashiandhom.com
`OHASHI & HORN LLP
`
`325 North Saint Paul Street, Suite 4400
`
`Dallas, Texas 75201
`Telephone: 214-743-4170
`Facsimile: 214—743-4179
`
`Attorneys for Plaintiff Godo Kaisha IP Bridge 1
`
`*Motion for pro hac vice admission to be filed
`
`PLAINTIFF’S FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT — Page 9
`
`

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`Case 2:17-cv-OOlOO—JRG-RSP Document 6-1 Filed 02/01/17 Page 1 of 21 PageID #: 83
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`EXHIBIT A
`
`

`

`case 2:17‘CV‘00100‘JRG'RSP Dme’“ IIIIIlfllllllfllflillllllllllllflflflllfllfllllflflllflfilfiiflli 84
`
`USOO7893SOIB2
`
`(12) United States Patent
`Tsutsui et al.
`
`(10) Patent No.:
`
`(45) Date of Patent:
`
`US 7,893,501 BZ
`*Feb. 22, 2011
`
`(54) SEMICONDUCTOR DEVICE INCLUDING
`MISFET HAVING INTERNAL STRESS FILM
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,023,676 A
`
`6/1991 Tatsuta
`
`(75)
`
`Inventors: Masafumi Tsutsui, Osaka (JP);
`Hiroyuki Umimoto, Hyogo (JP); Kaori
`Akamatsu, Osaka (JP)
`
`(73) Assignee: Panasonic Corporation, Osaka (JP)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`This patent is subject to a terminal dis-
`claimer.
`
`(21) Appl.No.: 12/170,191
`
`(22) Filed:
`
`Jul. 9, 2008
`
`(65)
`
`Prior Publication Data
`
`US 2009/0050981 A1
`
`Feb. 26, 2009
`
`Related U.S. Application Data
`
`(63) Continuation of application No. 11/730,988, filed on
`Apr. 5, 2007, now Pat. No. 7,417,289, which is a con-
`tinuation of application No. 10/859,219, filed on Jun.
`3, 2004, now Pat. No. 7,205,615.
`
`(30)
`
`Foreign Application Priority Data
`
`Jun. 16, 2003
`
`(JP)
`
`.......................... 2003-170335
`
`(51)
`
`Int. Cl.
`(2006.01)
`H01L 29/76
`(2006.01)
`H01L 29/94
`(2006.01)
`H01L 31/062
`(2006.01)
`H01L 31/113
`(2006.01)
`H011. 31/119
`(52) U.S. Cl.
`.................................................... 257/369
`(58) Field of Classification Search
`..
`257/369
`See application file for complete search history.
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`52-120776
`
`10/1977
`
`(Continued)
`OTHER PUBLICATIONS
`
`Shimizu, A., et 3]., “Local Mechanical-Stress ComtIol (LMC): A
`New Technique for CMOS_Performa.nce Enhancement”, 2001,
`IEDM 01. p. 19.4.1-19.4.4.
`
`(Continued)
`
`Primary Examiner—Howard Weiss
`(74) Attorney. Agent, or Firm—McDermott Will & Emery
`LLP
`
`(57)
`
`ABSTRACT
`
`A semiconductor device includes a first-type internal stress
`film formed of a silicon oxide film over source/drain regions
`ofan nM'ISFET and a second-type internal stress film formed
`ofa TEOS film over source/drain regions ofa pMISFET. In a
`channel region of the 11M]SFET, a tensile sness is generated
`in the direction ofmovement ofdemons due to the first-type
`internal stress film, so that the mobility of elections is
`increased. In a channel region ofthe pMISFET, a compressive
`stress is generated in the direction of movement ofholes due
`to the second-type internal stress film, so that the mobility of
`holes is increased.
`
`25 Claims, 9 Drawing Sheets
`
`Rn
`
`
`Rp
`f—~—/;fi
`
`
`
`

`

`Case 2:17-cv-00100—JRG-RSP Document 6-1 Filed 02/01/17 Page 3 of 21 PagelD #: 85
`
`US 7,893,501 B2
`
`Page 2
`
`us. PATENT DOCUMENTS
`
`2005/0194596 A1
`
`9/2005 Chan eta].
`
`6,437,404 B1 *
`6,573,172 Bl
`6.870230 32*
`6,977,194 BZ
`
`............
`
`8/2002 Xiang a a1.
`6/2003 En eta].
`............ 257/365
`3/2005 Matsudaetal.
`12/2005 Belyansky et 211.
`
`257/347
`
`g
`n,
`JP
`
`FOREIGN PATENT DOCUMENTS
`(fig-33233 A
`1;;:33;
`2003_086708
`3/2003
`2004-193166
`7/2004
`
`7’022’561 B2
`7305515 32 "
`7,417,289 B2 *
`2003/0040158 A1
`2004/0075148 A1
`
`4/2006 Huang et 31'
`4/2007 Tsutsui 9t 31- -------------- 257/359
`8/2008 Tsutsui et a1.
`............... 257/369
`2/2003 Saitoh
`4/2004 Kumagai et a1.
`
`Japanese Ofiice Action, with English u-anslation, issued in Japanese
`Patent Application No. zoos-170335, mailed Dec. 22, 2009.
`Japanese Office Action, with English Innslation, issued in Japanese
`Patent Application No. 2003—170335, mailed Mar. 23, 2010.
`* cited by examiner
`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 4 of 21 PageID #: 86
`
`US. Patent
`
`Feb. 22, 2011
`
`Sheet 1 of 9
`
`US 7,893,501 B2
`
`FIG.1
`
`Rn
`
`
`Rp
`
`
`10
`
`8a
`
`5 4b 2
`
`1ylb
`
`2
`
`3a
`
`1X18
`
`5 4
`
`a
`
`2
`
`3b
`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 5 of 21 PagelD #: 87
`
`US. Patent
`
`Feb. 22, 2011
`
`Sheet 2 of9
`
`US 7,893,501 B2
`
`FIG. 2A
`
`Rn
`
`Rp
`
`
`
`FIG. 2B
`
`
`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 6 of 21 PagelD #: 88
`
`US. Patent
`
`Feb. 22, 2011
`
`Sheet 3 of9
`
`US 7,893,501 B2
`
`FIG.3A
`
`Rn
`
`
`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 7 of 21 PagelD #: 89
`
`US. Patent
`
`Feb. 22, 2011
`
`Sheet 4 of9
`
`US 7,893,501 B2
`
`Rp
`Rn
`FIG. 4A
`
`
`8a
`
`8a
`
`FIG. 4B
`
`FIG. 4C
`
`8a
`
`11
`
`11
`
`
`
`
`
`
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`iglfl§13\“:23!
`
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`
`

`

`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 8 of 21 PagelD #: 90
`
`US. Patent
`
`Feb. 22, 2011
`
`Sheet 5 of9
`
`US 7,893,501 B2
`
`FIG 5A
`
`Rn
`Rp
`
`
`12
`
`FIG. 5B
`
`i-333555:'-':.3.:5.'?.:-'.:-':‘-'."3_"_'-'_'3.‘i:'_'-'\_"-:':’:':':':':
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`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 9 of 21 PagelD #: 91
`
`US. Patent
`
`Feb. 22, 2011
`
`Sheet 6 of9
`
`US 7,893,501 B2
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`Case 2:17-cv-00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 10 of 21 PageID #: 92
`
`US. Patent
`
`Feb. 22, 2011
`
`Sheet 7 of9
`
`US 7,893,501 32
`
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`US 7,893,501 B2
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`U.S. Patent
`
`Feb. 22, 2011
`
`Sheet 9 of9
`
`US 7,893,501 B2
`
`FIG. 9A
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`Case 2:17-cv—00100-JRG-RSP Document 6-1 Filed 02/01/17 Page 13 of 21 PageID #: 95
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`US 7,893,501 B2
`
`1
`SEMICONDUCTOR DEVICE INCLUDING
`MISFET HAVING INTERNAL STRESS FILM
`
`RELATED APPLICATIONS
`
`This application is a Continuation of US. application Ser.
`No. 11/730,988, filed Apr. 5, 2007, now US. Pat. No. 7,417,
`289, which is a Continuation of US. application Ser. No.
`10/859,219, filed Jun. 3, 2004, now US. Pat. No. 7,205,615,
`and claiming priority of Japanese Application No. 2003-
`170335, filed Jun. 16, 2003, the entire contents of each of
`which are hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a semiconductor device
`including an MISFET and a method for fabricating the same,
`and more particularly relates to a measure for increasing the
`mobility of carriers.
`When a stress is generated in a semiconductor crystal layer,
`a crystal-lattice constant varies and a band structure is
`changed, so that the mobility of carriers is changed. This
`phenomenon has been known as the “piezo resistivity efi'ect”.
`Whether the carrier mobility is increased or reduced differs
`depending on the plane direction of a substrate, the direction
`in which carriers move, and whether the stress is a tensile
`stress or a compressive stress. For example, in an Si (100)
`substrate, i.e., a silicon substrate of which the principal sur-
`face is the {100} plane, assume that carriers move inthe[011]
`direction. When carriers are electrons, with a tensile stress
`generated in the direction in which electrons in a channel
`region move, the mobility of the carriers is increased. On the
`other hand, when carriers are holes, with a compressive stress
`generated in the direction in which holes in a channel region
`move, the mobility of the carriers is increased. The increase
`rate of carrier mobility is proportional to the size of a stress.
`In this connection, conventionally, there have been propos-
`als for increasing canier mobility by applying a stress to a
`semiconductor crystal layerto increase the operation speed of
`transistors and the like. For example, in Reference 1 , an entire
`semiconductor substrate is bent using an external device,
`thereby generating a stress in an active region of a transistor.
`
`2
`The intemal stress film is capable of covering one or both
`of source/drain regions. In an nMJSFET, the internal stress
`film generates a tensile stress substantially in the parallel
`direction to a gate length direction in a channel region (i.e.,
`the direction of movement of electrons). In a pMISFET, the
`internal stress film generates a compressive stress substan-
`tially in the parallel direction to a gate length direction in a
`channel region (i.e., the direction of movement of holes).
`Covering both side surfaces or both side and upper surfaces
`of a gate electrode, the internal stress film can generate a
`stress in the longitudinal direction of the channel region
`through the gate electrode, thereby increasing the mobility of
`carriers.
`
`Moreover, covering a side surface ofthe gate electrode and
`an upper surface of the semiconductor substrate in two
`regions of the substrate sandwiching part of the gate elec-
`trode, whether the MISFET is an nMISFET or a pMISFET,
`the internal stress film can generate a tensile stress substan-
`tially in the parallel direction to the gate width direction ofthe
`MISFET, thereby increasing the mobility of carriers.
`A first method for fabricating a semiconductor device
`according to the present invention is a method in which an
`nMISFET and a pMISFET are formed in first and second
`active regions ofa semiconductor substrate, respectively, and
`then first and second internal stress films which cover source/
`drain regions ofthe nMISFET and source/drain regions ofthe
`pMISFET, respectively, and generate a tensile stress and a
`compressive stress, respectively, substantially in the parallel
`directions to respective gate length directions of the channel
`regions are formed.
`According to this method, a CMOS device of which the
`operation speed is increased can be obtained.
`A second method for fabricating a semiconductor device
`according to the present invention is a method in which an
`internal stress film is formed first, a groove is formed in the
`internal stress film, a gate insulating film and a buried gate
`electrode are formed inthe groove, and then the internal stress
`film is removed.
`
`According to this method, a stress which increases the
`mobility of carriers in the channel region can be generated
`using a remaining stress in the gate insulating film.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`SUMMARY OF THE INVENTION
`
`45
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`in the above-described known structure, an
`However,
`external device is needed in addition to a semiconductor
`substrate and a stress can be generated only in the same
`direction in an entire region ofthe semiconductor substrate in
`which active regions of a transistor and the like are provided
`and which is located in the principal surface side. For
`example, when an Si (100) substrate is used, neither the
`mobility of electrons nor the mobility of holes can be
`increased
`
`It is therefore an object ofthe present invention to provide,
`by generating a stress which increases the mobility ofcarriers
`in a semiconductor layer without using an external device, a
`semiconductor device including a pMISFET and an nMIS-
`FET ofwhichrespective operation speeds are increased and a
`method for fabricating the same.
`A semiconductor device according to the present invention
`includes an internal stress film for generating a stress in a gate
`length direction in a channel region of an active region in
`which a MISFET is formed.
`
`Thus, the mobility of carriers in the MISFET can be
`increased by using the piezo resistivity effect.
`
`50
`
`FIG. 1 is a cross-sectional view illustrating a semiconduc-
`tor device according to a first embodiment of the present
`invention.
`
`FIG. 2A through 2C are cross-sectional views illustrating
`first halfofrespective steps for fabricating the semiconductor
`device of the first embodiment.
`
`FIG. 3A through 3C are cross-sectional views illustrating
`latter halfofrespective steps for fabricating the semiconduc-
`tor device of the first embodiment.
`
`55
`
`FIGS. 4A through 4C are cross-sectional views illustrating
`first, second and third modified examples ofthe first embodi-
`ment.
`
`FIGS. 5A through 5D are cross-sectional views illustrating
`respective steps for fabricating a semiconductor device
`according to the first modified example of the first embodi-
`ment.
`
`FIGS. 6A through 6C are cross-sectional views illustrating
`respective steps for fabricating a semiconductor device
`according to the third modified example of the first embodi-
`ment.
`
`60
`
`65
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`

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`Case 2:17-cv-00100—JRG-RSP Document 6-1 Filed 02/01/17 Page 14 of 21 PagelD #: 96
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`US 7,893,501 B2
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`3
`FIGS. 7A through 7D are cross-sectional views illustrating
`first half of respective steps for fabricating a semiconductor
`device according to a second embodiment of the present
`invention.
`
`FIGS. 8A through 8D are cross-sectional views illustrating
`latter halfof respective steps for fabricating the semiconduc-
`tor device of the second embodiment.
`FIGS. 9A and 9B are a plane view of an MISFET of a
`semiconductor device according to a third embodiment ofthe
`present invention and a cross-sectional View illustrating a
`cross-sectional structure taken along the line Di-IX (a cross
`section in the gate width direction), respectively.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`First Embodiment
`
`FIG. 1 is a cross-sectional View illustrating a semiconduc-
`tor device according to a first embodiment of the present
`invention. As shown in FIG. 1, a surface region of a semicon-
`ductor substrate 1, i.e., an Si (100) substrate is divided into a
`plurality ofactive regions la and lb by an isolation region 2.
`The semiconductor device includes an nMISFET formation
`region Rn which includes the active region 1a and in which an
`nMISFET is to be formed and a pMISFET formation region
`Rp which includes the active region 1b and in which a pMIS-
`FET is to be formed.
`The nMISFET includes n-type source/drain regions 3a and
`4a each of which includes an n—type lightly doped impurity
`region, an n-type heavily doped impurity region and a silicide
`layer such as a CoSi2 layer, a gate insulating film 5 formed on
`the active region 1a and made ofa silicon oxide film, a silicon
`oxynitride film or the like, a gate electrode 6a formed on the
`gate insulating film 5 and made of polysilicon, aluminum or
`the like, and a sidewall 7 covering a side surface of the gate
`electrode 6a and made ofan insulating film. Part ofthe active
`region la located under the gate electrode 6a is a channel
`region 1x in which electrons move (travel) when the nMIS-
`FET is in an operation state.
`The pMISFET includes p-type source/drain regions 31) and
`4b each of which includes a p-type lightly doped impurity
`region, a p-type heavily doped impurity region and a silicide
`layer such as a CoSi2 layer, a gate insulating film 5 formed on
`the active region 1b and made ofa silicon oxide film, a silicon
`oxynitride film or the like, a gate electrode 6b formed on the
`gate insulating film 5 and made of polysilicon, aluminum or
`the like, and a sidewall 7 covering a side surface of the gate
`electrode 6b and made ofan insulating film. Part ofthe active
`region 1b located under the gate electrode 6b is a channel
`region ly in which holes move (travel) when the leSFET is
`in an operation state.
`Moreover, provided are a first-type internal stress film 8a
`formed on the source/drain regions 3a and 4a of the nMIS-
`FET, made of a silicon nitride film or the like, and having a
`thickness ofabout 20nm, a second-type internal stress film 8b
`formed on the source/drain regions 3b and 4b of the pMIS-
`FET, made ofa TEOS film or the like, and having a thickness
`of about 20 run, an interlevel insulating film 9 covering the
`nMISFET and pMISFET and having a surface flattened, a
`lead electrode 10 formed on the interlevel insulating film 9,
`and a contact 11 connecting each ofthe source/drain regions
`3a, 3b, 4a and 4b with the lead electrode 10 through the
`interlevel insulating film 9.
`Herein, an “internal stress film” is a film characterized in
`that where the internal stress film is directly in contact with
`some other member or faces some other member with a thin
`
`10
`
`1.5
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`film interposed therebetween, a stress is generated in the film
`itself. As for stress, there are tensile stress and compressive
`stress. In this embodiment and other embodiments, an inter-
`nal stress film in which a tensile stress is generated substan-
`tially in the parallel direction to the direction in which carriers
`move (i.e., the gate length direction) in a channel region ofan
`MISFET is referred to as a “first-type internal stress film” and
`an internal stress film in which a compressive stress is gen-
`erated substantially in the