UNITED STATES PATENT AND TRADEMARK OFFICE
`
`________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`________________________________
`
`NVIDIA CORPORATION,
`Petitioner
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`Patent Owner
`
`________________________________
`
`Case No. IPR2017-00382
`Patent No. 7,124,325
`
`________________________________
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`TO PETITION FOR INTER PARTES REVIEW
`
`1
`
`NVIDIA 1007
`
`

`

`TABLE OF CONTENTS
`
`TABLE OF AUTHORITIES ....................................................................................iv
`I.
`INTRODUCTION ...........................................................................................1
`II.
`BACKGROUND .............................................................................................2
`A.
`Integrated Circuit Memory Technology................................................2
`B.
`The ’325 Patent .....................................................................................5
`C.
`References Cited in the Petition............................................................8
`1.
`Tanaka.........................................................................................8
`2.
`Ikehashi .....................................................................................10
`3.
`Garrett, Hassoun, and Ishikawa ................................................10
`III. CLAIM INTERPRETATION .......................................................................11
`A.
`“Interface Device”...............................................................................11
`1.
`Claim language .........................................................................14
`2.
`’325 Patent specification...........................................................15
`3.
`Technical dictionaries ...............................................................17
`4.
`References cited in the petition.................................................18
`5.
`Conclusion ................................................................................18
`“Trimming” .........................................................................................20
`“DRAM” .............................................................................................20
`“DDRII” ..............................................................................................20
`“Settable Control Element”.................................................................21
`
`B.
`C.
`D.
`E.
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`IV.
`
`V.
`
`B.
`
`C.
`D.
`
`E.
`
`F.
`
`TRIAL SHOULD NOT BE INSTITUTED ON CHALLENGE 1. ..............23
`A.
`Challenge 1 Has No Likelihood of Prevailing With Respect to
`All Claims Because Tanaka and Ikehashi Fail to Disclose
`Trimming of “Interface Devices.”.......................................................24
`1.
`Tanaka fails to disclose trimming of an “interface
`device.”......................................................................................24
`Ikehashi fails to disclose trimming of an “interface
`device.”......................................................................................28
`Challenge 1 Has No Likelihood of Prevailing with Respect to
`All Claims Because Tanaka and Ikehashi Fail to Disclose a
`“Settable Control Element.”................................................................30
`Challenge 1 is Fatally Flawed as an Obviousness Challenge.............31
`Challenge 1 Has No Likelihood of Prevailing with Respect to
`Claim 11. .............................................................................................37
`Challenge 1 Has No Likelihood of Prevailing with Respect to
`Claim 12. .............................................................................................39
`Challenge 1 Has No Likelihood of Prevailing with Respect to
`Claim 13. .............................................................................................40
`TRIAL SHOULD NOT BE INSTITUTED FOR CHALLENGE 2. ............40
`A.
`Challenge 2 Has No Likelihood of Prevailing with Respect to
`Claims 1 and 8-13................................................................................41
`1.
`Garrett does not disclose a test apparatus. ................................41
`2.
`The proposed combination of Garrett and Hassoun .................44
`a.
`The proposed combination of Garrett and Hassoun
`would not have been obvious to one skilled in the
`art. ...................................................................................45
`The proposed combination of Garrett and Hassoun
`would not have resulted in claim 1.................................50
`
`2.
`
`b.
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`B.
`
`C.
`
`Challenge 2 is Fatally Flawed as an Obviousness Challenge
`with Respect to at Least Claims 14, 16, and 17. .................................54
`Challenge 2 Has No Likelihood of Prevailing with Respect to
`Claims 14, 16, and 17..........................................................................54
`TRIAL SHOULD NOT BE INSTITUTED FOR CHALLENGE 3. ............57
`A.
`Challenge 3 Has No Likelihood of Prevailing with Respect to
`Claim 4. ...............................................................................................57
`Challenge 3 Has No Likelihood of Prevailing with Respect to
`Claims 2–7, 15, and 18–20..................................................................58
`VII. CHALLENGES 2 AND 3 ARE REDUNDANT WITH
`CHALLENGE 1. ...........................................................................................59
`VIII. CONCLUSION..............................................................................................62
`
`VI.
`
`B.
`
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`TABLE OF AUTHORITIES
`
`Cases
`Carl Zeiss GmbH. v. Nikon Corp.,
`IPR2013-00363, Paper 17 (PTAB Jan. 30, 2014) .........................................60
`
`CR Bard, Inc. v. Medline Indus., Inc.,
`IPR 2015-00511, Paper 9 (PTAB Jul. 15, 2015).....................................25, 38
`Dell, Inc. v. Elecs. & Telecommn’cs Research Inst.,
`IPR2014-00152, Paper 12 (PTAB May 16, 2014) ......................26, 29, 38, 44
`Edwards Lifesciences LLC v. Cook Inc.,
`582 F.3d 1322 (Fed. Cir. 2009) ...............................................................19, 22
`In re Fine,
`837 F.3d 1071 (Fed. Cir. 1988) .....................................................................57
`Gemalto S.A. v. HTC Corp.,
`754 F.3d 1364 (Fed. Cir. 2014) ...............................................................19, 23
`GPNE Corp. v. Apple Inc.,
`No. 2015-1825 (Fed. Cir. Aug. 1, 2016) .......................................................20
`Harmonic Inc. v. Avid Tech., Inc.,
`815 F.3d 1356 (Fed. Cir. 2016) .....................................................................61
`Honeywell Int’l, Inc. v. ITT Indus., Inc.,
`452 F.3d 1312 (Fed. Cir. 2007) ...............................................................19, 22
`Intelligent Bio-Systems, Inc. v. Illumina Cambridge Ltd.,
`821 F.3d 1359 (Fed. Cir. 2016) .....................................................................34
`Lam Research Corp. v. Flamm,
`IPR2016-00466, Paper 7 (PTAB July 19, 2016).........................26, 29, 38, 44
`Liberty Mut. Ins. Co. v. Progressive Cas. Ins. Co.,
`CBM2012-00003, Paper 7 (PTAB Oct. 25, 2012)............................60, 61, 62
`Monsanto Co. v. Pioneer Hi-Bred Int’l, Inc.,
`IPR2013-00023, Paper 32 (PTAB Apr. 11, 2013) ......................25, 29, 38, 44
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`Multiform Desiccants, Inc. v. Medzam, Ltd.,
`133 F.3d 1473 (Fed. Cir. 1998) .....................................................................19
`Oakley, Inc. v. Sunglass Hut Int’l,
`316 F.3d 1331 (Fed. Cir. 2003) ...................................................25, 29, 37, 44
`On Demand Machine Corp. v. Ingram Indus., Inc.,
`422 F.3d 1331 (Fed. Cir. 2006) ...............................................................19, 23
`Shopkick, Inc. v. Novitaz, Inc.,
`IPR2015-00279, Paper 7 (PTAB May 29, 2015) ..........................................36
`Synopsys, Inc. v. Mentor Graphics Corp.,
`IPR2012-00041, Paper 16 (PTAB Feb. 22, 2013) ........................................33
`
`Statutes
`35 U.S.C. § 102(b) ...................................................................................................59
`35 U.S.C. § 102(e) ...................................................................................................59
`35 U.S.C. § 103................................................................................................. 31, 32
`35 U.S.C. § 312(a)(3)........................................................................................ 34, 58
`35 U.S.C. § 313..........................................................................................................1
`35 U.S.C. § 314(a) ............................................................................................ 30, 61
`35 U.S.C. § 316(b) ...................................................................................................62
`
`Rules
`37 C.F.R. § 42.1(b) ..................................................................................................60
`37 C.F.R. § 42.107 .....................................................................................................1
`37 C.F.R. § 42.108 ...................................................................................................61
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`Other Authorities
`MCGRAW-HILL ILLUSTRATED TELECOM DICTIONARY (4th ed. 2001) .....................17
`MPEP § 2143.03 ......................................................................................................57
`MPEP § 706.02(j) ....................................................................................... 32, 33, 35
`PENGUIN DICTIONARY OF ELECS. 3d ed. 2001) ........................................................17
`WEBSTER’S NEW WORLD COMPUTER DICTIONARY (9th ed. 2001)..........................17
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`I.
`
`INTRODUCTION
`
`Pursuant to 35 U.S.C. § 313 and 37 C.F.R. § 42.107, the Patent Owner
`
`hereby provides a Preliminary Response to the Petition for Inter Partes Review
`
`filed December 7, 2016 (Paper 2, herein “petition” or “Pet.”). A Notice dated
`
`January 4, 2017 (Paper 3) set April 4, 2017 as the deadline for this Preliminary
`
`Response. This Preliminary Response is timely filed, and no fee is due with this
`
`Preliminary Response. If, however, the Office believes that any additional fee is
`
`due, it is authorized to charge deposit account No. 50-5836.
`
`The petition asserts three challenges to the claims of U.S. Patent No.
`
`7,124,325 (the ’325 Patent). For at least the reasons provided herein, the Patent
`
`Owner respectfully requests that the Board deny the petition and not institute trial.
`
`Challenge 1 presents an obviousness challenge based on Tanaka (Ex. 1003)
`
`and Ikehashi (Ex. 1004). In reality, Challenge 1 is two anticipation challenges
`
`improperly paired together and presented as a single obviousness challenge.
`
`Regardless, Challenge 1 is fundamentally flawed in that neither Tanaka nor
`
`Ikehashi teaches or suggests trimming any component of an “interface device,”
`
`under any reasonable interpretation of that term. Instead, both Tanaka and
`
`Ikehashi trim parameters of a signal used deep within a memory device to affect
`
`(e.g., write or erase) flash memory cells. Moreover, neither Tanaka nor Ikehashi
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`trim a “settable control element,” as that phrase should be interpreted in the ’325
`
`Patent.
`
`Challenges 2 and 3 are obviousness challenges based on Garrett (Ex. 1005)
`
`and Hassoun (Ex. 1006) (Challenge 2) or Garrett, Hassoun, and Ishikawa (Ex.
`
`1007) (Challenge 3). Those so-called obviousness challenges are improper, like
`
`Challenge 1, with respect to many of the claims, as the petition fails to specify how
`
`a combination of the references would resemble the claims more than any
`
`individual reference. More importantly, the base Challenge 2 has at least two
`
`deficiencies, as the petition has failed to show beyond conclusory allegations that
`
`Garrett or Hassoun teach or suggest (1) the “current source” recited in claim 1 or
`
`(3) the “settable control element” recited in claims 1 and 14.
`
`II.
`
`BACKGROUND
`
`A.
`
`Integrated Circuit Memory Technology
`
`Two common types of memory are DRAM (dynamic random-access
`
`memory) and flash memory. They are different types of memory, with differently
`
`constructed memory cells, radically different peripheral and support circuitry and
`
`therefore different characteristics. Flash memory is cheaper but considerably
`
`slower than DRAM. Flash is also non-volatile, whereas DRAM is volatile. Thus,
`
`DRAM is used as a computer’s main (RAM) memory, whereas flash is generally
`
`used for long-term storage, typically as an alternative to a disk (e.g., the ubiquitous
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`thumb (or USB) drive is made of flash memory).
`
`Note that the names are
`
`somewhat misnomers. Both DRAM and flash are random-access memories, and
`
`flash is not fast; quite to the contrary, it is at least an order of magnitude slower
`
`than DRAM.
`
`Memory is provided in the form of integrated circuits, sometimes
`
`colloquially referred to in the art as “ICs” or “chips.” An integrated circuit is a
`
`packaged electronic component with solder bumps, pins or leads that can connect
`
`to other components, typically on a printed circuit board. One of the challenges
`
`posed by integrated circuits is that their electrical characteristics can vary from
`
`chip to chip and over time, due to such things as process variations in the
`
`fabrication process, external environment, or aging. Thus, real-world ICs are not
`
`all ideal and not all instances of the same type of chip are identical in their
`
`electrical characteristics. To compensate for those variations, some ICs are
`
`designed to have some adjustability in critical circuit elements. “Trimming” is
`
`adjusting those adjustable values so that the memory operates as defined by its
`
`specification across a range of process and environmental conditions. Different
`
`types of memories, because of their different constructions and methods of
`
`operation, include trimming in different parts of their designs.
`
`The variations in the electrical characteristics for IC interface connections,
`
`over which high-speed electrical information signals are sent or received, is
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`especially important for some ICs. For example, if the impedance of IC’s output
`
`driver does not match the impedance of the signal traces connected to the that
`
`output driver, then the signal integrity – the quality of the electrical waveform
`
`transmitting information – is diminished. A consequence of reduced signal
`
`integrity is that the maximum rate at which the output driver can transmit that
`
`information off the chip through the interface is also reduced. Similarly, if there is
`
`an impedance mismatch between a terminating resistor at an IC’s interface
`
`connection and the impedance of the signal traces connected to that interface
`
`connection, reflections will reduce the signal integrity and ultimately limit the
`
`frequency (i.e., rate or bandwidth) at which information can be communicated
`
`through the interface into the integrated circuit. Thus, the design of IC interface
`
`devices must take into consideration I/O (input/output) and signal integrity in
`
`general and impedance matching in particular to facilitate highest possible
`
`frequency of operation.
`
`This is certainly true for interface connections in memory ICs and the
`
`memory controller ICs connected to them. This is especially critical when high
`
`bandwidth operation is required. Signal integrity issues have been critical in
`
`DRAM memory system and IC design for many years now. Impedance
`
`mismatches on the interface devices of a DRAM memory IC or a DRAM memory
`
`controller IC limit the rate at which data access operations can occur.
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`B.
`
`The ’325 Patent
`
`The ’325 Patent concerns trimming of output drivers and terminations of an
`
`IC. Indeed, the title of the ’325 Patent is “METHOD AND APPRATUS FOR
`
`INTERNALLY TRIMMING OUTPUT DRIVERS AND TERMINATIONS IN
`
`SEMICONDUCTOR DEVICES.” The ’325 Patent extensively discusses the need
`
`to trim the “interface parameters” of those “interface devices” in ICs related to
`
`DRAM memory. For example, the ’325 Patent explains that properly trimmed
`
`interface parameters are necessary “to maintain the integrity of the data bus signals
`
`transmitted to the data bus” at high data bus transmission rates:
`
`As data transmission rates increase on the data bus,
`the semiconductor devices effecting access for the
`purpose of writing to the data bus or reading from the
`data bus demand narrower tolerances for the interface
`parameters in order to maintain the integrity of the data
`signals transmitted to the data bus.
`***
`For operation in data bus systems with a high data
`transmission rate, provision is therefore made for the
`semiconductor device’s
`interface parameters
`to be
`trimmed at least once before or during the initial startup
`of the semiconductor device or repeatedly during the
`operation of the semiconductor device.
`
`’325 Patent at 1:36-41, 2:6-11.
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`The ’325 Patent
`
`identifies the two particular interface devices whose
`
`relevant interface parameter needs to be trimmed. In both cases, the interface
`
`parameter being tuned is the impedance, or, alternatively, resistance. “The first
`
`such interface parameter is the impedance of the output drivers,” which are used to
`
`place data on the data bus at “higher . . . data transmission rates”:
`
`A first such interface parameter is the impedance
`of the output drivers (OCD-off chip driver), which a
`semiconductor device uses to effect a write access to the
`data bus, or to output data signals to the data bus. The
`impedance of an output driver influences the rise and fall
`times when there is a signal level change in the data
`signal driven by the output driver, and hence influences a
`signal delay in the data signal. A maximum skew in the
`signal delays of all of
`the output drivers
`in a
`semiconductor device or in all of the semiconductor
`devices in a data bus system limits a maximum data
`transmission rate. The smaller the maximum skew in this
`case, the higher the data transmission rates that can be
`implemented.
`
`Id. at 1:36-54 (emphases added).
`
`The other interface device that needs trimming is a termination device,
`
`which is at the receiving end of a data bus where high-speed data signals are
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`accepted from the bus through an interface connection into the integrated circuit.
`
`The ’325 Patent discusses termination devices as well:
`
`formed by
`is
`interface parameter
`Another
`terminations, which terminate the data bus locally in the
`semiconductor device in order to prevent reflections
`(ODT-on die termination). As the precision of the
`termination increases, interference signals arising at the
`location of the termination are attenuated to an increasing
`extent and a higher maximum data transmission rate is
`made possible in the data bus system.
`
`Id. at 1:55-62 (emphases added).
`
`The ’325 Patent illustrates both types of interface devices for an interface
`
`connection in the one and only disclosed embodiment of the invention, which is
`
`illustrated in Figure 3 (reproduced below). In this drawing and the others in the
`
`patent, “Two of the interface devices are output driver devices l0a, l0b. The two
`
`other interface devices are termination devices l0c, 10d.” Id. at 6:65-67 (referring
`
`to the same-labeled elements in Fig. 1); see also id. at 8:4-29 (same regarding
`
`invention illustrated in Fig. 3). These interface devices are colored red in the
`
`drawing below. The trimmed interface parameter of the output drivers 10a and
`
`10b is an output impedance. The trimmed interface parameter of the termination
`
`devices 10c and 10d is resistance. The ’325 Patent refers to both types of trimmed
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`devices as “control elements” or “settable control elements,” and they are colored
`
`orange in the drawing below.
`
`Id. at Fig. 3 (annotations and coloring added).
`
`C.
`
`References Cited in the Petition
`
`1.
`
`Tanaka
`
`Tanaka discloses an integrated circuit microcomputer 1 that includes a flash
`
`memory 5 on a microcomputer integrated circuit 1, as illustrated in Tanaka’s
`
`Figure 1:
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`Tanaka at Fig. 1 (coloring added). The relevant disclosure of Tanaka concerns
`
`trimming of characteristics of the signals used to perform operations (e.g., data
`
`writes or erases) in the flash memory 5 portion of the microcomputer 1. As is well
`
`known in the art, writing to or erasing from a flash memory cell requires a signal
`
`with a boosted voltage. See id. at 4:38-43. Specifically, Tanaka teaches a
`
`production testing technique to perform “voltage trimming” and “pulse width
`
`trimming.” Id. at 5:55, 6:24. Figures 25-29 of Tanaka illustrate trimming
`
`operations to adjust the voltage and pulse width of pulses to write and erase flash
`
`memory cells. See generally id. at 17:4 – 18:47.
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`2.
`
`Ikehashi
`
`Ikehashi, just like Tanaka, primarily concerns trimming of write voltage and
`
`pulse width for flash memory.
`
`See Ikehashi at 1:14-65 (referring to “flash
`
`memory” and “trimming” and stating “The present invention relates to a
`
`nonvolatile semiconductor memory that internally generates a reference voltage, a
`
`writing voltage, a erasure voltage, and a readout voltage.”)
`
`3.
`
`Garrett, Hassoun, and Ishikawa
`
`Garrett is directed at a controller with an adjustable output driver and how
`
`that controller makes adjustments to current sink parameters of master (i.e.,
`
`memory controller) and DRAM slave devices on its channel. Garrett utilizes a
`
`reference voltage to make those adjustments. Hassoun concerns production
`
`trimming/testing and discloses a variable current source 44 that has the specific
`
`purpose of setting the swing on a digitally changing data signal and toggling that
`
`digital data. Ishikawa is like Tanaka in that both are directed at an integrated
`
`circuit having non-volatile flash memory and a central processing unit. See
`
`Ishikawa at 1:1-14. Also like Tanaka (and Ikehashi), Ishikawa discloses trimming
`
`of internal voltage generators to affect operations on the cells of the flash memory.
`
`See id. at 17:25 – 18:12.
`
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`III. CLAIM INTERPRETATION
`
`A.
`
`“Interface Device”
`
`The petition offers no interpretation of the phrase “interface device.”1 See
`
`Pet. at 7. However, the petition suggests what the phrase means when it accurately
`
`characterizes the ’325 Patent’s “interface devices” as part of its “Overview of the
`
`’325 Patent”:
`
`The ’325 patent describes a method and device for
`trimming semiconductor interface devices. Ex. 1001
`[’325 Patent], Abstract. Interface devices, like output
`drivers and terminations (id., 3:18-21), have parameters
`
`1 The Board need not interpret the phrase “interface device” to decide that trial
`
`should not be instituted in this case. As explained in § IV-A infra at 25-30,
`
`Challenge 1 is fatally flawed because neither Tanaka nor Ikehashi discloses a
`
`settable control element in an “interface device.” That is true under any
`
`reasonable interpretation of the phrase that in any way acknowledges the plain
`
`and ordinary meaning of “interface.” Nonetheless, because the interpretation of
`
`the phrase is dispositive for Challenge 1, Polaris offers its interpretation here.
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`that affect reading and writing from a data bus (id., 1:36-
`41). “[T]he impedance of the output drivers . . .[,] which
`a semiconductor device uses to effect a write access to
`the data bus,” is an interface parameter that, if trimmed
`correctly, can allow for a higher data transmission rate.
`Id., 1:42-54.
`
`These interface devices are subject to variation due
`to the manufacturing process, temperature variation
`during operation, and other such variations over time.
`Id., 1:63-2:5. Accordingly, as recognized by the ’325
`patent, prior art methods of trimming existed to trim the
`interface devices “before or during the initial startup . . .
`or repeatedly during [] operation.” Id. 2:6-17. Indeed,
`the ’325 patent observes that interface devices have
`settable “control elements . . . in the form of switchable
`impedances whose respective value can be programmed”
`based on a value saved in a “trimming register.” Id.
`
`Pet. at 3 (underlining added). The petitioner’s expert, Dr. Tredennick echoes the
`
`same points, almost word-for-word:
`
`16. The ’325 patent discusses calibrating or
`“trimming” interface devices within a semiconductor.
`Ex. 1001 [’325 Patent], Abstract. The patent says these
`interface devices include output drivers and terminations.
`Id., 3:18-21. Output drivers and terminations have
`parameters that control reading and writing from a data
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`bus. Id., 1:36-41. As the speed of data transmission
`increases on a bus, for example in DRAM, the patent
`states
`that “narrower
`tolerances for
`the
`interface
`parameters” are required to “maintain the integrity of the
`data signals transmitted to the data bus.” Id. One such
`interface parameter is stated to be “the impedance of the
`output drivers . . . which a semiconductor device uses to
`effect a write access to the data bus.” Id., 1:42-54. If
`trimmed or calibrated correctly, it enables a higher data
`transmission rate. Id. In the case of terminations, “which
`terminate the data bus locally” and prevent reflections,
`greater precision allows for “a higher maximum data
`transmission rate is made possible.” Id., 1:55-62.
`
`17. The manufacturing process and temperature
`variations during operation cause variations in the
`interface devices. Id., 1:63-2:5. Before the ’325 patent,
`methods of trimming existed in the prior art to trim
`interface devices “before or during the initial startup . . .
`or repeatedly during [] operation.” Id. 2:6-17. The
`interface devices have settable “control elements . . . in
`the form of switchable impedances whose respective
`value can be programmed” using a value stored in a
`“trimming register.” Id.
`
`Tredennick Decl. (Ex. 1002) ¶¶ 16-17 (emphases added) (all ellipses and brackets
`
`in original).
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`This characterization of the ’325 Patent suggests the proper interpretation of
`
`the phrase “interface device” refers to as a part of a semiconductor device
`
`connected to data bus pin or comparable interface connection. In the ’325 Patent,
`
`impedance/resistance of the interface devices should be tuned to enable high-rate
`
`data transfers. This understanding can be confirmed by considering the claim
`
`language in context, the specification, technical dictionaries that reflect the
`
`understanding in the art, and the references cited in the petition.
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`1.
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`Claim language
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`The ’325 Patent claims refer extensively to “interface devices.” For
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`example, claim 1 refers to “a semiconductor device having a plurality of interface
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`devices.” ’325 Patent 9:1-2. Claim 14, the other independent claim, is drawn to
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`“[a] semiconductor device comprising: at least one interface device . . . .” Id.
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`10:26-27. It is clear from this language that the “interface device” is associated
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`with an interface between the semiconductor device and something external to the
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`semiconductor device. That is, the “interface device” concerns a conceptual or
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`physical edge or boundary of the semiconductor device, and specifically with
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`respect to “interface connections.”
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`It is also clear that the relevant interface is a data interface, that is an
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`electrical interface through which information or data signals are sent to and/or
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`from the semiconductor device. Indeed, claim 1 recites that the “interface device”
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`is connected to an “interface connection”: “connecting the current source in the
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`test apparatus to an interface connection on the semiconductor device, the interface
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`connection being connected to one of the plurality of interface devices.” Id. 9:5-8
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`(emphasis added).
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`2.
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`’325 Patent specification
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`Figures 1-3 clearly and prominently illustrate the external boundary of the
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`semiconductor device 1 using a dashed vertical line, an “interface connection” 32
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`at this physical or conceptual boundary, and “interface devices” 10a-10d to send
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`and to receive signals of interest, such as data retrieved from or stored in memory,
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`as shown in the following color-annotated version of Figure 3:
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`’325 Patent, Fig. 3 (color annotations added). Everything left of the dashed
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`vertical line (yellow above) is part of the semiconductor device 1. Everything right
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`of that line is external to the semiconductor device 1. Note also that the “interface
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`connections” 32 are distinct from “supply connections” 31 and 33, which simply
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`provide power and ground and from the connections between the test control unit
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`24 and the semiconductor device 1.
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`The ’325 Patent provides two and only two examples of “interface devices”:
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`output drivers and terminations. See, e.g., id., Abstract, 1:42-62, 3:18-21, 5:24-27,
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`6:27-34, 6:66–7:12.
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`In fact, the title of the ’325 Patent clearly states which
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`interface devices are
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`trimmed:
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` “METHOD AND APPARATUS FOR
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`INTERNALLY TRIMMING OUTPUT DRIVERS AND TERMINATIONS IN
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`SEMICONDUCTOR DEVICES.” The former is for sending data out from the
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`semiconductor device. The latter is essential for receipt of high frequency data. In
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`fact, the specification discusses the need to trim “interface devices” in memory
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`devices, particularly DRAM-related devices, so that high data rates can be
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`obtained. See id. at 1:36-62 (quoted in § II-B infra at 5-6).
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`Figures 1-3 show three types of connections at the boundary between the
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`semiconductor device 1 and the outside world: (1) “supply connections” 31 and 33
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`for power and ground; (2) “interface connections” 32 for data-bearing signals and
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`(3) connections for test signals 34, 35 and 51 between the semiconductor device 1
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`and the test control unit 24. The “interface devices” are connected between the
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`interface connection and a supply connection and provide an interface parameter
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`that maintains the integrity of the data signals transmitted across the interface
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`connection. See id. at 1:36-62 (quoted in § II-B infra at 5-6).
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`3.
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`Technical dictionaries
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`Appropriate definitions of the term “interface” from technical dictionaries
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`comport with the notion expressed in the claim language and reflected in the
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`specification that the relevant “interface” is between the semiconductor device, on
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`one hand, and another device external to the semiconductor device, on the other
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`hand. See, e.g., PENGUIN DICTIONARY OF ELECS. at 288 (3d ed. 2001) (Ex. 2001)
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`(“Interface The electronic circuitry used to connect two or more devices, usually
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`required to compensate for differences in speed, signal levels, and or codes
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`between the connecting devices. The devices are generally computer components
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`or systems.”); WEBSTER’S NEW WORLD COMPUTER DICTIONARY at 196 (9th ed.
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`2001) (Ex. 2002) (interface 1. The connection between two hardware devices,
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`between two applications, or between different sections of a computer network);
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`MCGRAW-HILL ILLUSTRATED TELECOM DICTIONARY at 315 (4th ed. 2001) (Ex.
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`2003) (“Interface A device or software program that connects two separate
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`entities. The two entities can be virtual (software), hardware/electronic