IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In the Inter Partes Review of:
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`
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`U.S. Patent No. 5,870,087
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`Trial Number: To Be Assigned
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`Panel: To Be Assigned
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`Filed: November 13, 1996
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`Issued: February 9, 1999
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`Inventor(s): Kwok Kit Chau
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`Assignee: Avago Technologies General IP
`(Singapore) Pte. Ltd.
`
`Title: MPEG Decoder System And Method
`Having A Unified Memory For Transport
`Decode And System Controller Functions
`
`Mail Stop Inter Partes Review
`Commission for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`
`
`PETITION FOR INTER PARTES REVIEW UNDER 37 C.F.R. § 42.100
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`

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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`
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`TABLE OF CONTENTS
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`MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(A)(1) ........................ 1  
`
`I.  
`
`A.   Real Party-In-Interest Under 37 C.F.R. § 42.8(b)(1) ...................................... 1  
`
`B.   Related Matters Under 37 C.F.R. § 42.8(b)(2) ................................................ 1  
`
`C.   Lead and Back-Up Counsel and Service Information Under 37 C.F.R.
`§ 42.8(b)(3) and (4) ......................................................................................... 1  
`
`II.  
`
`III.  
`
`GROUNDS FOR STANDING ....................................................................... 2  
`
`IDENTIFICATION OF CHALLENGE STATEMENT ................................ 2  
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`A.   Claims and Statutory Grounds ........................................................................ 2  
`
`B.   Claim Construction ......................................................................................... 4  
`
`C.   How the Claims are Unpatentable ................................................................... 5  
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`D.   Evidence Supporting Challenge ...................................................................... 6  
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`IV.   BACKGROUND ............................................................................................ 6  
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`A.   ‘087 Patent Overview ...................................................................................... 6  
`
`B.   Prior Art Overview .......................................................................................... 8  
`
`1.   Fujii ............................................................................................................. 8  
`
`2.   Maturi ........................................................................................................ 10  
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`3.   Bheda ......................................................................................................... 11  
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`4.   Lam ........................................................................................................... 12  
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`5.   Yao ............................................................................................................ 13  
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`C.   Level of Ordinary Skill in the Art ................................................................. 13  
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`D.   Applicable Legal Standards .......................................................................... 14  
`
`V.   HOW THE CHALLENGED CLAIMS ARE UNPATENTABLE .............. 14  
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`A.   Ground 1: Fujii Anticipates Claims 1, 7, and 16. .......................................... 14  
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`1.  
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`Independent Claims 1 and 16 .................................................................... 14  
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`2.   Dependent Claim 7 .................................................................................... 36  
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`B.   Ground 2: Fujii and Bheda Render Obvious Claims 2-3 and 17. ................. 38  
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`1.   Dependent Claims 2 and 17 ...................................................................... 39  
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`2.   Dependent Claim 3 .................................................................................... 45  
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`C.   Ground 3: Fujii and Lam Render Obvious Claim 5. ..................................... 47  
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`D.   Ground 4: Maturi and Yao Render Obvious Claims 1, 7, and 16. ................ 51  
`
`1.  
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`Independent Claims 1 and 16 .................................................................... 52  
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`2.   Dependent Claim 7 .................................................................................... 70  
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`E.   Ground 5: Maturi, Yao, and Bheda Render Obvious Claims 2-3 and 17. .... 72  
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`1.   Dependent Claims 2 and 17 ...................................................................... 74  
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`2.   Dependent Claim 3 .................................................................................... 76  
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`F.   Ground 6: Maturi, Yao, and Lam Render Obvious Claim 5. ........................ 77  
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`VI.   CONCLUSION ............................................................................................ 80  
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`
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`TABLE OF AUTHORITIES
`
`Cases  
`
`In re CSB-System Int’l, Inc.,
`832 F.3d 1335 (Fed. Cir. 2016) ............................................................................. 4
`
`Intirtool Ltd. v. Texar Corp.,
`369 F.3d 1289 (Fed. Cir. 2004) ..................................................................... 14, 52
`
`Karsten Mfg. Corp. v. Cleveland Golf Co.,
`242 F.3d 1376 (Fed. Cir. 2001) ........................................................................... 14
`
`Leggett & Platt, Inc. v. VUTEk, Inc.,
`537 F.3d 1349 (Fed. Cir. 2008) ........................................................................... 25
`
`Phillips vs. AWH Corporation,
`415 F.3d 1303 (Fed. Cir. 2005) ............................................................................. 4
`
`SIBIA Neurosciences, Inc. v. Cadus Pharm. Corp.,
`225 F.3d 1349 (Fed. Cir. 2000) ........................................................................... 14
`
`ZTE Corp. v. ContentGuard Holdings Inc.,
`IPR 2013-00134, Paper 12 (P.T.A.B. June 19, 2013) ......................................... 14
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`EXHIBITS
`
`Exhibit No.
`
`Description
`
`1001
`
`U.S. Patent No. 5,870,087 to Chau (“the ‘087 Patent”)
`
`1002
`
`1003
`
`1004
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`1005
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`1006
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`1007
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`1008
`
`1009
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`1010
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`1011
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`1012
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`1013
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`1014
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`Prosecution History of the ‘087 Patent
`
`Declaration of Dr. Claudio Silva (“Dec.”)
`
`Curriculum Vitae of Dr. Claudio Silva
`
`U.S. Patent No. 5,898,695 to Fuji et al. (“Fujii”)
`
`U.S. Patent No. 5,559,999 to Maturi et al. (“Maturi”)
`
`U.S. Patent No. 6,002,441 to Bheda et al. (“Bheda”)
`
`U.S. Patent No. 5,960,464 to Lam (“Lam”)
`
`Y. Yao, “Unified Memory Architecture Cuts PC Cost,”
`Microprocessor Report, vol. 9, n. 8 (June 19, 1995) (“Yao”)
`
`“VESA Announces Release of Unified Memory Architecture
`Standard,” Business Wire (Mar. 8, 1996) (“Business Wire”)
`
`Transmission of Non-Telephone Signals, Information Technology
`– Generic Coding of Moving Pictures and Associated Audio
`Information: Video, ITU-T Recommendation H.262, July 1995
`(“H.262 Standard”)
`
`R. Ng, “Fast Computer Memories,” IEEE Spectrum, vol. 29, n. 10
`(Oct. 1992) (“Ng”)
`
`Claim Construction Order (D.I. 150) in Broadcom Corp. v. Sony
`Corp., 8:16-cv-01052 (C.D. Cal.)
`
`Dismissal Order (D.I. 153) in Broadcom Corp. v. Sony Corp.,
`8:16-cv-01052 (C.D. Cal.)
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`
`
`Petitioners request inter partes review (“IPR”) of Claims 1-3, 5, 7, and 16-17
`
`of U.S. Patent No. 5,870,087 (“the ‘087 Patent”), attached hereto as Exhibit 1001.
`
`I.   MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(a)(1)
`A.   Real Party-In-Interest Under 37 C.F.R. § 42.8(b)(1)
`Amazon.com, Inc. and Amazon Web Services, Inc. (collectively “Amazon”)
`
`identify the following real parties-in-interest in addition to Amazon.com, Inc. and
`
`Amazon Web Services, Inc.: Amazon Digital Services LLC, AWSHC, Inc., and
`
`Amazon Fulfillment Services, Inc.
`
`B.   Related Matters Under 37 C.F.R. § 42.8(b)(2)
`Broadcom Corp. and Avago Technologies General IP (Singapore) Pte. Ltd.
`
`(collectively “Broadcom”) asserted the ‘087 Patent in Broadcom Corp. et al. v.
`
`Amazon.com, Inc. et al., Case No. 8:16-cv-01774-JVS-JCG (C.D. Cal.). That case
`
`remains pending and may affect, or be affected by, decisions in this proceeding.
`
`C.   Lead and Back-Up Counsel and Service Information Under 37
`C.F.R. § 42.8(b)(3) and (4)
`
`Amazon provides the following designations of counsel:
`
`Lead Counsel
`Joseph F. Edell (Reg. No. 67,625)
`Joe.Edell.IPR@fischllp.com
`Fisch Sigler LLP
`5301 Wisconsin Avenue NW
`Fourth Floor
`Washington, DC 20015
`Phone: (202) 362-3524
`Fax: (202) 362-3501
`
`Back-up Counsel
`David M. Saunders
`David.Saunders.IPR@fischllp.com
`Fisch Sigler LLP
`96 North Third Street
`Suite 260
`San Jose, CA 95112
`Phone: (650) 362-8208
`Fax: (202) 362-3501
`
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`

`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`
`
` Power of Attorney accompanies this Petition pursuant to 37 C.F.R. §
`
` A
`
`42.10(b). Amazon consents to electronic service by email at
`
`Joe.Edell.IPR@fischllp.com.
`
`II.   GROUNDS FOR STANDING
`Amazon certifies that the ‘087 Patent is available for IPR, and Amazon is
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`not barred or estopped from requesting IPR on the asserted grounds.
`
`III.  
`
`IDENTIFICATION OF CHALLENGE STATEMENT
`A.   Claims and Statutory Grounds
`Amazon requests inter partes review of claims 1-3, 5, 7, and 16-17
`
`(“Challenged Claims”). Amazon requests that the Board find the Challenged
`
`Claims unpatentable.
`
`IPR of the Challenged Claims is requested in view of the following:
`
`•   U.S. Patent No. 5,898,695 (“Fujii”) was filed on March 27, 1996 and
`issued on April 27, 1999, and claims priority to two Japanese patent
`applications which were both filed on March 29, 1995; Fujii is prior art
`under § 102(a), (e);
`•   U.S. Patent No. 5,559,999 (“Maturi”) was filed on September 9, 1994
`and issued on September 24, 1996, and is prior art under § 102(a), (e);
`•   U.S. Patent No. 6,002,441 (“Bheda”) was filed on October 28, 1996 and
`issued on December 14, 1999, and is prior art under § 102(a), (e);
`•   U.S. Patent No. 5,960,464 (“Lam”) was filed on August 23, 1996 and
`issued on September 28, 1999, and is prior art under § 102(a), (e); and
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`
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`•   “Unified Memory Architecture Cuts PC Cost” article (“Yao”) was
`published on June 19, 1995 in Volume 9, Issue No. 8 of Microprocessor
`Report, and is prior art under § 102(a), (b).
`
`Amazon requests IPR on the following grounds:
`
`Ground
`1
`2
`
`3
`4
`
`5
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`6
`
`Proposed Statutory Rejections for the ‘087 Patent
`Claims 1, 7, and 16 are anticipated by Fujii under § 102(a), (e).
`Claims 2-3 and 17 are rendered obvious by Fujii and Bheda
`under § 103(a).
`Claim 5 is rendered obvious by Fujii and Lam under § 103(a).
`Claims 1, 7, and 16 are rendered obvious by Maturi and Yao
`under § 103(a).
`Claims 2-3 and 17 are rendered obvious by Maturi, Yao, and
`Bheda under § 103(a).
`Claim 5 is rendered obvious by Maturi, Yao, and Lam under §
`103(a).
`
`
`
`Proposed Grounds 1-6 are not redundant. Ground 1, unlike Grounds 2-6, is
`
`based on § 102. Moreover, Grounds 2-6 focus on different prior art combinations
`
`and approaches to arrive at the Challenged Claims. For instance, Grounds 1-3
`
`focus on Fujii’s teachings, which are directed towards using the system controller’s
`
`memory for demultiplexing and decoding.1 On the other hand, Grounds 4-6 focus
`
`
`1 E.g., Fujii, 3:60-64; Dec., ¶¶28-29.
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`on Maturi’s teachings, which are directed towards a method of synchronizing
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`video and audio decoding using a single memory.2
`
`B.   Claim Construction
`The ‘087 Patent has expired.3 Accordingly, the “plain meaning” standard of
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`Phillips vs. AWH Corporation, 415 F.3d 1303, 1312-13 (Fed. Cir. 2005) applies to
`
`the ‘087 claims.4 For purposes of the IPR, the term “memory” as used in claims 1-
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`3, 5, 7, and 16-17 should mean “single unified memory.”
`
`This meaning is consistent with the ‘087 Patent. Throughout the
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`specification, the memory is referred to as “single unified memory”:
`
`•   “The present invention relates…particularly to an MPEG decoder
`system which includes a single unified memory for MPEG transport,
`decode and system controller functions.”
`•   “The video decoding system of the present invention includes a single
`unified memory which stores code and data for the transport logic,
`system controller and MPEG decoder functions. The single unified
`memory is preferably a 16 Mbit memory.”
`
`
`2 E.g., Maturi, 2:47-48, 4:55-67; Dec., ¶¶31-32.
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`3 See, e.g., IPR2017-00520, Patent Owner Preliminary Response, Paper 7 at 3
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`(P.T.A.B. Apr. 20, 2017) (admitting ‘087 Patent expired on or about November 13,
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`2016).
`
`4 In re CSB-System Int’l, Inc., 832 F.3d 1335, 1340-1341 (Fed. Cir. 2016).
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`•   “The MPEG decoder logic preferably includes a memory controller
`which couples to the single unified memory.”
`•   “The present invention comprises a video decoder system and method
`which includes a single unified memory for MPEG transport, decode,
`and system controller functions.”5
`
`This meaning, moreover, is consistent with how a person of ordinary skill in the art
`
`(“POSITA”) would have understood the plain meaning of “memory,” consistent
`
`with the specification.6 In the matter Broadcom Corp. v. Sony Corp., the district
`
`court construed “memory” in the claims of the ‘087 Patent to mean “single unified
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`memory” using the Phillips standard.7
`
`C.   How the Claims are Unpatentable
`How Claims 1-3, 5, 7, and 16-17 are unpatentable, including the
`
`identification of evidence, is provided in Section V.
`
`
`5 ‘087 Patent, 1:30-34, 5:3-5:7, 5:24-26, 17:2-4; see also id., 5:7-10, 6:22-27, 7:48-
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`7:51; 11:15-30.
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`6 Dec., ¶¶53-54.
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`7 Ex. 1013 (Broadcom Corp. v. Sony Corp., 8:16-cv-01052 (C.D. Cal.), Claim
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`Construction Order at 3-8 (D.I. 150)); Ex. 1014 (dismissing Broadcom Corp. v.
`
`Sony Corp. matter with prejudice based on joint motion to dismiss).
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`D.   Evidence Supporting Challenge
`An Appendix of Exhibits is attached. The relevance of the evidence may be
`
`found in Section V. Amazon also submits a declaration of Dr. Claudio Silva
`
`(“Dec.”) in support of this Petition.
`
`IV.   BACKGROUND
`A.  
`‘087 Patent Overview
`The ‘087 Patent generally relates to a single unified memory for decoding,
`
`or decompressing, video and audio data.8 The patent acknowledges that decoders
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`for the Moving Pictures Experts Group (“MPEG”)-1 and MPEG-2 standards were
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`known in the art.9 Such decoders “typical[ly]” included on-chip and external
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`memory,10 “transport logic which operates to demultiplex received data into a
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`plurality of individual multimedia streams”,11 and “a system controller which
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`controls operations in the system and executes programs or applets.”12 The patent
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`asserts that such “[p]rior art MPEG video decoder systems have generally” used
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`8 ‘087 Patent, 1:30-34.
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`9 Id., 4:14-28; see also id., 2:31-32 (“The two predominant MPEG standards are
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`referred to as MPEG-1 and MPEG-2.”).
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`10 Id., 4:14-17.
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`11 Id., 4:22-24.
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`12 Id., 4:25-27.
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`“separate memory” for the decoder, on the one hand, and the transport logic and
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`system controller, on the other.13 The patent contends that it was “generally not []
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`possible to combine these memories, due to size limitations” and cost.14
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`The patent purports to address this issue by use of a “unified memory for
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`multiple functions” including “for the transport logic, system controller, and
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`MPEG decoder functions.”15 The claims, however, do not provide a way of
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`overcoming the memory size and cost limitations that, in the specification’s words,
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`made it impractical or impossible to combine the separate memories.
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`Representative independent claim 1 recites:
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`1. An MPEG decoder system which includes a single memory for use by
`transport, decode and system controller functions, comprising:
`a channel receiver for receiving and16 MPEG encoded stream;
`transport logic coupled to the channel receiver which demultiplexes
`one or more multimedia data streams from the encoded stream;
`a system controller coupled to the transport logic which controls
`operations within the MPEG decoder system;
`
`
`13 Id., 4:28-35.
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`14 Id., 4:35-43.
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`15 Id., 4:67-5:6.
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`16 It appears element 1.1’s “and” should be “an.”
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`an MPEG decoder coupled to receive one or more multimedia data
`streams output from the transport logic, wherein the MPEG decoder operates
`to perform MPEG decoding on the multimedia data streams; and
`a memory coupled to the MPEG decoder, wherein the memory is
`used by the MPEG decoder during MPEG decoding operations, wherein the
`memory stores code and data useable by the system controller which enables
`the system controller to perform control functions within the MPEG decoder
`system, wherein the memory is used by the transport logic for
`demultiplexing operations;
`wherein the MPEG decoder is operable to access the memory during
`MPEG decoding operations;
`wherein the transport logic is operable to access the memory to store
`and retrieve data during demultiplexing operations; and
`wherein the system controller is operable to access the memory to
`retrieve code and data during system control functions.
`
`B.  
`
`Prior Art Overview
`
`Fujii
`
`1.  
`Fujii discloses an MPEG decoder system that decodes multiplexed
`
`multimedia data by consolidating memory components into a single RAM
`
`memory.17 For example, Fujii “provide[s] a decoder for compressed and
`
`
`17 Fujii, 11:1-5 (“[T]he packet landing buffer is provided in RAM used by the
`
`microprocessor for the system control. Therefore, data can be supplied to the
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`decoders without increasing the number of components and the cost thereof.”).
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`multiplexed video and audio data, wherein packet landing buffers are allocated in a
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`RAM used by a CPU for the system control to thereby reduce the number of
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`components and lower the cost of components.”18 Annotated Figure 11 of Fujii
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`shows the transport logic (blue), system controller (green), decoder (orange), and
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`single memory (red):19
`
`
`In IPR2016-00646 the Board instituted IPR of claims 1, 7, 10-11, and 16 of
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`
`
`the ‘087 Patent based on Fujii.20 That IPR was terminated on May 16, 2017 prior to
`
`
`18 Id., 3:60-64.
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`19 Id., Fig. 11 (annotated).
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`20 IPR2016-00646, Institution Decision, Paper 11 at 21 (P.T.A.B. Aug. 22, 2016).
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`
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`the issuance of a final written decision due to a settlement agreement being reached
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`between the Patent Owner and petitioners Asustek Computer, Inc. and Asus
`
`Computer International.21
`
`2.   Maturi
`Maturi22 discloses “a decoding system for a [MPEG] multiplexed
`
`audio/video bitstream” that includes a “host microcontroller” and a “decoder.”23
`
`Maturi details that “decoder 16 and the microcontroller 18 have access” to the
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`same “Dynamic Random Access Memory (DRAM) 20.”24 Annotated Figure 3 of
`
`Maturi depicts the claimed transport logic (blue), system controller (green),
`
`decoder (orange), and single memory (red):25
`
`
`21 IPR2016-00646, Termination Order, Paper 26 at 2 (P.T.A.B. May 16, 2017).
`
`22 The Maturi reference lists inventors G. Maturi, D. Auld, and D. Neuman, while
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`the ‘087 Patent lists inventor K. Chau. Therefore, Maturi is “by another” and prior
`
`art under at least § 102(e).
`
`23 Maturi, 2:47-54.
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`24 Id., 4:55-60; id., Figs. 1, 3.
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`25 Id., Fig. 3 (annotated).
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`Bheda
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`3.  
`Bheda discloses a “novel apparatus and method for decompressing or
`
`‘decoding’ compressed digital audio/video signals in a highly efficient manner.”26
`
`It describes a host processor that performs “pre-processing tasks” such as
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`“demultiplexing”27 and a subprocessor that performs post-processing tasks such as
`
`decoding.28 Each can use system memory 140,29 and the subprocessor includes a
`
`
`26 Id., 1:6-9.
`
`27 Id., 3:46-55.
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`28 Id., 5:11-19 (performs discrete cosine transform, motion compensation, and
`
`more); see also Dec., ¶¶18-19, 35 (those algorithms are part of MPEG decoding).
`
`29 Bheda, 5:59-66.
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`memory controller to also access external DRAM.30 Moreover, Bheda discloses
`
`that system memory and DRAM can be “combined as a single memory unit,”31 at
`
`which point the DRAM controller 174 would be used by the host processor to
`
`access DRAM.
`
`Lam
`
`4.  
`Lam discloses an MPEG decoder system that decodes multiplexed
`
`multimedia data using a single memory—namely, the main memory of the
`
`computer.32 Lam specifies that prior art MPEG decoders included “a large amount
`
`(e.g., 2 megabytes) of memory” and that “[s]uch chip sets can be expensive.”33
`
`Lam states that “it would be desirable to employ the main memory of the
`
`computer” for decoding.34
`
`
`30 Id., 7:28-30.
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`31 Id., 11:20-22.
`
`32 Lam, 6:59-62 (“While prior MPEG 2 decoding circuits employed dedicated
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`memory, the present invention shares the main memory 108 with the computer
`
`102.”).
`
`33 Id., 2:19-22.
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`34 Id., 2:22-23.
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`Yao
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`5.  
`Yao describes the many benefits of a “unified memory architecture (UMA),”
`
`such as, lower cost, power consumption, and chip size.35 Yao explains that UMA
`
`“will soon become a dominant PC approach”36 and “that, 18 months from now, the
`
`UMA approach will be dominant for all PCs but high-end desktops.”37
`
`C.   Level of Ordinary Skill in the Art
`
`A POSITA would have held a bachelor’s degree in electrical engineering,
`
`computer engineering, or computer science, or a closely related field, with at least
`
`two years of experience in the design and development of multimedia processor
`
`systems utilizing memory.38 Alternatively, a POSITA would have held a master’s
`
`degree in electrical engineering, computer engineering, or computer science, or a
`
`closely related field, and fewer years of experience in the design and development
`
`of multimedia processor systems utilizing memory.39
`
`
`35 Yao, 3.
`
`36 Id., 4.
`
`37 Id., 5.
`
`38 Dec., ¶¶50-52.
`
`39 Id.
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`D.   Applicable Legal Standards
`
`“To establish anticipation, each and every element in a claim, arranged as is
`
`recited in the claim, must be found in a single prior art reference.”40 In determining
`
`whether a claim is obvious to a POSITA at the time of the invention, the Board
`
`considers (1) the level of ordinary skill in the pertinent art; (2) the scope and
`
`content of the prior art; (3) the differences between the claimed invention and the
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`prior art; and (4) objective secondary considerations of non-obviousness, if any.41
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`V.   HOW THE CHALLENGED CLAIMS ARE UNPATENTABLE
`A.   Ground 1: Fujii Anticipates Claims 1, 7, and 16.
`1.  
`Independent Claims 1 and 16
`Preamble: The preambles for claims 1 and 16 are non-limiting as they fail
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`to give life, meaning, or vitality to the claims.42 Nevertheless, Fujii discloses a
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`40 ZTE Corp. v. ContentGuard Holdings Inc., IPR 2013-00134, Paper 12 at 24
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`(P.T.A.B. June 19, 2013) (citing Karsten Mfg. Corp. v. Cleveland Golf Co., 242
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`F.3d 1376, 1383 (Fed. Cir. 2001)).
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`41 See, e.g., SIBIA Neurosciences, Inc. v. Cadus Pharm. Corp., 225 F.3d 1349,
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`1355 (Fed. Cir. 2000). Dr. Silva applied such anticipation and obviousness
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`standards, which are also applied herein, in analyzing the Challenged Claims. Dec.,
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`¶¶43-48.
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`42 Intirtool Ltd. v. Texar Corp., 369 F.3d 1289, 1295 (Fed. Cir. 2004); Dec., ¶58.
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`“[video/MPEG] decoder system which includes a single memory for use by
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`transport, decode and system controller functions,” as recited in the preambles of
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`claims 1 and 16. Specifically, Fujii discloses an MPEG decoder system, which is a
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`specific type of video decoder, that includes a single memory (RAM) for use by
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`transport, decode, and system controller functions.43 Fujii notes that the MPEG
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`standard is a “well known” method of encoding video,44 and explains that it intends
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`to address the “problems of an increased number of system components and an
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`increased cost” in prior art MPEG decoder systems.45 That solution includes a
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`single RAM for use by the transport, decode, and system controller modules.46
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`How the transport, decode, and system controller modules use this RAM is
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`described further below.
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`a)  
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`Elements 1.1 and 16.1: “a channel receiver for receiving
`and47 [MPEG encoded/encoded video] stream”
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`Fujii discloses a channel receiver for receiving an MPEG encoded stream.
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`Specifically, Fujii discloses a “tuner” that “selects data of one channel transmitted
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`43 Fujii, Abs., 3:60-64, Fig. 11; Dec., ¶¶58-59.
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`44 Fujii, 1:13-18.
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`45 Id., 2:58-63.
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`46 Id., 3:60-64; see also id., Fig. 11 (depicting single RAM 7).
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`47 It appears element 1.1’s “and” should be “an.”
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`Petition for Inter Partes Review of U.S. Patent No. 5,870,087
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`from a communications medium such as a CATV and a communications satellite,
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`and supplies the selected channel data to a demodulator.”48 That data stream
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`includes “TS packet[s]”49 defined by the MPEG standard.50
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`b)  
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`Elements 1.2 and 16.2: “transport logic coupled to the
`channel receiver which demultiplexes one or more
`multimedia data streams from the encoded stream”
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`Fujii discloses transport logic coupled to the channel receiver which
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`demultiplexes one or more multimedia data streams from the encoded stream.
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`Fujii’s “transport logic” is program packet filter 15 and interface unit 14:51
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`48 Fujii, 6:1-5; id., Fig. 1 (box 1), Fig. 11 (box 1).
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`49 Id., 6:9-10.
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`50 Id., 1:31-36; Dec., ¶¶20-21, 60-61.
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`51 Fujii, Fig. 11 (annotated). At best, block 206 recited in the ‘087 specification
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`corresponds to the claimed function of demultiplexing one or more multimedia
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`data streams from the encoded stream under a § 112(6) analysis. ‘087 Patent, 8:10-
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`13, 8:17-21, 12:60-63, Fig. 3. Fujii’s combination of program packet filter 15 and
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`interface unit 14 is a structure corresponding to the ‘087 Patent’s block 206. Fujii,
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`7:10-11, 9:23-25, 9:47-50, 9:59-65, 10:8-13, Fig. 11; Dec., ¶¶63-65.
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`Fujii’s tuner (“channel receiver”) transmits the encoded stream to the
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`demodulator,52 then to RAM53 where it is sent to “program packet filter 15.”54 The
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`“program packet filter 15 derives from transmitted TS [transport stream] packets a
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`PSI packet and a TS packet containing an element of the user selected program ...
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`and supplies the filtered packets to the interface unit.”55
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`52 Fujii, 6:2-5.
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`53 Dec., ¶65.
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`54 Fujii, 9:14-16.
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`55 Id., 9:16-19.
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`Program packet filter 15 performs the algorithm of Figure 15,56 using a
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`packet ID, i.e., PID, stored in RAM (S1) to demultiplex the encoded stream into a
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`video stream (S5 and S6) and audio stream (S5 and S7).57 Program packet filter 15
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`sends the data to the transfer buffer of interface unit 14, which saves demultiplexed
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`streams to the RAM memory.58
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`c)  
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`Elements 1.3 and 16.3: “a system controller coupled to
`the transport logic which controls operations within the
`[MPEG/video] decoder system”
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`Fujii discloses a system controller coupled to the transport logic which
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`controls operations within the MPEG decoder system. Fujii’s “system controller”
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`56 Id., 10:8-13.
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`57 Id., Fig. 15; see also id., 7:10-11 (“packet filtering (or demultiplexing) process in
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`accordance with the algorithm illustrated in FIG. 7”); id., 10:11-13 (“The processes
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`of S5 to S9 after the packet PID is fetched are the same as FIG. 7.”); Dec., ¶¶64-
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`65.
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`58 Dec., ¶¶64-65; Fujii, 9:23-25, 9:47-50, 9:59-65; see also id., 11:42-44 (“The
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`channel demultiplexer 202 shown in FIG. 17 corresponds to the circuit constituted
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`by the program packet filter 15 and interface unit 14 shown in FIG. 11.”), 6:10-13,
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`Fig. 14.
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`includes microprocessor 12, which is coupled to program packet filter 15 and
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`interface unit 14:59
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`The microprocessor provides “system control.”60 For instance, it schedules
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`data moves61 and handles interrupts.62
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`59 Fujii, Fig. 11 (annotated).
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`60 Id., 10:14; see also id., 3:60-64 (“a RAM used by a CPU for the system
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`control”).
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`61 Id., 6:10-13, 9:47-50.
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`62 Id., 6:43-45, 9:42-46; Dec., ¶¶66-67.
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`d)  
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`Elements 1.4 and 16.4: “[an MPEG/a video] decoder
`coupled to receive one or more multimedia data streams
`output from the transport logic, wherein the
`[MPEG/video] decoder operates to perform
`[MPEG/video] decoding on the multimedia data
`streams”
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`Fujii discloses an MPEG decoder coupled to receive multimedia data streams
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`output from the transport logic, and operates to perform MPEG decoding on the
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`multimedia data streams. Fujii’s video decoder 8 and audio decoder 10 are an
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`MPEG decoder:63
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`63 Fujii, Fig. 11 (annotated); Dec., ¶¶68-70.
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`Each is coupled to a data bus to receive multimedia data streams outputted
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`from the transport logic (program packet filter 15 and interface unit 15).64 The
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`transport logic outputs the demultiplexed multimedia data streams and saves them
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`to RAM65 so that the “decoders” only receive filtered (i.e., demultiplexed)
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`streams.66 The “video data” and “audio data” are supplied to the decoders from
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`RAM “via the bus.”67 The decoder “expands and decodes the encoded video
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`data…and encoded audio data.”68
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`e)  
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`Elements 1.5 and 16.5: “a memory coupled to the
`[MPEG/video] decoder, wherein the memory is used by
`the [MPEG/video] decoder during [MPEG/video]
`decoding operations”
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`Fujii describes a memory coupled to the MPEG decoder. For example,
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`Fujii’s video and audio decoders 8, 10 are coupled to RAM 7 through a data bus:69
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`64 Fujii, Fig. 11.
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`65 Id. 9:59-61.
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`66 Id., 10:8-11; see also id., 4:12-14.
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`67 Id., 4:55-57; Dec., ¶¶68-69.
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`68 Fujii, 4:60-65.
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`69 Id., Fig. 11 (annotated); Dec., ¶¶72-73.
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`Fujii explains that the “encoded stream” is “stored via the bus access means
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`and the bus into the random access memory” and “via the bus the video data is
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`supplied to the video data decoding means” and the “audio data decoding
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`means.”70 Fujii further explains that this “RAM” is used by both the
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`“microprocessor for system control” and as the source of “data [that] can be
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`supplied to the decoders.”71
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`Fujii discloses that the memory is used by the MPEG decoder during MPEG
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`decoding operations, and the decoder is operable to access the memory during
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`70 Fujii, 4:51-57.
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`71 Id., 10:14-16.
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`MPEG decoding operations.72 Fu