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`This material may be protected by Copyright law (Title 17 U.S. Code)
`
`>UTER PRESS ASSOCIATION WINNER _.,?-~~ T COMPUTER NEWSLETTER
`/\.' .:/
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`1YHL:ROPROCES8fJR~"REPORT
`THE INSIDERS' GUIDE TO ~ItR,€1PRQ,~ESSOR HARDWARE
`.... ~ ow
`$'
`Unified Memory Architecture Cuts PC Cost
`Defines the Platform for Next Generation of Mainstream Computers
`
`VOLUME 9 NUMBER 8
`
`JUNE 19, 1995
`
`byYongYao
`
`A new wave of PC design, named unified memory
`architecture (UMA), is quietly sweeping the PC indus(cid:173)
`try. With the unified memory architecture, a PC com(cid:173)
`bines its main memory and its frame buffer in a single
`physical DRAM array, eliminating the traditional stand(cid:173)
`alone frame buffer-a $30 to $60 saving. Core-logic ven(cid:173)
`dors are rushing to get on the UMA bandwagon, and
`companies that build video/graphics controllers are ei(cid:173)
`ther seeking partners or diving into the already crowded
`core-logic business. System manufacturers are enthusi(cid:173)
`astic about the new architecture and are eager for the
`cost advantage of upcoming UMA chip sets.
`The potential impact ofUMA, however, is far more
`than just cost savings. A paradigm shift from the 16-
`year-old PC architecture originated by IBM, UMA will
`redefine the business model of some chip makers and
`trigger another round of consolidation in the core-logic
`and graphics markets. Coupled with a move to get rid of
`the ISA bus, the unified memory architecture leads to a
`new level of integration. More functions and features
`will be packed into the PC without significant price in(cid:173)
`creases, ultimately benefiting the consumer.
`
`UMA Approach Brings Cost Savings
`Let us examine the memory requirement for today's
`mainstream PC displays. An 800 x 600 screen with 8-bit
`color requires 480K of memory. A 1024 x 768 screen with
`8-bit color requires 768K, and the same 1024 x 768 reso(cid:173)
`lution requires 1.5M for 16-bit color. On the other hand,
`the granularity offered by today's commodity DRAM
`technology is 256K x 16. Thus, to satisfy the requirement
`of 480K of memory in a 32-bit-wide graphics subsystem
`(using two DRAMs), a standalone frame buffer has to be
`1M in size, wasting 0.52M of valuable DRAM. By the
`same token, a half megabyte of DRAM will be wasted if
`the frame buffer requires 1.5M.
`In the unified memory architecture, however, the
`system can allocate the exact amount of DRAM required
`
`( 0
`
`(
`
`for the frame buffer. During its booting sequence, the
`machine assigns a block of DRAM for its frame buffer,
`and whatever remains is used for main memory. The
`size for the frame buffer is dynamically configurable, de(cid:173)
`pending on the choice of display resolution and color
`depth. For instance, 480K will be assigned for 800 x 600
`resolution and 8-bit color.
`The memory granularity using the UMA approach
`is determined by the operating system. For DOS and
`Windows, the granularity is 64K This is the maximum
`possible amount of DRAM wasted. In the above example,
`32K of DRAM is wasted. Nothing will be wasted if the
`display resolution is 1024 x 768, whether it is 8-bit, 16-
`bit, or 24-bit color.
`The cost savings do not come for free. Assume that
`a PC has 8M of main memory, a 1M separate frame
`buffer, and a 1024 x 768 display with 8-bit color. Now let
`its graphics subsystem share the 8M DRAM with its
`Continued on page 6
`
`In This Issue
`
`Unified Memory Architecture Cuts PC Cost .................. l
`
`Editorial: PowerPC Delivers Beef, But No Sizzle .......... 3
`
`Most Significant Bits ....................................................... 4
`
`Intel Plugs i960 into PC Servers .................................. 10
`
`Power PC 604 Emerges in Systems .............................. :12
`
`Pentium Competitors Go Head to Head ...................... 14
`
`Patent Watch ................................................................. 21
`
`Literature Watch ........................................................... 22
`
`Recent IC Announcements ........................................... 23
`
`Resources ....................................................................... 24
`
`Copyright C 1995 MicroDesign Resources. Reproduction by any means ia expreuly prohibited.
`
`ISSN 0899-9341.
`
`AMAZON 1009
`Page 1 of 6
`
`

`

`IV/JCROPROCESSOR REPORT
`
`Unified Memory
`Continued from page 1
`
`main memory subsystem, eliminating the 1M frame
`buffer. Since 768K of the 8M must be used for the graph(cid:173)
`ics subsystem, only 7 .25M will be available for the OS
`and applications. If the OS and applications need more
`than 7.25M of main memory, the 9% shortage of avail(cid:173)
`able memory will increase the amount of swapping be(cid:173)
`tween main memory and the hard disk, which degrades
`performance. For a true-color high-resolution display,
`the memory loss is more significant.
`Fortunately, most commercially available graphics
`applications are written for 8-bit color, and most of
`today's screens are either 800 x 600 or 1024 x 768. To
`steal one-half or three-quarters of a megabyte from the
`8M main memory generally causes no performance prob(cid:173)
`lems. But the $30 savings is substantial in today's main(cid:173)
`stream desktop market, where system OEMs negotiate
`over pennies. This explains why most OEMs are enthu(cid:173)
`siastic about UMA.
`The exact savings are implementation dependent.
`For performance reasons, the amount of memory for the
`frame buffer may be added to the main memory. For the
`case above, this would result in 9M of main memory,
`with 8.25M available for OS and applications. Another
`way to trade the cost savings for enhanced performance
`is to add an L2 cache. The L2 cache will reduce CPU ac(cid:173)
`cesses to DRAM, leaving more memory bandwidth for
`graphics. Therefore, under the UMA umbrella, there
`will be different approaches for chip-set design.
`
`Weitek Samples 486 UMA Chip Set
`Aiming to bring high-performance 64-bit graphics
`and multimedia to low-end 486 PCs, Weitek has an(cid:173)
`nounced its W464 UMA chip set. Historically, Weitek
`has not been involved in the core-logic business. It does,
`however, have graphics expertise and PC market experi-
`
`CPU
`tt.
`Address l
`
`CPU Bus
`
`-
`
`c:
`
`Cache
`SRAM
`
`t
`
`t
`
`! Da~
`
`Host
`IIF
`
`PCI
`IIF
`
`RAM
`DAC/
`CRTC
`
`T
`Figure 1. The W464 chip set integrates graphics and core-logic
`chips that share a single DRAM array.
`
`' - - -
`PCibus
`
`lD
`Host
`1/F g
`i
`>-
`as
`t:
`0
`Cache 8 ~
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`Q)
`0
`:::>
`~
`::::.
`:::>
`C)
`C)
`
`DMA
`
`ISA
`1/F
`
`PCI
`1/F
`1
`
`ence. This is a good example of how the unified memory
`architecture can change a company's business outlook.
`As Figure 1 shows, the chip set is composed of two
`208-pin PQFP devices that integrate complete core logic
`for a 486 PC (including Cyrix Mise), a 64-bit DRAM(cid:173)
`based GUI accelerator, and a 135-MHz RAMDAC. The
`graphics accelerator, Weitek's fourth-generation high(cid:173)
`performance design, handles up to 1280 x 1024 resolu(cid:173)
`tion and 32-bit color, 256 Windows raster operations
`(ROPs), and full plug-and-play compatibility. In addi(cid:173)
`tion, graphics data is stored using a lossless compression
`algorithm, reducing the amount of memory needed for
`the frame buffer.
`Weitek has seen the first silicon of its W464 chip
`set, which is currently in debugging. It is now running
`DOS and Windows applications. The W464 is expected
`to be in production by September, making it the indus(cid:173)
`try's first PC UMA chip set that offers a PCI interface.
`The Weitek implementation has gone one step fur(cid:173)
`ther. It eliminates not only the standalone frame buffer
`but also the separate graphics-controller chip. Compared
`with most 32-bit 486 chip sets, the W 464 may actually
`offer better performance, due to its 64-bit memory and
`graphics, while lowering overall system cost.
`Since the 464 chip set works only with the 486, it
`might be too late for the desktop market, which is
`rapidly moving to Pentium-class CPUs. Given the Sep(cid:173)
`tember production date of the W464, OEMs must decide
`whether to use it based on the system redesign cost and
`delayed time to market. Even though Weitek will pro(cid:173)
`vide a reference design kit (which has become a common
`business practice in the PC world) for launching a new
`design, system manufacturers will still need a certain
`amount of design effort. Weitek's timing would be better
`for the 486 notebook market, but the W464 is not a 3.3-
`V chip set. It also lacks enhanced power management
`and LCD control logic.
`Weitek is developing a Pentium chip set, named
`the W564. The experience of the W464 will certainly
`help Weitek get this Pentium chip set to market more
`quickly and with less design risk. The W564 will sup(cid:173)
`port all Pentium-pinout CPUs (see page 14). It will also
`add several performance enhancements, including
`Weitek's video-acceleration technology, local-bus EIDE,
`and advanced DRAM support. The W564 will be a 3.3-V
`device with 5-V-tolerant I/0.
`VLSI Plans a Single-Chip Solution
`Like Weitek, VLSI Technology has put th e graphics
`controller into a core-logic UMA chip set. VLSI differen(cid:173)
`tiates its solution by targeting Pentium-class CPUs with
`a 3.3-V design. VLSI has been designing its desktop
`UMA chip set, named Coyote, and its notebook UMA
`chip set, Falcon, in parallel. By incorporating the Intel
`burst order as well as th e linear burst mode, the two-
`
`6
`
`J UNE 19, 1995
`
`AMAZON 1009
`Page 2 of 6
`
`

`

`chip sets will support Pentium, the K5, and Ml. The pro(cid:173)
`jected date for engineering samples is 1Q96 for Coyote
`and 2Q96 for Falcon. Using a 352-pin BGA package,
`VLSI designers combine almost all core logic and graph(cid:173)
`ics-controllogic into a single chip. Figure 2 shows a sys(cid:173)
`tem diagram for the Coyote chip set.
`The VL82C546 integrates a DRAM controller, PCI
`interface, graphics accelerator, L2 cache controller,
`RAMDAC, and distributed DMA controller (see sidebar,
`next page). The DRAM control logic supports fast-page(cid:173)
`mode DRAM, EDO DRAM, SDRAM, and SGDRAM. By
`integrating the distributed DMA and serial interrupt,
`VLSI makes the VL82C542 ISA bridge chip optional.
`This integration makes it possible to have high-speed yet
`compatible PCI connections for legacy devices.
`VLSI has developed its own graphics technology,
`called the GraphiCore Architecture, in the past two
`years. The key elements of GraphiCore are a config(cid:173)
`urable geometry pipeline and an orthogonal instruction
`set for single-state execution. The accelerated graphics
`functions include line draw, clipping, all 256 Windows
`ROPs, bitBLT, stretchBLT, patternBLT, color expan(cid:173)
`sion, color compression, rectangle fill, and text opera(cid:173)
`tions. The graphics accelerator resides on the CPU bus
`so as to run at the CPU bus frequency.
`In contrast to non-UMA approaches, VLSI's solu(cid:173)
`tion minimizes chip count, cuts overall system cost, re(cid:173)
`duces power consumption, and eliminates redundant
`functions. These features are especially important for
`notebooks, where board space and power budget are crit(cid:173)
`ical. With its parallel development projects, VLSI may
`well be the first company to bring a UMA notebook chip
`set to market. This strategy will give VLSI a head start
`for Pentium-class notebooks.
`Opti Partners with Graphics Vendors
`Opti has taken a different approach, defining a 20-
`page specification for the interface between the memory
`controller and the graphics controller. Figure 3 shows
`the proposed system. The interface is straightforward.
`Essentially, it consists of only two signals: MREO# and
`MGNT#. Under Opti's specification, the memory controller
`is the default owner of the DRAM array. The graphics
`controller must send a request (MREQ#=O) to the memory
`controller every time it needs to access the DRAM array.
`It will not gain access until the memory controller re(cid:173)
`sponds with an acknowledge (MGNT#=O).
`Opti presented this proposal to the VESA commit(cid:173)
`tee last month to stimulate a standardization process.
`Besides the two-signal interface, Opti's specification also
`includes recommendations on system BIOS, device dri(cid:173)
`vers, and future system compatibility.
`Because of the slow process of standardization, Opti
`has joined with a couple of unnamed graphics vendors to
`provide a UMA core-logic and graphics chip set. It has
`
`,\I I C I~ 0 P I{ 0 C E S S 0 R R E P 0 I{ T
`
`EDO
`DRAM
`or
`SDRAM
`
`CPU Bus = Control
`
`352BGA
`
`VL82C546
`
`Peripheral
`Control
`208MQFP
`
`VI...82C547
`
`PCI Slols
`
`00001
`
`Optional ISA
`Bridge
`160 MQFP
`
`VL82C542
`
`Figure 2. VLSI's Coyote chip set is a single-chip solution for the core
`logic and graphics functions.
`
`also been working with several system houses for early
`design-ins. Opti expects that its UMA core-logic chip set
`will be on the market by year-end. The supporting
`graphics chips should arrive at about the same time.
`Compared with VLSI's approach, Opti's solution
`will have some performance disadvantages due to its
`interchip arbitration, although some of the arbitration
`can be overlapped with the DRAM's recharge time. It
`does, however, have the advantage of being flexible. De(cid:173)
`signers have flexibility in architecture trade-offs, while
`OEMs have flexibility when choosing graphics solu(cid:173)
`tions. This approach will be appreciated by those com(cid:173)
`panies having design expertise with either core logic or
`graphics but not both.
`Opti is a major player in the core-logic business. Its
`business model has always been to pursue volume mar(cid:173)
`kets. A fundamental question to be asked before adopting
`an Opti-like approach, however, is why such an interface
`protocol is needed in the first place. If the graphics/video
`controller is integrated into the core-logic chip set, this
`protocol becomes unnecessary.
`
`!
`Optl
`Host
`Memory
`Controller
`
`P54C
`
`1r
`I
`
`Oala(63:0)
`
`Optl
`Data
`Buffer
`Controller
`
`l
`
`MREGI
`
`PCI bus
`
`!
`Third Party
`MGNTI
`I Memav A[11:0} ~ory A[B:Q] Graphics/
`VIdeo
`CAS(7:0)f
`CAS£7:0)1
`Accelerator
`
`RASf
`
`RASf
`
`DRAM
`Arrary
`
`Memory Oala (63:01
`
`Figure 3. Opti's proposal includes signaling between the memory
`controller and the graphics controller.
`
`JUNE 19, 1995
`
`7
`
`AMAZON 1009
`Page 3 of 6
`
`

`

`MICROPROCESSOR REPORT
`
`Eliminating the ISA Bus
`The ISA bus, introduced in 1981, has long been in(cid:173)
`adequate for PC performance needs. Most PCs shipped
`today have two peripheral buses: ISA and PCI. It
`would be nice ifthere were only one peripheral bus, but
`there are two major technical issues-legacy DMA and
`legacy interrupts-that prevent PC makers from get(cid:173)
`ting rid of the ISA bus.
`To support legacy DMA, the PCI bus must address
`three problems. First, PCI does not have the necessary
`seven DRQ# and seven DACK# signals. Second, on the
`ISA bus, the I/0 and memory commands are separate
`signals. Thus, simultaneous I/0 and memory transfers
`are possible on the ISA bus but not on the PCI bus, ac(cid:173)
`cording to its current definition. The third technical dif(cid:173)
`ficulty is that the ISA bus allows long-length I/0 trans(cid:173)
`fers (on the order of one microsecond), which will create
`a major performance limitation for PCI.
`In terms of legacy interrupts, the PCI bus has only
`four sharable IRQs, while the ISA bus supports 11
`edge-sensitive IRQs. The common solution is to intro(cid:173)
`duce sideband signals from PCI to ISA. This solution
`does not allow the elimination of the ISA bus.
`Aiming to introduce products without an ISA bus,
`eight companies, including Vl.SI, formed a consortium
`in late 1994 to define a standard to support ISA devices
`on PCI. The standard, called distributed DMA, is now
`in its final legal review and will soon be released to the
`public. Following the distributed DMA standard, chip
`vendors can integrate ISA support into PCI compo(cid:173)
`nents. PC system manufacturers will soon be able to
`build PCs without the ISA bus, resulting in higher in(cid:173)
`tegration, better performance, and yet lower cost PCs.
`
`PCs are a commodity business: the bottom line for a
`system OEM is to lower its manufacturing cost while
`maximizing system performance. To be adopted by PC
`makers, every new technology must add real value and
`improve the bottom line. For example, a few years ago
`Intel and ATI tried to establish a standard for interfac(cid:173)
`ing separate graphics and video chips. The standard did
`not take off because there was no incentive for separat(cid:173)
`ing graphics and video, which should naturally fit to(cid:173)
`gether. Therefore, any separate UMA graphics approach
`may be short-lived for the mainstream PCs; the inte(cid:173)
`grated approach will ultimately prevail.
`
`Everyone Wants a Common Standard
`Although an Opti-like interface protocol might be
`short-lived for mainstream PCs , a common specification
`for BIOS, device drivers, and future system compatibil(cid:173)
`ity is extremely important. The entire PC industry will
`benefit if there is only one UMA standard. All the major
`UMA players have claimed that they would stand behind
`a common standard if one appears.
`
`In the past year, Opti, VLSI, and Intel have been
`the three biggest chip-set suppliers. Of these leaders,
`only Intel has not said whether it is working on UMA so(cid:173)
`lutions. Its latest chip sets, Triton and Orion, are not
`based on the unified memory architecture, but Intel is
`interested in UMA. No company can ignore the potential
`UMA impact, including the microprocessor giant. Intel is
`known to be collaborating with Cirrus Logic on UMA
`chip sets; Cirrus plans to roll out its UMA graphics con(cid:173)
`troller in the first half of 1996.
`Companies like Intel and Cirrus have been taking
`cautious steps, carefully examining the issues associated
`with different UMA approaches. PC graphics has some
`unique characteristics. For instance, more than 90% of
`CPU cycles to the frame buffer are write cycles; the CPU
`rarely reads from it. Furthermore, when both the mem(cid:173)
`ory subsystem and the graphics subsystem share the
`same bus bandwidth, what will be the overall perfor(cid:173)
`mance impact? In this design, it becomes critical to in(cid:173)
`telligently use the bus bandwidth, and the right kinds of
`FIFO schemes are helpful. Designers have to be careful
`that their machines will not hang up when end users
`switch display resolutions.
`Chips and Technologies also is working on its own
`UMA solution, which may be available before the end of
`the year. C&T's advantage is its in-house expertise on
`both graphics and core logic. Even so, C&T would like to
`work with others to drive one UMA standard, so all UMA
`chip sets can share the same BIOS and device drivers.
`
`Separate Frame Buffer Has Its Niche
`In the PC industry, most technologies or new archi(cid:173)
`tectures start at the high end and then migrate to the low
`end. It seems, however, that the unified memory archi(cid:173)
`tecture is evolving the other way around. It will be
`adopted by low-end PCs first, then by midrange PCs, and
`may eventually be incorporated into some high-end ma(cid:173)
`chines. The unified memory architecture is driven pri(cid:173)
`marily by cost reduction, whereas most other PC archi(cid:173)
`tecture changes are initiated to enhance performance.
`Even though the unified memory architecture will
`soon become a dominant PC approach, a graphics con(cid:173)
`troller with a dedicated frame buffer will still have a role
`for years to come. The desktop market alone is expected
`to exceed 50 million units in 1996, according to Com(cid:173)
`puter Intelligence InfoCorp. There is enough room for
`multiple solutions, including the conventional separate
`frame buffer.
`By using new DRAM technologies, such as MD RAM
`from MoSys, graphics companies such as Tseng Labs
`and S3 may design their video/graphics accelerators to
`deliver more performance or to embed specific features
`that serve power users. For those users, features such as
`video playback, 3D graphics, and image rendering will
`soon be mandatory. In addition, video and graphics are
`
`8
`
`JUNE 19, 1995
`
`AMAZON 1009
`Page 4 of 6
`
`

`

`still emerging technologies. More advanced approaches
`are under development. It will be much easier for the
`standalone graphics controller to take advantage of the
`latest developments.
`With its dedicated frame buffer and specialty mem(cid:173)
`ory, a high-end graphics controller should have perfor(cid:173)
`mance superior to its equivalent UMA solution. For in(cid:173)
`stance, in the UMA design, CPU memory accesses have
`to be held while the memory bus is busy serving graph(cid:173)
`ics functions. This alone can cause a 10% performance
`degradation for certain applications.
`We recommend that graphics chip vendors give
`their standalone controllers both a dedicated frame
`buffer and hooks for interfacing with some of the upcom(cid:173)
`ing UMA chip sets. This is a safe way for a graphics com(cid:173)
`pany to reduce risk and maintain its market share.
`Technology Revives the UMA Approach
`The idea of the unified memory architecture is noth(cid:173)
`ing new. Apple's early Macs and some workstations have
`been designed this way for years. Perhaps there were no
`particular reasons why IBM defined its early PCs using
`a separate frame buffer, although IBM had certain con(cid:173)
`straints on the availability of off-the-shelf components.
`In 1979, PCs were using text-mode monochrome dis(cid:173)
`plays; the amount of memory needed for those displays
`was very small. It would have been easier just to put the
`frame buffer into main memory.
`The non-UMA architecture, however, has been the
`PC platform of choice since day one. A few companies,
`such as C&T and Tandy, tried UMA once before but did
`not go far with it. Why, all of a sudden, has the unified
`memory architecture become so hot? Various technolo(cid:173)
`gies are converging to revive the unified memory archi(cid:173)
`tecture in the PC market.
`The increasing density of commodity DRAMs has
`made non-UMA solutions more costly. On the other
`hand, this same trend will make systems with at least
`16M of main memory more popular. Therefore, it makes
`more sense to steal main memory for the frame buffer.
`In addition, main-memory and frame-buffer band(cid:173)
`widths are converging. Exotic high-bandwidth memories
`for frame buffers are not gettin.g into volume PCs. These
`low volumes have kept their prices high. For example,
`VRAM chips have always been two or more times as ex(cid:173)
`pensive as commodity DRAMs.
`In contrast, affordable new DRAM technologies,
`such as EDO DRAMs, are substantially increasing main(cid:173)
`memory bandwidth, while advanced caching and buffer(cid:173)
`ing schemes have kept most CPU memory references off
`the main-memory bus. In addition, 64-bit data paths,
`data bursting, and high bus frequencies have greatly re(cid:173)
`duced the time needed to transfer a given amount of data.
`Together, these changes have created more bus band(cid:173)
`width for graphics/video functions.
`
`,\I 1 C R 0 P 1~ 0 C E S S 0 R R f: I' 0 R T
`
`Price & Availability
`Samples of the W464 UMA chip set are available
`now from Weitek in two 208-pin PQFPs. Production is
`scheduled to begin in September. The 10,000-piece
`price for the chip set is $43.50. For more information,
`contact Weitek (Sunnyvale, Calif.) at 408. 738.8400; fax
`408.739.4374.
`Samples of the Coyote chip set will be available in
`1Q96 from VLSI Technology, in a single 352-pin BGA.
`Production is scheduled to begin in 2Q96. Pricing of the
`chip set will be available in 4Q95. For more informa(cid:173)
`tion, contact VLSI (Tempe, Ariz.) at 602.752.6481; fax
`602.752.6014. For information on the distributed DMA
`standard, send e-mail to deuoy@tempe.ulsi.com.
`Samples of the Opti UMA chip set will be available in
`4Q95 at a $40 sample price. Production is scheduled to
`begin in 1Q96. For more information on Opti's UMA
`specification and its chip set, contact Opti (Santa Clara,
`Calif.) at 408.486.8605; fax 408.980.8860.
`
`Today's CPUs have enough computing power to
`handle jobs like line drawing, image decompression, and
`graphics rendering. These functions previously relied on
`special accelerators. A unified memory actually in(cid:173)
`creases CPU graphics performance by making it more
`convenient for the CPU to access the frame buffer.
`BGA packages and high integration offer designers
`an efficient way of balancing signal I/0 and chip gate
`count. It has become economical to pack the core logic
`and graphics control into one chip. Although the BGA
`package costs about one cent more per pin than the
`PQFP, the BGA package is relatively new, and there is
`room for BGA prices to drop.
`Because ofthe price tag for big monitors, main(cid:173)
`stream PCs may still be using 17" or smaller displays for
`some time to come. Given the limitations of human vision,
`going beyond the resolution of 1280 x 1024 does not make
`much sense for these monitors. Also, human eyes can dis(cid:173)
`tinguish only a certain number of colors: 24-bit color space
`is probably enough. These three facts tell us that the
`amount of memory needed for the graphics/video subsys(cid:173)
`tem is no more than 4M for mainstream PCs. They also
`show that the memory bandwidth for supporting the
`graphics subsystem will not increase dramatically.
`In short, technology has arrived at the point where
`it is inevitable for future mainstream PCs to incorporate
`the unified memory architecture. Some OEMs will show
`UMA systems at Comdex next spring. Almost all ven(cid:173)
`dors now working on UMA solutions have plans to ex(cid:173)
`tend this architecture to P6-class machines. We project
`that, 18 months from now, the UMA approach will be
`dominant for all PCs but high-end desktops. •
`Yong Yao is the director of MicroDesign Resources'
`Technology Roadmap service (see page 5).
`
`JUNE 19, 1995
`
`9
`
`AMAZON 1009
`Page 5 of 6
`
`

`

`HP Rolls Out 120-MHz PA-7200 Systems
`On the heels of its 100-MHz servers, HP has raised the
`speed of its PA-7200 and put it into a dual-processor
`workstation. The new J-series desktops deliver 169
`SPECint92 and 269 SPECfp92 with a single processor.
`Entry pricing for the 120-MHz J210 is $41,770 for the
`uniprocessor and $54,770 for two processors. The sys(cid:173)
`tems are due to begin shipments in 3Q95, but HP does
`not expect volume shipments until late this year.
`These systems set a new mark for PA-RISC perfor(cid:173)
`mance and keep HP ahead of Sun's 125-MHz Hyper(cid:173)
`Spare systems (see MPR 5/8/95, p. 4). Digital's Alpha
`workstations, however, deliver far better performance,
`and IBM's new 604-based workstations (see page 12)
`offer equivalent integer performance for far less money.
`HP is waiting for the PA-8000 to restore the competi(cid:173)
`tiveness of its product line, but that processor won't be
`available until1Q96.
`
`R4400 Reaches New Performance Level
`NEC has announced sampling of a 250-MHz R4400. The
`company achieved this speed using a 0.35-micron pro(cid:173)
`cess, which also shrinks the die to 108 mm2 . The com(cid:173)
`pany estimates that the new chip will achieve 175 SPEC(cid:173)
`int92 and 178 SPECfp92. Production shipments are
`slated for the third quarter. NEC did not announce vol(cid:173)
`ume pricing; samples are available for $2,000.
`The new version must satisfy high-end MIPS users
`until the R10000 is ready early next year. It keeps high(cid:173)
`end MIPS performance competitive with most other
`RISC architectures, at least until UltraSparc and the
`PowerPC 620 become available late this year. Interest(cid:173)
`ingly, the new R4400 has only 13% better integer perfor(cid:173)
`mance than the 133-MHz Pentium and requires a 20%
`larger die in a similar 0.35-micron process, gaining no
`advantage from its streamlined RISC architecture.
`
`Cypress Enters Pentium Chip-Set Market
`Cypress's first Pentium chip set uses an innovative inte(cid:173)
`grated cache to reduce cost while increasing perfor(cid:173)
`mance. The HyperCache chip set consists of three chips:
`a PCI and memory interface, a data-path chip with inte(cid:173)
`grated 128K cache, and a system I/0 device. The chip set
`supports Pentium-class CPUs from Intel, AMD, and
`Cyrix (see page 14) at bus speeds of up to 66 MHz.
`Integrating a complete 128K cache and tags into a
`single package eliminates the cost of several packages
`from a typical discrete cache. Furthermore, timing is
`greatly improved, as critical signals are no longer driven
`from chip to chip. HyperCache uses a synchronous core
`to deliver 3-1-1-1 burst timing, yet the entire chip set
`costs little more than a discrete synchronous cache of the
`same size. System performance is further improved by
`the cache's two-way set-associative design; discrete
`caches are typically direct mapped due to pin-count
`
`MICROPROCESSOR REPORT
`
`New Analyst Yong Yao
`Yong Yao has joined MicroDesign Resources as our
`senior analyst for PC technologies. His latest work ap(cid:173)
`pears on the cover of this issue, and he will continue to
`write articles for Microprocessor Report covering chip
`sets, graphics, and other aspects of system design.
`Yong comes to us from Vitesse, where he was the di(cid:173)
`rector of product planning as well as the designer of the
`multiprocessor V-Bus (see MPR 5/30/94, p. 1). His expe(cid:173)
`rience also includes designing system-logic chip sets,
`graphics chips, and network interfaces as well as re(cid:173)
`search at UC Berkeley. Yong has a PhD in electrical en(cid:173)
`gineering from Shanghai Jiao-tong University.
`His primary role with MDR will be to direct our Tech(cid:173)
`nology Roadmap service, which provides detailed infor(cid:173)
`mation on PC system design trends, including analyses
`of current products and projections of future configura(cid:173)
`tions and technology trends. For more information
`about this service, contact Yong at our editorial office
`(see page 2).
`
`limitations. Cypress claims that these features make its
`128K cache comparable to a 256K asynchronous design.
`The chip set includes a PCI-to-ISA bridge, EIDE
`support with bus mastering, DMA/interrupt control, a
`real-time clock, keyboard and mouse control, and power
`management, giving it a greater level of integration than
`Intel's popular Triton chip set. At $48 for the three-chip
`set, HyperCache carries about the same price as the
`cacheless Triton. The Cypress cache can be expanded in
`128K increments at $14 each.
`Cypress entered the chip-set arena by purchasing
`Contaq Microsystems, a 10-person design firm. Cypress
`itself is a leading supplier of cache chips for Pentium
`PCs, and this customer base should give its new product
`a quick entry into the high-volume chip-set market.
`
`Somerset Seeks New Head
`Seeking to streamline the decision-making process, ffiM
`and Motorola have decided to reorganize their Somerset
`Design Center, the source of most Power PC processor
`designs to date. Since its inception, the center has been
`managed jointly by IBM and Motorola personnel. This
`awkward structure has slowed progress in some areas
`and caused enough dissatisfaction that engineers have
`been leaving for greener pastures.
`Given the lackluster results of the 604 and 620 (see
`page 3), a change is in order. The companies have now
`assigned a single leader for each project, replacing the
`old co-manager structure. They are also seeking a single
`manager to oversee all of Somerset, although it may take
`months to locate the right person. The partners hope
`that these changes will spur progress on the next gener(cid:173)
`ation of PowerPC designs. •
`
`JUNE 19, 1995
`
`5
`
`AMAZON 1009
`Page 6 of 6
`
`