IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In the Inter Partes Review of:
`
`Trial Number: To Be Assigned
`
`U.S. Patent No. 5,870,087
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`Panel: To Be Assigned
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`Filed: November 13, 1996
`
`Issued: February 9, 1999
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`Inventor(s): Kwok Kit Chau
`
`Assignee: Avago Technologies General IP
`(Singapore) Pte. Ltd.
`
`Title: MPEG Decoder System And Method
`Having A Unified Memory For Transport
`Decode And System Controller Functions
`
`Mail Stop Inter Partes Review
`Commission for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`DECLARATION OF DR. CLAUDIO T. SILVA UNDER 37 C.F.R.
`§ 1.68 IN SUPPORT OF PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 5,870,087
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`TABLE OF CONTENTS
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`
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`I.  
`
`INTRODUCTION .......................................................................................... 1  
`
`A.   Professional Background ................................................................................. 1  
`
`B.   Documents and Information Considered ......................................................... 5  
`
`C.   Summary of Opinions ..................................................................................... 6  
`
`II.  
`
`BACKGROUND ............................................................................................ 7  
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`A.   Technology Overview ..................................................................................... 7  
`
`B.   The ‘087 Patent Overview ............................................................................. 12  
`
`C.   The Fujii Patent ............................................................................................. 14  
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`D.   The Maturi Patent .......................................................................................... 17  
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`E.   The Bheda Patent .......................................................................................... 19  
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`F.   The Lam Patent ............................................................................................. 20  
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`G.   The Yao Reference ........................................................................................ 22  
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`III.   LEGAL STANDARDS TO BE APPLIED .................................................. 23  
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`IV.   A PERSON OF ORDINARY SKILL IN THE ART ................................... 25  
`
`V.  
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`CLAIM CONSTRUCTION ......................................................................... 27  
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`VI.   DETAILED DISCUSSION .......................................................................... 29  
`
`A.   Fujii Anticipates Independent Claims 1 and 16. ........................................... 29  
`
`1.   Claims 1 and 16 Preambles: “[An MPEG/A video] decoder system which
`includes a single memory for use by transport, decode and system
`controller functions” .............................................................................. 29  
`
`2.   Claim Elements 1.1 and 16.1: “a channel receiver for receiving and
`[MPEG encoded/encoded video] stream” .............................................. 30  
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`3.   Claim Elements 1.2 and 16.2: “transport logic coupled to the channel
`receiver which demultiplexes one or more multimedia data streams from
`the encoded stream” ............................................................................... 32  
`
`4.   Claim Elements 1.3 and 16.3: “a system controller coupled to the transport
`logic which controls operations within the [MPEG/video] decoder
`system” ................................................................................................... 35  
`
`5.   Claim Elements 1.4 and 16.4: “[an MPEG/a video] decoder coupled to
`receive one or more multimedia data streams output from the transport
`logic, wherein the [MPEG/video] decoder operates to perform
`[MPEG/video] decoding on the multimedia data streams” ................... 37  
`
`6.   Claim Elements 1.5 and 16.5: “a memory coupled to the [MPEG/video]
`decoder, wherein the memory is used by the [MPEG/video] decoder
`during [MPEG/video] decoding operations” ......................................... 39  
`
`7.   Claim Elements 1.6 and 16.6: “wherein the memory stores code and data
`useable by the system controller which enables the system controller to
`perform control functions within the [MPEG/video] decoder system” . 42  
`
`8.   Claim Elements 1.7 and 16.7: “wherein the memory is used by the
`transport logic for demultiplexing operations” ...................................... 44  
`
`9.   Claim Elements 1.8 and 16.8: “wherein the [MPEG/video] decoder is
`operable to access the memory during [MPEG/video] decoding
`operations” ............................................................................................. 48  
`
`10.   Claim Elements 1.9 and 16.9: “wherein the transport logic is operable to
`access the memory to store and retrieve data during demultiplexing
`operations” ............................................................................................. 51  
`
`11.   Claim Elements 1.10 and 16.10: “wherein the system controller is
`operable to access the memory to retrieve code and data during system
`control functions” .................................................................................. 56  
`
`B.   Fujii Anticipates Dependent Claim 7. ........................................................... 57  
`
`1.   Claim Element 7.1: “wherein said memory includes a plurality of memory
`portions, wherein said memory includes a video frame portion for
`storing video frames” ............................................................................. 57  
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`2.   Claim Element 7.2: “a system controller portion for storing code and data
`executable by the system controller” ..................................................... 58  
`
`3.   Claim Element 7.3: “and a transport buffer portion for storing data used by
`the transport logic” ................................................................................. 59  
`
`C.   The Combination of Fujii and Bheda Renders Obvious Claims 2-3 and
`17. .................................................................................................................. 59  
`
`1.   Claim Elements 2.1 and 17.1: “wherein the [MPEG/video] decoder
`includes a memory controller coupled to the memory” ......................... 61  
`
`2.   Claim Elements 2.2 and 17.2: “wherein the transport logic is coupled to
`the memory controller and is operable to access the memory through the
`memory controller” ................................................................................ 63  
`
`3.   Claim Elements 2.3 and 17.3: “wherein the system controller is coupled to
`the memory controller and is operable to access the memory through the
`memory controller” ................................................................................ 64  
`
`4.   Claim 3: “The MPEG decoder system of claim 2, wherein the memory
`controller is operable to store compressed data in the memory to reduce
`memory storage requirements.” ............................................................. 65  
`
`D.   The Combination and Fujii and Lam Renders Obvious Dependent
`Claim 5. ......................................................................................................... 66  
`
`E.   The Combination of Maturi and Yao Renders Obvious Independent Claims
`1 and 16. ........................................................................................................ 69  
`
`1.   Claims 1 and 16 Preambles: “[An MPEG/ A video] decoder system which
`includes a single memory for use by transport, decode and system
`controller functions” .............................................................................. 69  
`
`2.   Claim Elements 1.1 and 16.1: “a channel receiver for receiving and
`[MPEG encoded/encoded video] stream” .............................................. 70  
`
`3.   Claim Elements 1.2 and 16.2: “transport logic coupled to the channel
`receiver which demultiplexes one or more multimedia data streams from
`the encoded stream” ............................................................................... 71  
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`4.   Claim Elements 1.3 and 16.3: “a system controller coupled to the transport
`logic which controls operations within the [MPEG/video] decoder
`system” ................................................................................................... 73  
`
`5.   Claim Elements 1.4 and 16.4: “[an MPEG/a video] decoder coupled to
`receive one or more multimedia data streams output from the transport
`logic, wherein the [MPEG/video] decoder operates to perform
`[MPEG/video] decoding on the multimedia data streams” ................... 74  
`
`6.   Claim Elements 1.5 and 16.5: “a memory coupled to the [MPEG/video]
`decoder, wherein the memory is used by the [MPEG/video] decoder
`during [MPEG/video] decoding operations” ......................................... 76  
`
`7.   Claim Elements 1.6 and 16.6: “wherein the memory stores code and data
`useable by the system controller which enables the system controller to
`perform control functions within the [MPEG/video] decoder
`system” ................................................................................................... 78  
`
`8.   Claim Elements 1.7 and 16.7: “wherein the memory is used by the
`transport logic for demultiplexing operations” ...................................... 86  
`
`9.   Claim Elements 1.8 and 16.8: “wherein the [MPEG/video] decoder is
`operable to access the memory during [MPEG/video] decoding
`operations” ............................................................................................. 88  
`
`10.   Claim Elements 1.9 and 16.9: “wherein the transport logic is operable to
`access the memory to store and retrieve data during demultiplexing
`operations” ............................................................................................. 90  
`
`11.   Claim Elements 1.10 and 16.10: “wherein the system controller is
`operable to access the memory to retrieve code and data during system
`control functions” .................................................................................. 93  
`
`F.   The Combination of Maturi and Yao Renders Obvious Dependent
`Claim 7. ......................................................................................................... 95  
`
`1.   Claim Element 7.1: “wherein said memory includes a plurality of memory
`portions, wherein said memory includes a video frame portion for
`storing video frames” ............................................................................. 95  
`
`2.   Claim Element 7.2: “a system controller portion for storing code and data
`executable by the system controller” ..................................................... 96  
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`3.   Claim Element 7.3: “and a transport buffer portion for storing data used by
`the transport logic” ................................................................................. 97  
`
`G.   The Combination of Maturi, Yao, and Bheda Renders Obvious Claims 2-3
`and 17. ........................................................................................................... 98  
`
`1.   Claim Elements 2.1 and 17.1: “wherein the [MPEG/video] decoder
`includes a memory controller coupled to the memory” ......................... 99  
`
`2.   Claim Elements 2.2 and 17.2: “wherein the transport logic is coupled to
`the memory controller and is operable to access the memory through the
`memory controller” .............................................................................. 101  
`
`3.   Claim Elements 2.3 and 17.3: “wherein the system controller is coupled to
`the memory controller and is operable to access the memory through the
`memory controller” .............................................................................. 102  
`
`4.   Claim 3: “The MPEG decoder system of claim 2, wherein the memory
`controller is operable to store compressed data in the memory to reduce
`memory storage requirements.” ........................................................... 103  
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`H.   The Combination of Maturi, Yao, and Lam Renders Obvious Claim 5. .... 104  
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`I.  
`INTRODUCTION
`1.   My name is Dr. Claudio T. Silva. I understand that I am submitting a
`
`declaration in connection with an inter partes review (“IPR”) proceeding before
`
`the United States Patent and Trademark Office for U.S. Patent No 5,870,087 (“the
`
`‘087 Patent”).
`
`2.  
`
`I have been retained on behalf of Amazon.com, Inc. and Amazon Web
`
`Services, Inc. to offer technical opinions with respect to the ‘087 Patent and the
`
`prior art references cited in this IPR.
`
`Professional Background
`
`A.  
`I am a Professor of Computer Science and Engineering and Data Science at
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`3.  
`
`New York University. Prior to my work in academia, I worked in industry for six
`
`years in the area of computer graphics and visualization. I received a Bachelor of
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`Science in Mathematics from the Federal University of Ceará in Brazil, and a
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`Ph.D. from State University of New York at Stony Brook in Computer Science.
`
`My curriculum vitae, which includes a more detailed account of my background,
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`experience, and publications, is attached hereto (Ex. 1004).
`
`4.  
`
`From July 1998 until July 2000, I served as an adjunct assistant professor in
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`the Department of Applied Mathematics and Statistics at SUNY Stony Brook.
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`From September 2002 until April 2006 I was an associate professor in the
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`Department of Computer Science & Engineering at Oregon Health & Science
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`
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`University. From October 2003 until June 2011, I was a faculty member at the
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`Scientific Computing and Imaging Institute at the University of Utah. From
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`January 2008 until May 2009 I served as Associate Director at the University of
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`Utah’s Scientific Computing and Imaging (SCI) Institute. I also served as an
`
`Associate Professor of Computer Science from October 2003 until June 2010, and
`
`a Professor of Computer Science from July 2010 until June 2011 at the University
`
`of Utah. I am currently a Professor of Computer Science and Engineering at
`
`NYU’s Tandon School of Engineering, a position I have held since July 2011
`
`(when the school was called Polytechnic Institute of NYU). I also serve as a
`
`faculty member to a number of organizations within NYU, including the Center for
`
`Urban Science and Progress, the Center for Data Science, and Courant’s
`
`Department of Computer Science.
`
`5.  
`
`Between 1998 and 2002, I worked in industry at the IBM T. J. Watson
`
`Research Center and AT&T Labs-Research. At both places, I worked on 3D data
`
`acquisition, modeling, and rendering techniques. As part of my activities at IBM, I
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`was part of the MPEG-4 3D Model Coding (3DMC) standardization committee.
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`6.  
`
`In 2011, I co-founded Modelo, Inc., a company that creates custom
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`advanced 3-D modeling solutions for its clients.
`
`7.  
`
`I have published over 220 technical articles, most at highly competitive
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`refereed conferences and rigorously reviewed journals. I currently serve as chair of
`
`
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`the executive committee for the IEEE Computer Society Technical Committee on
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`Visualization and Graphics. I also hold 12 U.S. patents. My publications have
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`received awards from organizations and programs such as the IEEE Shape
`
`Modeling International, IEEE Visualization, EuroVis (a conference co-sponsored
`
`by Eurographics and the IEEE Visualization and Graphics Technical Committee),
`
`and Eurographics (the European Association for Computer Graphics).
`
`8.   My research has been funded by the National Science Foundation, the
`
`Department of Energy, the National Aeronautics and Space Administration, the
`
`National Institutes of Health, the Alfred P. Sloan Foundation, the Gordon and
`
`Betty Moore Foundation, AT&T, IBM, and MLB Advanced Media. With regard to
`
`the subject matter of the ‘087 Patent relating to MPEG decoder systems, I have
`
`been a member of the MPEG-4 3D Model Coding (3DMC) standardization
`
`committee. I have also been a member of the Geometry Subcommittee for the
`
`NIfTI Data Format Working Group of the National Institutes of Health. I have also
`
`done relevant work in the areas of 3D rendering and graphics hardware design.
`
`9.   With regard to these research projects, I have published several papers,
`
`including this small sample (please see my CV for many more):
`
`•   “Multi-Fragment Effects on the GPU Using the k-Buffer,” L. Bavoil,
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`S.P. Callahan, A. Lefohn, J.L.D. Comba, and C. Silva, ACM
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`
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`SIGGRAPH Symposium on Interactive 3D Graphics and Games,
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`pages 97-104 (2007);
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`•   “Hardware-Assisted Visibility Sorting for Unstructured Volume
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`Rendering,” S. Callahan, M. Ikits, J. Comba, and C. Silva, IEEE
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`Transactions on Visualization and Computer Graphics, 11(3):285-295
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`(2005);
`
`•   iWalk: Interactive Out-Of-Core Rendering of Large Models, W.
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`Correa, J. Klosowski, and C. Silva, Technical Report TR-653-02,
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`Princeton University (2002);
`
`•   “Efficient Conservative Visibility Culling Using The Prioritized-
`
`Layered Projection Algorithm,” J. Klosowski and C. Silva, 7(4):365-
`
`379, IEEE Transactions on Visualization and Computer Graphics
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`(2001); and
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`•   “Efficient Compression of Non-Manifold Polygonal Meshes,” A.
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`Gueziec, F. Bossen, G. Taubin, and C. Silva, 14(1-3):137-166,
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`Computational Geometry: Theory and Applications (1999).
`
`10.  
`
`I have also taught graduate and undergraduate courses with a strong focus on
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`graphics, visualization, computer hardware, and data compression and
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`decompression.
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`11.  
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`I am being compensated at my standard consulting rate for my work on this
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`declaration. My compensation is not dependent on the outcome of this case, and I
`
`have no financial interest in the outcome.
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`B.   Documents and Information Considered
`
`12.  
`
`I have reviewed the ‘087 Patent, including the claims of the patent in view of
`
`the specification, and I have reviewed the ‘087 Patent’s prosecution history. In
`
`addition, I have reviewed the following documents:
`
`•   U.S. Patent No. 5,898,695 to Fujii et al. (“Fujii”);
`
`•   U.S. Patent No. 6,002,441 to Bheda et al. (“Bheda”);
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`•   1006 U.S. Patent No. 5,960,464 to Lam (“Lam”);
`
`•   1007 U.S. Patent No. 5,559,999 to Maturi et al. (“Maturi”);
`
`•   “Unified Memory Architecture Cuts PC Cost,” Y. Yao, Microprocessor
`
`Report, vol. 9, n. 8 (June 19, 1995) (“Yao”);
`
`•   Business Wire, “VESA Announces Release of Unified Memory
`
`Architecture Standard” (Mar. 8, 1996) (“1996 Business Wire Article”);
`
`•   Transmission of Non-Telephone Signals, Information Technology –
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`Generic Coding of Moving Pictures and Associated Audio Information:
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`Video, ITU-T Recommendation H.262, July 1995 (“H.262 Standard”);
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`•   “Fast Computer Memories,” R. Ng, IEEE Spectrum (Oct. 1992) (“Ng
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`Article”); and
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`•   IPR2016-00646 Institution Decision, Paper 11 (Aug. 22, 2016).
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`Summary of Opinions
`
`C.  
`In my opinion, claims 1-3, 5, 7, and 16-17 of the ‘087 Patent are anticipated
`
`13.  
`
`by the prior art, rendered obvious by the prior art, or both. In the remainder of this
`
`declaration, I demonstrate that:
`
`•   Fujii anticipates claims 1, 7, and 16 of the ‘087 Patent;
`
`•   The combination of Fujii and Bheda renders obvious claims 2-3 and
`
`17 of the ‘087 Patent;
`
`•   The combination of Fujii and Lam renders obvious claim 5 of the ‘087
`
`Patent;
`
`•   The combination of Maturi and Yao renders obvious claims 1, 7, and
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`16 of the ‘087 Patent;
`
`•   The combination of Maturi, Yao, and Bheda renders obvious claims
`
`2-3 and 17 of the ‘087 Patent; and
`
`•   The combination of Maturi, Yao, and Lam renders obvious claim 5 of
`
`the ‘087 Patent.
`
`14.  
`
`I also offer my opinion on how a person of ordinary skill in the art would
`
`have interpreted certain claim terms in the ‘087 Patent. My opinion on the
`
`interpretation of relevant claim terms is set forth in this declaration.
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`II.   BACKGROUND
`A.   Technology Overview
`15.   Multimedia data, in particularly video, has historically required a large
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`amount of storage space. The Moving Picture Experts Group (MPEG) was
`
`established in the late 1980s with the goal of creating a standard to allow for the
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`compression of multimedia data to decrease those storage requirements. That
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`group, in conjunction with the International Organization for Standardization
`
`(“ISO”), has developed multiple MPEG standards over time.
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`16.   MPEG-1, was published in the early 1990s as ISO/IEC 11172. It consisted
`
`of multiple sub-parts, such as 11172-1 (System), 11172-2 (Video), and 11172-3
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`(Audio). MPEG-1 built on the work of the Joint Photographic Experts Group
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`(JPEG), which developed a standard for image compression.
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`17.   MPEG-2 was published by 1996 as ISO/IEC 13818, though draft versions
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`were published before then. Like MPEG-1, MPEG-2 consisted of subparts 1
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`(System), 2 (Video), 3 (Audio), and others. Portions of MPEG-2 were also
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`published by the International Telecommunications Union (“ITU”) as H.220.0
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`(corresponding to 13818-1) and H.262 (corresponding to 13818-2).1 DVDs use
`
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`1 H.262 Standard at 2 (“The identical text is also published as ISO/IEC
`
`International Standard 13818-1.”)
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`MPEG-2 compression. MPEG-4 was ratified in the late 1990s, and MPEG-4 Part
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`10 (H.264) in the early 2000s.
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`18.   Both MPEG-1 and MPEG-2 compress video by taking advantage of spatial
`
`and temporal redundancies.2 Spatial redundancy refers to the fact that different
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`portions of an image (a single video frame) often contain the same or similar color
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`and light values. MPEG3 uses various algorithms, such as discrete cosine
`
`transform, quantization, and entropy coding, to take advantage of these intra-
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`frame redundancies.
`
`19.   MPEG encoding takes advantage of a video’s temporal redundancy, which
`
`refers to the fact that many portions of sequential video frames do not change over
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`short periods of time. Rather than store each such frame in its entirety, MPEG
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`encoding compares surrounding frames to generate motion vectors that describe
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`these changes. An MPEG decoder reverses this process using various techniques,
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`such as, motion compensation. However, techniques like motion compensation
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`require reference to a previous and/or future frame. Rather than make every frame
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`dependent on each other, in which case a single frame drop would destabilize the
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`decoding process, MPEG defines “intra-frames” (“I” frames) that are not
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`dependent on other frames. MPEG also defines “predicted frames” (“P” frames)
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`2 E.g., ‘087 Patent at 3:38-41.
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`3 Herein, “MPEG” refers to MPEG-1 and MPEG-2.
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`that are temporally compressed against a past frame, and “bi-directional frames”
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`(“B” frames) that are temporally compressed against both a past and a forward
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`frame. I frames provide a reference point for P and B frames, and P frames can
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`form a reference point for future P frames. The ‘087 Patent refers to reference
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`frames as “anchor” frames. An example portion of a video stream containing I, B,
`
`and P frames is shown in the MPEG-2 standard:4
`
`20.   As discussed earlier, an MPEG multimedia stream contains not only video
`
`data but also audio, text and pictures for subtitles, tables identifying the streams,
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`electronic guides, as well as other program-specific information or stream
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`4 H.262 Standard at 7.
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`metadata.5 In MPEG-1, data is placed into a “program stream.” In MPEG-2, data
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`can be placed into either a “program stream” (“PS”) or a “transport stream” (“TS”).
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`TS allows for error correction and stream synchronization, while PS lacks error
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`correction and is used in conditions where one does not expect to drop data, such as
`
`with DVDs. A transport stream consists of a series of TS packets, each of which is
`
`188 bytes in size and includes a header as well as a payload. Fujii illustrates these
`
`“TS packets”:6
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`21.   A TS packet’s payload can contain multiple PES (“Packetized Elementary
`
`Stream”) packets, each of which contains a PES Packet Header that identifies the
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`type of program element (for example, video, audio, text, etc.) contained in that
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`5 E.g., H.262 Standard at 8-9.
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`6 Fujii at Fig. 3A.
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`PES packet. Fujii’s Figure 3B shows that the TS packet’s data payload can also
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`include program-specific information:7
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`
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`22.   Whether the stream is a program or transport stream, a POSITA would have
`
`understood that the PES packets are combined into a single stream to be placed in
`
`the PS or TS packet. This combining process is called multiplexing. In general,
`
`this is done by interleaving packets containing video, audio, or other types of data.
`
`Multiplexing may also combine content as streams of different resolutions, such
`
`as, high resolution and low resolution, of the same content. To decode a
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`multiplexed stream, the combination process must be reversed, i.e., demultiplexed.
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`While demultiplexing is necessary to decode a program or transport stream, it is
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`7 Fujii at Fig. 3B.
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`not the same as decoding. Decoding converts the demultiplexed but encoded
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`(compressed) video or audio or text stream into raw (uncompressed) data.
`
`B.  
`The ‘087 Patent Overview
`23.   The ‘087 Patent generally relates to a single unified memory for decoding,
`
`or decompressing, video and audio data.8 The patent acknowledges that decoders
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`for MPEG-1 and MPEG-2 standards were known in the art.9 Such decoders
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`“typical[ly]” included on-chip and external memory,10 “transport logic which
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`operates to demultiplex received data into a plurality of individual multimedia
`
`streams”,11 and “a system controller which controls operations in the system and
`
`executes programs or applets.”12 The patent asserts that such “[p]rior art MPEG
`
`video decoder systems have generally” used “separate memory” for the decoder,
`
`on the one hand, and the transport and system controller logic, on the other.13 The
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`8 ‘087 Patent at 1:30-34.
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`9 ‘087 Patent at 4:14-28, 2:31-32 (“The two predominant MPEG standards are
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`referred to as MPEG-1 and MPEG-2.”).
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`10 ‘087 Patent at 4:14-17.
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`11 ‘087 Patent at 4:22-24.
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`12 ‘087 Patent at 4:25-27.
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`13 ‘087 Patent at 4:28-35.
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`patent contends that it was “generally not [] possible to combine these memories,
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`due to size limitations” and cost.14
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`24.   The patent purports to address this issue by use of a “unified memory for
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`multiple functions,” including “the transport logic, system controller, and MPEG
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`decoder functions.”15 The ‘087 claims, however, do not provide a way of
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`overcoming the memory size and cost limitations that, in the specification’s words,
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`made it impractical or impossible to combine the separate memories.
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`25.   Representative independent claim 1 recites:
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`1. An MPEG decoder system which includes a single memory for use by
`transport, decode and system controller functions, comprising:
`a channel receiver for receiving and MPEG encoded stream;
`transport logic coupled to the channel receiver which demultiplexes
`one or more multimedia data streams from the encoded stream;
`a system controller coupled to the transport logic which controls
`operations within the MPEG decoder system;
`an MPEG decoder coupled to receive one or more multimedia data
`streams output from the transport logic, wherein the MPEG decoder operates
`to perform MPEG decoding on the multimedia data streams; and
`a memory coupled to the MPEG decoder, wherein the memory is
`used by the MPEG decoder during MPEG decoding operations, wherein the
`memory stores code and data useable by the system controller which enables
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`14 ‘087 Patent at 4:35-43.
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`15 ‘087 Patent at 4:67-5:6.
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`the system controller to perform control functions within the MPEG decoder
`system, wherein the memory is used by the transport logic for
`demultiplexing operations;
`wherein the MPEG decoder is operable to access the memory during
`MPEG decoding operations;
`wherein the transport logic is operable to access the memory to store
`and retrieve data during demultiplexing operations; and
`wherein the system controller is operable to access the memory to
`retrieve code and data during system control functions.
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`26.   Challenged Claims 1 and 16 are independent claims. Challenged Claims 2-3,
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`5, and 7 depend upon claim 1. Challenged Claim 17 depends upon claim 16.
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`C.   The Fujii Patent
`27.   U.S. Patent No. 5,898,695 (“Fujii”) is titled “Decoder for Compressed and
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`Multiplexed Video and Audio Data.” As listed on the cover of the Fujii patent, the
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`named inventors are Yukio Fujii and Masuo Oku. The patent application that
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`issued as Fujii was filed on March 27, 1996, and claims priority to two Japanese
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`patent applications, both filed on March 29, 1995. It is my understanding that Fujii
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`is prior art to the ‘087 Patent.
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`28.   Fujii discloses an MPEG decoder system that decodes multiplexed
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`multimedia data by consolidating memory components into a single RAM
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`memory.16 For example, Fujii “provide[s] a decoder for compressed and
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`multiplexed video and audio data, wherein packet landing buffers are allocated in a
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`RAM used by a CPU for the system control to thereby reduce the number of
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`components and lower the cost of components.”17 Annotated Figure 11 of Fujii
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`shows the transport logic (blue), system controller (green), decoder (orange), and
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`single memory (red):18
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`16 Fujii at 11:1-5 (“[T]he packet landing buffer is provided in RAM used by the
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`microprocessor for the system control. Therefore, data can be supplied to the
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`decoders without increasing the number of components and the cost thereof.”).
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`17 Fujii at 3:60-64.
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`18 Fujii at Fig. 11 (annotated).
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`29.   Fujii discloses three preferred embodiments that use a single memory. The
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`first preferred embodiment is depicted in Figures 1 through 10.19 The second
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`preferred embodiment is depicted in Figures 11 through 15.20 And a third preferred
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`embodiment in Figures 16 through 23.21 Many of Fujii’s described components and
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`functions are common between these three preferred embodiments. For instance,
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`Fujii explains that for its second preferred embodiment: “Blocks common to the
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`first embodiment are represented by identical reference numerals, and the
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`19 Fujii at 6:1-2.
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`20 Fujii at 9:10.
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`21 Fujii at 10:32.
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`description thereof is omitted.”22 Therefore, while my declaration focuses on the
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`second preferred embodiment, I cite some portions of the specification that
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`concern the first embodiment but that are also included in the second embodiment.
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`D.   The Maturi Patent
`30.   U.S. Patent No. 5,559,999 (“Maturi”) is titled “MPEG Decoding System
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`Including Tag List for Associating Presentation Time Stamps with Encoded Data
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`Units.” As listed on the cover of the Maturi patent, the named inventors are Greg
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`Maturi, David Auld, and Darren Neuman. The patent application that issued as
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`Maturi was filed on September 9, 1994. It is my understanding that Maturi is prior
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`art to the ‘087 Patent.
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`31.   Maturi discloses an MPEG decoder and system controller that have access to
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`the same DRAM 20.23 The system includes transport logic for demultiplexing (pre-
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`parser), video and audio decoders, and frame presentation units all accessing a
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`single unified DRAM.24 Maturi explains how its system controller (ho