United States Patent
`Gat
`
`115
`
`4,331,485
`[11]
`
`[45] May 25, 1982
`
`[54] METHOD FOR HEAT TREATING
`SEMICONDUCTOR MATERIAL USING
`HIGH INTENSITY CW LAMPS
`
`[76]
`
`Inventor: Arnon Gat, 1875 Newell Rd., Palo
`Alto, Calif. 94303
`
`[21] Appl. No.: 126,458
`
`Mar. 3, 1980
`[22] Filed:
`[51]
`Inte C13 caesccccccssssssee HOIL 21/26; HOIL 21/265
`[52] US. Che vaescccccccstessssssecsseeseserese 148/1.5; 148/187;
`357/91; 427/53.1; 427/55
`[58] Field of Search... 148/1.5, 187; 357/91;
`427/45.1, 53.1, 55
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,115,163
`9/1978 Gorina 0.eset 148/175
`
`4,151,008 4/1979 Kirkpatrick.....
`4,169,740 10/1979 Kalbitzer et al. wee 148/1.5
`
`OTHER PUBLICATIONS
`
`Cohenet al., Appl. Phys. Letts., 33 (Oct. 1978), 751.
`Celler et al., J. Appl. Phys., 50 (1979), 7264.
`
`Bomkeet al., Appl. Phys. Letts., 33 (1978), 955.
`E G & G Data Sheet, F1008 C-4, DC Krypton Arc
`Discharge Tube.
`Van Gutfeld, IBM Tech. Discl. Bulletin, 19 (1977),
`3955.
`Gat et al., Appl. Phys. Letts. 33 (1978), 389.
`
`Primary Examiner--Upendra Roy
`Attorney, Agent, or Firm—Flehr, Hohbach,Test,
`Albritton & Herbert
`.
`‘ABSTRACT
`[57]
`Apparatus for annealing semiconductor wafers includes
`a support for receiving the wafers andresistive heaters
`for heating the wafers by thermal conduction through
`the support or by convection. A high intensity arc lamp
`scans the heated wafers thereby raising the temperature
`sufficiently for heat treating. The process is simple,
`rapid, efficient, and does not create damaging thermal
`stresses in the wafers. The high temperature and short
`time treatment enables material properties unobtainable
`with conventional thermal processes.
`
`6 Claims, 3 Drawing Figures
`
`
`
`-~~-—AS IMPLANTED
`° © © © LAMP ANNEALED
`
`1000 °C 30 MIN.
`
`
`
`
`B00.
`
`1600
`
`2400
`
`3200
`
`4000
`
`4800
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`5600
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`
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`ARSENICCONCENTRATIONATOM/cm3
`
`
`
`
`
`DEPTH (A)
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`Page | of 5
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`Samsung Exhibit 1020
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`Page 1 of 5
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`Samsung Exhibit 1020
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`

`

`U.S. Patent May 25, 1982
`
`Sheet 1 of 2
`
`4,331,485
`
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`Page 2 of 5
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`Page 2 of 5
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`

`

`U.S. Patent May 25, 1982
`
`Sheet 2 of 2
`
`4,331,485
`
`
`
`ARSENICCONCENTRATIONATOM/cm3
`
`
`
`
`
`-~~-——AS IMPLANTED
`© © © © LAMP ANNEALED
`1000 °C 30 MIN.
`
`107!
`
`102°
`
`io!
`
`io!
`
`iol?
`
`iol®
`
`
`800
`1600.
`2400
`3200.
`4000.
`4800.
`5600
`DEPTH (A)
`
`FIG—3
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`Page 3 of 5
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`Page 3 of 5
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`

`

`1
`
`4,331,485
`
`METHOD FOR HEAT TREATING
`SEMICONDUCTOR MATERIAL USING HIGH
`INTENSITY CW LAMPS
`
`25
`
`30
`
`35
`
`This invention relates generally to semiconductor
`technology, and moreparticularly the invention relates
`to heat treating of semiconductor wafers.
`Electronic devices are formedin a singlecrystal semi-
`conductor wafers by the selective introduction of dop-
`ant atomsinto the lattice structure of the semiconductor
`material. Group III elements of the periodic table, such
`as boron and gallium, when diffused or implanted into
`the semiconductorlattice structure render the semicon-
`ductor material P typesince these elements are accept-
`ers of electrons in the atomic valence bandsofthe ele-
`ments. Group V elements of the period table, such as
`phosphorous and arsenic, when introduced into.
`the
`semiconductorlatticestructure render the semiconduc-
`tor material N type since the elements are donors of 20
`electrons from the valence bands of the atoms.
`. The dopant. atoms can be introduced into the semi-
`conductor material by diffusion from a dopant atmo-
`sphere in a diffusion furnace or by ion implantation in
`which charged dopantions are driven into the semicon-
`ductor material by a particle accelerator. Particularly in
`ion implanted semiconductor material
`lattice defects
`result and require thermal annealing to properly orient
`the dopant atomsin the lattice structure.
`Additionally, polycrystalline silicon is heat ‘treated by
`a furnace or by laser scanning and the like to increase
`crystal grain size and also to activate dopants in the
`polysilicon.
`Heretofore, thermal annealing of semiconductor ma-
`terial has been effected in a furriace with temperature
`cycled to 700° C.-1100° C. to effect activation of the
`implanted ions in the semiconductor lattice or to in-
`crease grain size in polycrystalline material. This proce-
`dure is time consuming and results in a diffusion or
`migration of the dopant atoms with decreasing perfor-
`mance of the. semiconductor product.
`Morerecently, laser annealing has been introduced.
`Laser annealing allows nearly instantaneous heating and
`cooling of the semiconductor material. with reduced
`dopant ion migration within the semiconductorlattice
`structure. However, because of the small-beam of the
`laser, considerable time is necessary for the total scan-
`ning of the semiconductor wafer. Moreover,
`laser
`equipment is expensive and :very inefficient in power
`usage. Further,
`laser annealing equipment as well as
`annealing furnaces require considerable space in the
`clean room atmosphere of a semiconductor production
`area.
`’ Thermally assisted flash‘annealing using high inten-
`‘sity xenon flash lamps has been proposed. However, the
`short pulses of incoherent light induce a very short
`temperaturerise in the material. To observe any anneal-
`ing effect, the sample must be heated considerably (ap-
`proximately 600° C.). Also since the energy discharged
`into the lamp is limited, only very small areas (e.g.
`1
`cm X 1 cm) can be annealed. The resultant material was
`reported to contain defects ina concentration thatindi-
`cates incomplete annealing. Hot. filament ribbons ‘have
`been proposed. This schemeis intended to.be used for
`the production. of silicon. which is deposited on a sub-
`strate for solar. cell usage.:In this application it is in-
`tended to melt the amorphoussilicon with a hot tung-
`sten filament andlet this molten silicon cool down and
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`Page 4 of 5
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`2
`recrystallize. All the apparatus has to be in vacuum to
`inhibit the oxidation of the hot filament. Because of the
`vacuum no preheating of the material is proposed and
`therefore the large gradient between the molten surface
`of the substrate may include strain and stress in the
`material.
`Accordingly, an object of the present invention is an
`improved methodofheat treating semiconductor mate-
`rial.
`Another object of the invention is apparatus for
`quickly annealing doped and undoped semiconductor
`material.
`Still another object of the invention is apparatus
`which is relatively simple and inexpensive and which
`requireslittle space in a semiconductor manufacturing
`facility.
`Briefly, in accordance with the invention a supportis
`provided for holding a’semiconductor wafer for heat
`treatment. The support includes heater means for heat-
`ing the wafer to an elevated temperature below the
`temperature for heat treatment and below a tempera-
`ture which causes migration of dopant atoms in the
`semiconductorlattice structure. A high intensity inco-
`herent CW light source is positionable with respect to
`the support for irradiation of a semiconductor body
`held on the support. Means can be provided for varying
`the spacing between the light source and the support,
`and means is provided for effecting relative motion
`between the light source and the support whereby the
`surface of the wafer can be scannedbythelight source.
`Meansis provided to controlthelight intensity by vary-
`ing the current through the lamp.
`Preferably, the high intensity light source comprises a
`CWarc discharge tube ofsufficient length to scan the
`entire width of a semiconductor body. The support
`preferably includes a vacuum chuck for holding a semi-
`conductor wafer, and resistive heater means are embed-
`ded in the support for heating of the wafer by thermal
`conduction through the support.
`In another embodimentofthe invention,the substrate
`is placedon isolated pins but close to the heater surface.
`The semiconductor material
`is heated to the heater
`temperature. Whenthe lampis scanning, the waferis far
`enough from the heater so that its temperature can rise
`quickly and independently of the chuck temperature
`throughout because of heat conduction. This reduces
`thermal gradients and facilitates the increase in temper-
`ature for a given light intensity.
`In annealing a semiconductor wafer and thelike, the
`high intensity light source is scanned across the surface
`of the wafer at a speed determined by the spacing be-
`tween the light source and wafer and bythe particular
`temperature desired for annealing the semiconductor
`material and the preheated temperature of the wafer.
`Thus, a semiconductor wafer can be annealed in a mat-
`ter of seconds thereby increasing the throughput of
`annéaled semiconductor material and without introduc-
`ing residual stresses in the annealed wafer and without
`causing dopant migration. Moreover, polycrystalline
`silicon is readily recrystallized with increased crystal
`size.
`
`Theinvention and objects and features thereof will be
`more. readily apparent from the followingdetailed de-
`scription andappended claims when taken with the
`drawing, in which:
`FIG. 1 is a perspective view of one embodiment of
`apparatus in accordance with the invention.
`
`
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`Page 4 of 5
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`4,331,485
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`20
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`30
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`4
`3
`FIG. 2 is a perspective view of another embodiment
`present invention does not alter the dopant concentra-
`ofapparatus in accordance with the invention,
`tion profile. Prior:to’ annealing all wafers had sheet
`resistivity of 3100 ohms per square. After conventional
`FIG. 3 isa plot of dopant concentration of three
`annealing, one wafer had sheetresistivity of 150 ohms
`wafers as implanted after conventional thermal anneal-
`ing and after processing in accordance with the present
`per square, while the scanned wafer had sheet resistivity
`invention.
`of 168 ohmsper square. The difference stems from the
`fact that the thermal annealing profile is more diffused
`In the drawing, a semiconductor waferto be annealed’
`and hasslightly higher average mobility. In both cases
`is placed on a support pedestal8 within housing 10 and
`positioned by means of a chuck 12 through a vacuum
`all the dopants are active and contribute to the electrical
`conductivity of the crystal.
`line 14. The support8 is a heat conductive material such
`The annealing or heat treating of semiconductor wa-
`as brass with a graphite top plate’in which a plurality of
`fers using the apparatus and method in accordance with
`resistive heaters 16 are provided with the resistive heat-
`the present invention has proved to be advantageousin
`ers interconnected with an electrical power source
`initial cost of the equipment, limited space required in
`through lines 18. In one embodimenttheresistive heat-
`ers are CalRods and a sufficient numberof heaters are
`the semiconductor manufacturing facility, and semicon-
`— 5
`
`
`provided whereby the support 8 and a wafer maintained throughput. Also, steeper and_shal-ductor material
`on vacuum chuck 12 can be heated to 500° C. The
`lower
`junctions are achieved meaning potentially
`smaller and faster devices. Also since achievable scan-
`support 8 is vertically moveable by means of lead
`ning temperature ranges are higher than furnace tem-
`screws 20 which are driven by suitable motor driven
`gear train shown generally at 22. Alternatively, support
`peratures larger poly grain can be grown with the
`above method. By preheating the semiconductor wafer
`8 can be madestationary.
`Mounted within housing 10 above pedestal8 is ther-
`throughthe support pedestal prior to the radiation beam
`mal radiation apparatus 30 including a radiant heater 32.
`scanning, deleterious thermal stresses within the semi-
`A concave surface 34 reflects radiant energy down-
`conductor wafer are avoided and the light intensity
`wardly onto the semiconductor body. In a preferred
`needed to raise the semiconductor temperature is re-
`embodiment the radiant heater comprises a CW arc
`duced considerably. The resulting annealed wafers are
`discharge tube such as the dc crypton arc discharge
`high quality. The invention has heat treating applica-
`tube FK-111C-3 available from EG & G. Thetube 32 is
`tions other than annealing and including polycrystalline
`semiconductor regrowth to increase crystal grainsize,
`of sufficient length to irradiate the entire surface of a
`aluminum sintering and grain growth, phosphorous
`semiconductor wafer on a vacuum chuck12 in a single
`scan.
`glass reflow andthelike.
`Thus, while the invention has been described with
`The radiant heater apparatus 30 is moveably mounted
`onapair of horizontal rails 36 and is driven by means of
`reference to a specific embodiment, the. description is
`illustrative of the invention andis not to be construed as
`motor 38 and lead screw 40. Thus, the radiant heater 30
`can be moved from oneside of the housing assembly 10
`limiting the invention. Various modifications and appli-
`cations may occur to those skilled in the art without
`to the other side to thereby scan a wafer on pedestal.8.
`departing from thetrue spirit and scope of the invention
`Alternatively, the radiant heater 30 can be fixed and the
`support 8 movedalongrails.
`as defined by the appended claims.
`Whatis claimedis:
`In annealing a semiconductor wafer in accordance
`with the present
`invention, the current through the
`1. A method ofheat treating a semiconductor bodyat
`radiant heater 32 is selected along with the linear speed
`a high temperature for a short duration comprising the
`of heater assembly 30 whereby the surface of the semi-
`steps of
`conductor wafer is heated to sufficient temperature for
`preheating said semiconductorbodytoa first temper-
`ature, and
`annealing. Normally,
`the annealing temperature for
`radiating a surface of said semiconductor body witha
`silicon semiconductor material will be in the range of
`1200°-1400° C. In some applications higher tempera-
`high intensity CW lamp thereby rapidly heating
`tures and melting can be achieved. Importantly, by
`said radiated surface to. a second temperature
`higherthan said first temperature fora short dura-
`preheating the semiconductor wafer 12 to a tempera-
`tion of time...
`ture of about 500° C. by meansoftheresistive heaters
`2. The method as. defined by claim. 1 and further
`16, excessive thermal stresses in the semiconductor
`wafer are avoided since the temperature rise provided
`including the step of adjusting the spacing between said
`by the radiant heater 30 need be only 700°-900° C.
`semiconductor body and said lamp and the scan speed
`In the embodiment of FIG. 2, a semiconductor wafer
`whereby said semiconductor bodyis heated to a prese-
`50 is supported on a plurality of thermally insulating
`lected temperature by said lamp.
`ceramic posts 52 above the,.vacuum chuck 54. By re-
`3. The method as defined by claim 1 and further -
`versing the air flow in the chuck,uniform heating of the
`including the step of adjusting the power to said lamp
`whereby said semiconductor bodyis heated to a prese-
`waferis facilitated by convection heating. Iii some cases
`convection heating is sufficient and reverse air flow is
`lected temperature by said scanned light source.
`4, The method as defined by claim 1 wherein the step
`not necessary. Thus, as the lamp is scanned across the
`wafer surface, temperature can increase throughout the
`of preheating said semiconductor body includes mount-
`thickness of the wafer and temperature gradients in the
`ing said semiconductor body on a support and heating
`wafer are minimized.
`,
`said support.
`5. The method as defined by claim 1 wherein the step
`FIG. 3 is a plot of dopant concentrations in three
`identical wafers two of which were annealed by con-
`of preheating said semiconductor bodyincludes posi-
`ventional thermal processing and by the scanning pro-
`tioning said body in spaced relationship with respect to
`cess in accordance with the present
`invention. The
`a top surface of a support pedestal wherebysaid bodyis
`dopant profile 60 for the conventionally processed
`heated by convection.
`wafer shows considerable dopant migration during an-
`6. The method as defined by claim 1 wherein said step
`of radiating a surface includes ‘scanning ‘said surface
`nealing as compared to the dopant profile 62 for the
`scanned: .wafer. This profile 62 is identical ‘to the as
`with said lamp.
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`implanted profile 61. meaning that annealing with the
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