IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Patent of:
`
`Lebens et al.
`
`U.S. Patent No.: 6,488,390
`
`
`
`Issue Date:
`
`December 3, 2002
`
`Appl. Serial No.: 09/978,760
`
`Filing Date:
`
`October 16, 2001
`
`Title:
`
`COLOR-ADJUSTED CAMERA LIGHT AND METHOD
`
`
`
`
`
`
`
`PETITION FOR INTER PARTES REVIEW OF UNITED STATES PATENT
`
`NO. 6,488,390 PURSUANT TO 35 U.S.C. §§ 311–319, 37 C.F.R. § 42
`
`
`
`
`
`Exhibit LG-1014
`
`PIC16C62X Microprocessor Data Sheet
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`PIC16C62X
`
`EPROM-Based 8-Bit CMOS Microcontroller
`
`RA1/AN1
`RA0/AN0
`OSC1/CLKIN
`OSC2/CLKOUT
`VDD
`RB7
`RB6
`RB5
`RB4
`
`RA1/AN1
`RA0/AN0
`OSC1/CLKIN
`OSC2/CLKOUT
`VDD
`VDD
`RB7
`RB6
`RB5
`RB4
`
`Pin Diagrams
`
`PDIP, SOIC, Windowed CERDIP
`
`18
`17
`16
`15
`14
`13
`12
`11
`10
`
`20
`19
`18
`17
`16
`15
`14
`13
`12
`11
`
`PIC16C62X
`
`PIC16C62X
`
`•1
` 2
` 3
` 4
` 5
` 6
` 7
` 8
` 9
`
`•1
` 2
` 3
` 4
` 5
` 6
` 7
` 8
` 9
`10
`
`RA2/AN2/VREF
`RA3/AN3
`RA4/T0CKI
`MCLR/VPP
`VSS
`RB0/INT
`RB1
`RB2
`RB3
`
`SSOP
`
`RA2/AN2/VREF
`RA3/AN3
`RA4/T0CKI
`MCLR/VPP
`VSS
`VSS
`RB0/INT
`RB1
`RB2
`RB3RB3
`
`Special Microcontroller Features (cont’d)
`• Programmable code protection
`• Power saving SLEEP mode
`• Selectable oscillator options
`• Serial in-circuit programming (via two pins)
`• Four user programmable ID locations
`CMOS Technology:
`• Low-power, high-speed CMOS EPROM technol-
`ogy
`• Fully static design
`• Wide operating voltage range
`- PIC16C62X - 2.5V to 6.0V
`- PIC16C62XA - 2.5V to 5.5V
`- PIC16CR620A - 2.0V to 5.5V
`• Commercial, industrial and extended tempera-
`ture range
`• Low power consumption
`- < 2.0 mA @ 5.0V, 4.0 MHz
`A typical @ 3.0V, 32 kHz
`- 15
`- < 1.0
`A typical standby current @ 3.0V
`
`Data
`Memory
`80
`96
`96
`80
`96
`128
`128
`
`Devices included in this data sheet:
`Referred to collectively as PIC16C62X .
`• PIC16C620
`• PIC16C620A
`• PIC16C621
`• PIC16C621A
`• PIC16C622
`• PIC16C622A
`• PIC16CR620A
`High Performance RISC CPU:
`• Only 35 instructions to learn
`• All single-cycle instructions (200 ns), except for
`program branches which are two-cycle
`• Operating speed:
`- DC - 20 MHz clock input
`- DC - 200 ns instruction cycle
`Device
`Program
`Memory
`512
`512
`512
`1K
`1K
`2K
`2K
`
`PIC16C620
`PIC16C620A
`PIC16CR620A
`PIC16C621
`PIC16C621A
`PIC16C622
`PIC16C622A
`• Interrupt capability
`• 16 special function hardware registers
`• 8-level deep hardware stack
`• Direct, Indirect and Relative addressing modes
`Peripheral Features:
`• 13 I/O pins with individual direction control
`• High current sink/source for direct LED drive
`• Analog comparator module with:
`- Two analog comparators
`- Programmable on-chip voltage reference
`(V
`) module
`REF
`- Programmable input multiplexing from device
`inputs and internal voltage reference
`- Comparator outputs can be output signals
`• Timer0: 8-bit timer/counter with 8-bit
`programmable prescaler
`Special Microcontroller Features:
`• Power-on Reset (POR)
`• Power-up Timer (PWRT) and Oscillator Start-up
`Timer (OST)
`• Brown-out Reset
`• Watchdog Timer (WDT) with its own on-chip RC
`oscillator for reliable operation
`
` 1998 Microchip Technology Inc.
`
`Preliminary
`
`DS30235G-page 1
`
`Exhibit LG-1014 Page 1
`
`(cid:211)
`m
`m
`

`

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`PIC16C62X
`
`
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`
`
`Device Differences
`
`Device
`
`PIC16C620
`
`PIC16C621
`
`PIC16C622
`
`PIC16C620A
`
`PIC16CR620A
`
`PIC16C621A
`
`PIC16C622A
`
`Voltage
` Range
`
`2.5 - 6.0
`
`2.5 - 6.0
`
`2.5 - 6.0
`
`2.5 - 5.5
`
`2.0 - 5.5
`
`2.5 - 5.5
`
`2.5 - 5.5
`
`Oscillator
`
`See Note 1
`
`See Note 1
`
`See Note 1
`
`See Note 1
`
`See Note 1
`
`See Note 1
`
`See Note 1
`
`Process
`Technology
`(Microns)
`
`0.9
`
`0.9
`
`0.9
`
`0.7
`
`0.7
`
`0.7
`
`0.7
`
`Note 1:
`
`If you change from this device to another device, please verify oscillator characteristics in your application.
`
`DS30235G-page 2
`
`Preliminary
`
` 1998 Microchip Technology Inc.
`
`Exhibit LG-1014 Page 2
`
`(cid:211)
`

`

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`PIC16C62X
`
`Table of Contents
`1.0
`General Description......................................................................................................................................................................5
`2.0
`PIC16C62X Device Varieties .......................................................................................................................................................7
`3.0
`Architectural Overview .................................................................................................................................................................9
`4.0 Memory Organization ................................................................................................................................................................ 13
`5.0
`I/O Ports .................................................................................................................................................................................... 25
`6.0
`Timer0 Module .......................................................................................................................................................................... 31
`7.0
`Comparator Module................................................................................................................................................................... 37
`8.0
`Voltage Reference Module........................................................................................................................................................ 43
`9.0
`Special Features of the CPU..................................................................................................................................................... 45
`10.0 Instruction Set Summary ........................................................................................................................................................... 61
`11.0 Development Support................................................................................................................................................................ 73
`12.0 Electrical Specifications............................................................................................................................................................. 79
`13.0 Device Characterization Information ......................................................................................................................................... 93
`14.0 Packaging Information............................................................................................................................................................... 95
`Appendix A:
` Enhancements.......................................................................................................................................................... 101
`Appendix B:
` Compatibility ............................................................................................................................................................. 101
`Appendix C:
` What’s New............................................................................................................................................................... 102
`Appendix D:
` What’s Changed ....................................................................................................................................................... 102
`Index .................................................................................................................................................................................................. 103
`PIC16C62X Product Identification System ........................................................................................................................................ 107
`
`To Our Valued Customers
`
`Most Current Data Sheet
`To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:
`http://www.microchip.com
`You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
`The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
`Errata
`An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
`workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi-
`sion of silicon and revision of document to which it applies.
`To determine if an errata sheet exists for a particular device, please check with one of the following:
`• Microchip’s Worldwide Web site; http://www.microchip.com
`• Your local Microchip sales office (see last page)
`• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
`When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-
`erature number) you are using.
`Corrections to this Data Sheet
`We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
`that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
`or appears in error, please:
`• Fill out and mail in the reader response form in the back of this data sheet.
`• E-mail us at webmaster@microchip.com.
`We appreciate your assistance in making this a better document.
`
` 1998 Microchip Technology Inc.
`
`Preliminary
`
`DS30235G-page 3
`
`Exhibit LG-1014 Page 3
`
`(cid:211)
`

`

`
`
`
`
`
`
`
`
`
`PIC16C62X
`
`NOTES:
`
`DS30235G-page 4
`
`Preliminary
`
` 1998 Microchip Technology Inc.
`
`Exhibit LG-1014 Page 4
`
`(cid:211)
`

`

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`
`
`GENERAL DESCRIPTION
`1.0
`Pin
`PIC16C62X
`are
`18
`and
`20
`The
`ROM/EPROM-based members of the versatile PICmi-
`cro™ family of low-cost, high-performance, CMOS,
`fully-static, 8-bit microcontrollers.
`All PICmicro™ microcontrollers employ an advanced
`RISC architecture. The PIC16C62X have enhanced
`core features, eight-level deep stack, and multiple inter-
`nal and external interrupt sources. The separate
`instruction and data buses of the Harvard architecture
`allow a 14-bit wide instruction word with the separate
`8-bit wide data. The two-stage instruction pipeline
`allows all instructions to execute in a single-cycle,
`except for program branches (which require two
`cycles). A total of 35 instructions (reduced instruction
`set) are available. Additionally, a large register set gives
`some of the architectural innovations used to achieve a
`very high performance.
`PIC16C62X microcontrollers typically achieve a 2:1
`code compression and a 4:1 speed improvement over
`other 8-bit microcontrollers in their class.
`The PIC16C620A, PIC16C621A and PIC16CR620A
`have 96 bytes of RAM. The PIC16C622(A) has 128
`bytes of RAM. Each device has 13 I/O pins and an 8-bit
`timer/counter with an 8-bit programmable prescaler. In
`addition, the PIC16C62X adds two analog comparators
`with a programmable on-chip voltage reference mod-
`ule. The comparator module is ideally suited for appli-
`cations requiring a low-cost analog interface (e.g.,
`battery chargers, threshold detectors, white goods
`controllers, etc).
`PIC16C62X devices have special features to reduce
`external components, thus reducing system cost,
`enhancing system reliability and reducing power con-
`sumption. There are four oscillator options, of which the
`single pin RC oscillator provides a low-cost solution,
`the LP oscillator minimizes power consumption, XT is a
`standard crystal, and the HS is for High Speed crystals.
`The SLEEP (power-down) mode offers power savings.
`The user can wake up the chip from SLEEP through
`several external and internal interrupts and reset.
`
`PIC16C62X
`
`A highly reliable Watchdog Timer with its own on-chip
`RC oscillator provides protection against software
`lock- up.
`A UV-erasable CERDIP-packaged version is ideal for
`code development while the cost-effective One-Time
`Programmable (OTP) version is suitable for production
`in any volume.
`Table 1-1 shows the features of the PIC16C62X
`mid-range microcontroller families.
`A simplified block diagram of the PIC16C62X is shown
`in Figure 3-1.
`The PIC16C62X series fit perfectly in applications
`ranging from battery chargers to low-power remote
`sensors. The EPROM technology makes customization
`of application programs (detection levels, pulse gener-
`ation, timers, etc.) extremely fast and convenient. The
`small footprint packages make this microcontroller
`series perfect for all applications with space limitations.
`Low-cost, low-power, high-performance, ease of use
`and I/O flexibility make the PIC16C62X very versatile.
`
`Family and Upward Compatibility
`1.1
`Those users familiar with the PIC16C5X family of
`microcontrollers will realize that this is an enhanced
`version of the PIC16C5X architecture. Please refer to
`Appendix A for a detailed list of enhancements. Code
`written for the PIC16C5X can be easily ported to
`PIC16C62X family of devices (Appendix B). The
`PIC16C62X family fills the niche for users wanting to
`migrate up from the PIC16C5X family and not needing
`various peripheral features of other members of the
`PIC16XX mid-range microcontroller family.
`
`Development Support
`1.2
`The PIC16C62X family is supported by a full-featured
`macro assembler, a software simulator, an in-circuit
`emulator, a low-cost development programmer and a
`full-featured programmer. A “C” compiler and fuzzy
`logic support tools are also available.
`
` 1998 Microchip Technology Inc.
`
`Preliminary
`
`DS30235G-page 5
`
`Exhibit LG-1014 Page 5
`
`(cid:211)
`

`

`PIC16C62X
`
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`TABLE 1-1:
`
`PIC16C62X FAMILY OF DEVICES
`
`PIC16C620
`
`PIC16C620A PIC16CR620A PIC16C621
`
`PIC16C621A
`
`PIC16C622
`
`PIC16C622A
`
`Clock
`
`Memory
`
`Peripherals
`
`Features
`
`20
`
`512
`
`80
`TMR0
`2
`Yes
`
`Maximum Frequency
`of Operation (MHz)
`EPROM Program
`Memory
`(x14 words)
`Data Memory (bytes)
`Timer Module(s)
`Comparators(s)
`Internal Reference
`Voltage
`4
`Interrupt Sources
`13
`I/O Pins
`Voltage Range (Volts) 2.5-6.0
`Brown-out Reset
`Yes
`Packages
`18-pin DIP,
`SOIC;
`20-pin SSOP
`
`20
`
`512
`
`96
`TMR0
`2
`Yes
`
`20
`
`512
`
`96
`TMRO
`2
`Yes
`
`20
`
`1K
`
`80
`TMR0
`2
`Yes
`
`20
`
`1K
`
`96
`TMR0
`2
`Yes
`
`20
`
`2K
`
`128
`TMR0
`2
`Yes
`
`20
`
`2K
`
`128
`TMR0
`2
`Yes
`
`4
`13
`3.0-5.5
`Yes
`18-pin DIP,
`SOIC;
`20-pin SSOP
`
`4
`13
`2.5-5.5
`Yes
`18-pin DIP,
`SOIC;
`20-pin SSOP
`
`4
`13
`2.5-6.0
`Yes
`18-pin DIP,
`SOIC;
`20-pin SSOP
`
`4
`13
`3.0-5.5
`Yes
`18-pin DIP,
`SOIC;
`20-pin SSOP
`
`4
`13
`2.5-6.0
`Yes
`18-pin DIP,
`SOIC;
`20-pin SSOP
`
`4
`13
`3.0-5.5
`Yes
`18-pin DIP,
`SOIC;
`20-pin SSOP
`
`All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
`I/O current capability. All PIC16C62X Family devices use serial programming with clock pin RB6 and data pin RB7.
`
`DS30235G-page 6
`
`Preliminary
`
` 1998 Microchip Technology Inc.
`
`Exhibit LG-1014 Page 6
`
`(cid:211)
`

`

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`
`PIC16C62X DEVICE VARIETIES
`2.0
`A variety of frequency ranges and packaging options are
`available. Depending on application and production
`requirements the proper device option can be selected
`using the information in the PIC16C62X Product
`Identification System section at the end of this data
`sheet. When placing orders, please use this page of the
`data sheet to specify the correct part number.
`
`2.1
`
`UV Erasable Devices
`
`The UV erasable version, offered in CERDIP package
`is optimal
`for prototype development and pilot
`programs. This version can be erased and
`reprogrammed to any of the oscillator modes.
`
`and
`PRO MATE
`Microchip's
`PICSTART
`programmers both support programming of
`the
`PIC16C62X.
`
`2.2
`
`One-Time-Programmable (OTP)
`Devices
`
`The availability of OTP devices is especially useful for
`customers who need the flexibility for frequent code
`updates and small volume applications. In addition to
`the program memory, the configuration bits must also
`be programmed.
`
`PIC16C62X
`
`2.3
`
`Quick-Turnaround-Production (QTP)
`Devices
`
`Microchip offers a QTP Programming Service for
`factory production orders. This service
`is made
`available for users who chose not to program a medium
`to high quantity of units and whose code patterns have
`stabilized. The devices are identical to the OTP devices
`but with all EPROM locations and configuration options
`already programmed by the factory. Certain code and
`prototype verification procedures apply before
`production shipments are available. Please contact
`your Microchip Technology sales office for more details.
`
`2.4
`
`Serialized
`Quick-Turnaround-Production
`(SQTP
`) Devices
`SM
`
`Microchip offers a unique programming service where
`a few user-defined locations in each device are
`programmed with different serial numbers. The serial
`numbers may be
`random, pseudo-random or
`sequential.
`Serial programming allows each device to have a
`unique number which can serve as an entry-code,
`password or ID number.
`
` 1998 Microchip Technology Inc.
`
`Preliminary
`
`DS30235G-page 7
`
`Exhibit LG-1014 Page 7
`
`(cid:211)
`(cid:210)
`(cid:210)
`

`

`PIC16C62X
`
`NOTES:
`
`
`
`
`
`
`
`
`
`
`DS30235G-page 8
`
`Preliminary
`
` 1998 Microchip Technology Inc.
`
`Exhibit LG-1014 Page 8
`
`(cid:211)
`

`

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`PIC16C62X
`
`The PIC16C62X devices contain an 8-bit ALU and
`working register. The ALU is a general purpose
`arithmetic unit. It performs arithmetic and Boolean
`functions between data in the working register and any
`register file.
`The ALU is 8-bit wide and capable of addition,
`subtraction, shift and
`logical operations. Unless
`otherwise mentioned, arithmetic operations are two's
`complement in nature. In two-operand instructions,
`typically one operand
`is
`the working
`register
`(W register). The other operand is a file register or an
`immediate constant. In single operand instructions, the
`operand is either the W register or a file register.
`The W register is an 8-bit working register used for ALU
`operations. It is not an addressable register.
`Depending on the instruction executed, the ALU may
`affect the values of the Carry (C), Digit Carry (DC), and
`Zero (Z) bits in the STATUS register. The C and DC bits
`operate as a Borrow and Digit Borrow out bit,
`respectively, bit in subtraction. See the
` and
`SUBLW
` instructions for examples.
`SUBWF
`A simplified block diagram is shown in Figure 3-1, with
`a description of the device pins in Table 3-1.
`
`ARCHITECTURAL OVERVIEW
`3.0
`The high performance of the PIC16C62X family can be
`attributed
`to a number of architectural
`features
`commonly found in RISC microprocessors. To begin
`with, the PIC16C62X uses a Harvard architecture, in
`which, program and data are accessed from separate
`memories using separate busses. This improves
`bandwidth over traditional von Neumann architecture
`where program and data are fetched from the same
`memory. Separating program and data memory further
`allows instructions to be sized differently than 8-bit
`wide data word. Instruction opcodes are 14-bits wide
`making it possible to have all single word instructions.
`A 14-bit wide program memory access bus fetches a
`14-bit instruction in a single cycle. A two-stage pipeline
`overlaps
`fetch and execution of
`instructions.
`Consequently, all instructions (35) execute in a sin-
`gle-cycle (200 ns @ 20 MHz) except for program
`branches.
`The PIC16C620A and PIC16CR620A address 512 x
`14 on-chip program memory. The PIC16C621(A)
`addresses 1K x 14 program memory. The
`PIC16C622(A) addresses 2K x 14 program memory.
`All program memory is internal.
`The PIC16C62X can directly or indirectly address its
`register files or data memory. All special function
`registers including the program counter are mapped in
`the data memory. The PIC16C62X have an orthogonal
`(symmetrical) instruction set that makes it possible to
`carry out any operation on any register using any
`addressing mode. This symmetrical nature and lack of
`‘special optimal situations’ make programming with the
`PIC16C62X simple yet efficient. In addition, the
`learning curve is reduced significantly.
`
` 1998 Microchip Technology Inc.
`
`Preliminary
`
`DS30235G-page 9
`
`Exhibit LG-1014 Page 9
`
`(cid:211)
`

`

`
`
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`
`
`
`
`
`
`
`PIC16C62X
`
`FIGURE 3-1:
`
` BLOCK DIAGRAM
`
`Device
`
`Program Memory
`
`Data Memory
`(RAM)
`
`PIC16C620
`PIC16C620A
`PIC16CR620A
`PIC16C621
`PIC16C621A
`PIC16C622
`PIC16C622A
`
`512 x 14
`512 x 14
`512 x 14
`1K x 14
`1K x 14
`2K x 14
`2K x 14
`
`80 x 8
`96 x 8
`96 x 8
`80 x 8
`96 x 8
`128 x 8
`128 x 8
`
`13
`
`Program Counter
`
`Data Bus
`
`8
`
`Voltage
`Reference
`
`8 Level Stack
`(13-bit)
`
`RAM
`File
`Registers
`
`RA0/AN0
`RA1/AN1
`RA2/AN2/VREF
`RA3/AN3
`
`RA4/T0CKI
`
`PORTB
`
`RAM Addr (1)
`
`9
`
`Addr MUX
`
`Comparator
`
`+-
`
`+-
`
`TMR0
`
`I/O Ports
`
`Indirect
`Addr
`
`8
`
`FSR reg
`
`STATUS reg
`
`3
`
`MUX
`
`ALU
`
`W reg
`
`Direct Addr
`
`7
`
`Power-up
`Timer
`
`Oscillator
`Start-up Timer
`
`Power-on
`Reset
`
`Watchdog
`Timer
`Brown-out
`Reset
`
`MCLR VDD, VSS
`
`EPROM
`
`Program
`Memory
`
`Program
`Bus
`
`14
`
`Instruction reg
`
`Instruction
`Decode &
`Control
`
`Timing
`Generation
`
`OSC1/CLKIN
`OSC2/CLKOUT
`
`Note 1: Higher order bits are from the STATUS register.
`
`DS30235G-page 10
`
`Preliminary
`
` 1998 Microchip Technology Inc.
`
`Exhibit LG-1014 Page 10
`
`(cid:211)
`

`

`TABLE 3-1:
`
`PIC16C62X PINOUT DESCRIPTION
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PIC16C62X
`
`SSOP
`Pin #
`
`I/O/P
`Type
`
`Buffer
`Type
`
`Description
`
`Name
`
`OSC1/CLKIN
`OSC2/CLKOUT
`
`DIP/
`SOIC
`Pin #
`
`16
`15
`
`18
`17
`
`I
`O
`
`ST
`
`ST
`ST
`ST
`ST
`ST
`
`ST/CMOS Oscillator crystal input/external clock source input.
`—
`Oscillator crystal output. Connects to crystal or resonator
`in crystal oscillator mode. In RC mode, OSC2 pin outputs
`CLKOUT which has 1/4 the frequency of OSC1, and
`denotes the instruction cycle rate.
`Master clear (reset) input/programming voltage input.
`This pin is an active low reset to the device.
`PORTA is a bi-directional I/O port.
`Analog comparator input
`Analog comparator input
` output
`Analog comparator input or V
`REF
`Analog comparator input /output
`Can be selected to be the clock input to the Timer0
`timer/counter or a comparator output. Output is open
`drain type.
`PORTB is a bi-directional I/O port. PORTB can be
`software programmed for internal weak pull-up on all
`inputs.
`RB0/INT can also be selected as an external
`interrupt pin.
`
`(1)
`TTL/ST
`
`TTL
`TTL
`TTL
`TTL
`TTL
`(2)
`TTL/ST
`(2)
`TTL/ST
`—
`—
`
`Interrupt on change pin.
`Interrupt on change pin.
`Interrupt on change pin. Serial programming clock.
`Interrupt on change pin. Serial programming data.
`Ground reference for logic and I/O pins.
`Positive supply for logic and I/O pins.
`
`MCLR/V
`PP
`
`4
`
`4
`
`I/P
`
`RA0/AN0
`RA1/AN1
`RA2/AN2/V
`REF
`RA3/AN3
`RA4/T0CKI
`
`RB0/INT
`
`RB1
`RB2
`RB3
`RB4
`RB5
`RB6
`RB7
`V
`SS
`V
`DD
`
`17
`18
`1
`2
`3
`
`6
`
`7
`8
`9
`10
`11
`12
`13
`5
`14
`
`19
`20
`1
`2
`3
`
`7
`
`8
`9
`10
`11
`12
`13
`14
`5,6
`15,16
`
`I/O
`I/O
`I/O
`I/O
`I/O
`
`I/O
`
`I/O
`I/O
`I/O
`I/O
`I/O
`I/O
`I/O
`P
`P
`
`Legend:
`
`O = output
`— = Not used
`TTL = TTL input
`Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
`Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
`
`I/O = input/output
`I = Input
`
`P = power
`ST = Schmitt Trigger input
`
` 1998 Microchip Technology Inc.
`
`Preliminary
`
`DS30235G-page 11
`
`Exhibit LG-1014 Page 11
`
`(cid:211)
`

`

`PIC16C62X
`
`3.1
`
`Clocking Scheme/Instruction Cycle
`
`3.2
`
`Instruction Flow/Pipelining
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The clock input (OSC1/CLKIN pin) is internally divided
`by four to generate four non-overlapping quadrature
`clocks namely Q1, Q2, Q3 and Q4. Internally, the
`program counter (PC) is incremented every Q1, the
`instruction is fetched from the program memory and
`latched
`into
`the
`instruction register
`in Q4. The
`instruction
`is decoded and executed during
`the
`following Q1 through Q4. The clocks and instruction
`execution flow is shown in Figure 3-2.
`
`An “Instruction Cycle” consists of four Q cycles (Q1,
`Q2, Q3 and Q4). The instruction fetch and execute are
`pipelined such that fetch takes one instruction cycle
`while decode and execute takes another instruction
`cycle. However, due to the pipelining, each instruction
`effectively executes in one cycle. If an instruction
`causes the program counter to change (e.g.,
`)
`GOTO
`then two cycles are required to complete the instruction
`(Example 3-1).
`A fetch cycle begins with the program counter (PC)
`incrementing in Q1.
`In the execution cycle, the fetched instruction is latched
`into the “Instruction Register (IR)” in cycle Q1. This
`instruction is then decoded and executed during the
`Q2, Q3, and Q4 cycles. Data memory is read during Q2
`(operand read) and written during Q4 (destination
`write).
`
`FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
`
`Q1
`
`Q2
`
`Q3
`
`Q4
`
`Q1
`
`Q2
`
`Q3
`
`Q4
`
`Q1
`
`Q2
`
`Q3
`
`Q4
`
`OSC1
`Q1
`Q2
`Q3
`Q4
`PC
`OSC2/CLKOUT
`(RC mode)
`
`Internal
`phase
`clock
`
`PC
`
`PC+1
`
`PC+2
`
`Fetch INST (PC)
`Execute INST (PC-1)
`
`Fetch INST (PC+1)
`Execute INST (PC)
`
`Fetch INST (PC+2)
`Execute INST (PC+1)
`
`EXAMPLE 3-1:
`
`INSTRUCTION PIPELINE FLOW
`
`1. MOVLW 55h
`
`2. MOVWF PORTB
`
`3. CALL SUB_1
`
`4. BSF PORTA, BIT3
`
`Fetch 1
`
`Execute 1
`Fetch 2
`
`Execute 2
`Fetch 3
`
`Execute 3
`Fetch 4
`
`Flush
`Fetch SUB_1 Execute SUB_1
`
`All instructions are single cycle, except for any program branches. These take two cycles since the fetch
`instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
`
`DS30235G-page 12
`
`Preliminary
`
` 1998 Microchip Technology Inc.
`
`Exhibit LG-1014 Page 12
`
`(cid:211)
`

`

`4.0 MEMORY ORGANIZATION
`
`FIGURE 4-2:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PIC16C62X
`
`PROGRAM MEMORY MAP
`AND STACK FOR THE
`PIC16C621/PIC16C621A
`
`4.1
`
`Program Memory Organization
`
`The PIC16C62X has a 13-bit program counter capable
`of addressing an 8K x 14 program memory space. Only
`the first 512 x 14
`(0000h
`- 01FFh)
`for
`the
`PIC16C620(A) and PIC16CR620, 1K x 14 (0000h -
`03FFh) for the PIC16C621(A) and 2K x 14 (0000h -
`07FFh) for the PIC16C622(A) are physically imple-
`mented. Accessing a location above these boundaries
`will cause a wrap-around within the first 512 x 14 space
`(PIC16C(R)620(A)) or 1K x 14 space (PIC16C621(A))
`or 2K x 14 space (PIC16C622(A)). The reset vector is
`at 0000h and the interrupt vector is at 0004h
`(Figure 4-1, Figure 4-2, Figure 4-3).
`
`FIGURE 4-1:
`
`PROGRAM MEMORY MAP
`AND STACK FOR THE
`PIC16C620/PIC16C620A/
`PIC16CR620A
`
`PC<12:0>
`
`CALL, RETURN
`RETFIE, RETLW
`
`13
`
`Stack Level 1
`Stack Level 2
`
`Stack Level 8
`
`Reset Vector
`
`000h
`
`Interrupt Vector
`
`On-chip Program
`Memory
`
`0004
`0005
`
`01FFh
`0200h
`
`1FFFh
`
`PC<12:0>
`
`13
`
`CALL, RETURN
`RETFIE, RETLW
`
`Stack Level 1
`Stack Level 2
`
`Stack Level 8
`
`Reset Vector
`
`Interrupt Vector
`
`On-chip Program
`Memory
`
`000h
`
`0004
`0005
`
`03FFh
`0400h
`
`1FFFh
`
`FIGURE 4-3:
`
`PROGRAM MEMORY MAP
`AND STACK FOR THE
`PIC16C622/PIC16C622A
`
`PC<12:0>
`
`13
`
`CALL, RETURN
`RETFIE, RETLW
`
`Stack Level 1
`Stack Level 2
`
`Stack Level 8
`
`Reset Vector
`
`Interrupt Vector
`
`On-chip Program
`Memory
`
`000h
`
`0004
`0005
`
`07FFh
`0800h
`
`1FFFh
`
` 1998 Microchip Technology Inc.
`
`Preliminary
`
`DS30235G-page 13
`
`Exhibit LG-1014 Page 13
`
`(cid:211)
`

`

`PIC16C62X
`
`4.2
`
`Data Memory Organization
`
`4.2.1
`
`GENERAL PURPOSE REGISTER FILE
`
`The register file is organized as 80 x 8 in the
`PIC16C620/621,
`96
`x
`8
`in
`the
`PIC16C620A/621A/CR620A and 128 x 8 in the
`PIC16C622(A). Each is accessed either directly or indi-
`rectly
`through
`the File Select Register FSR
`(Section 4.4).
`
`The data memory (Figure 4-4, Figure 4-5, Figure 4-6 and
`Figure 4-7) is partitioned into two Banks which contain the
`general purpose registers and the special function regis-
`ters. Bank 0 is selected when the RP0 bit is cleared. Bank
`1 is selected when the RP0 bit (STATUS <5>) is set. The
`Special Function Registers are located in the first 32 loca-
`tions of each Bank. Register locations 20-7Fh (Bank0) on
`the PIC16C620A/CR620A/621A and 20-7Fh (Bank0) and
`A0-BFh (Bank1) on the PIC16C622 and PIC16C622A are
`general purpose registers implemented as static RAM.
`Some special purpose registers are mapped in Bank 1.
`Addresses F0h-FFh of bank1 are implemented as common
`ram and mapped back to addresses 70h-7Fh in bank0 on
`the PIC16C620A/CR620A/621A/622A.
`
`DS30235G-page 14
`
`Preliminary
`
` 1998 Microchip Technology Inc.
`
`Exhibit LG-1014 Page 14
`
`(cid:211)
`

`

`PIC16C62X
`
`FIGURE 4-4: DATA MEMORY MAP FOR
`THE PIC16C620/621
`
`FIGURE 4-5: DATA MEMORY MAP FOR
`THE PIC16C622
`
`File
`Address
`
`File
`Address
`
`File
`Address
`
`File
`Address
`
`00h
`01h
`02h
`03h
`04h
`05h
`06h
`07h
`08h
`09h
`0Ah
`0Bh
`0Ch
`0Dh
`0Eh
`0Fh
`10h
`11h
`12h
`13h
`14h
`15h
`16h
`17h
`18h
`19h
`1Ah
`1Bh
`1Ch
`1Dh
`1Eh
`1Fh
`20h
`
`6Fh
`70h
`
`7Fh
`
`INDF(1)
`TMR0
`PCL
`STATUS
`FSR
`PORTA
`PORTB
`
`PCLATH
`INTCON
`PIR1
`
`INDF(1)
`OPTION
`PCL
`STATUS
`FSR
`TRISA
`TRISB
`
`PCLATH
`INTCON
`PIE1
`
`PCON
`
`CMCON
`
`VRCON
`
`General
`Purpose
`Register
`
`80h
`81h
`82h
`83h
`84h
`85h
`86h
`87h
`88h
`89h
`8Ah
`8Bh
`8Ch
`8Dh
`8Eh
`8Fh
`90h
`91h
`92h
`93h
`94h
`95h
`96h
`97h
`98h
`99h
`9Ah
`9Bh
`9Ch
`9Dh
`9Eh
`9Fh
`A0h
`
`00h
`01h
`02h
`03h
`04h
`05h
`06h
`07h
`08h
`09h
`0Ah
`0Bh
`0Ch
`0Dh
`0Eh
`0Fh
`10h
`11h
`12h
`13h
`14h
`15h
`16h
`17h
`18h
`19h
`1Ah
`1Bh
`1Ch
`1Dh
`1Eh
`1Fh
`20h
`
`INDF(1)
`TMR0
`PCL
`STATUS
`FSR
`PORTA
`PORTB
`
`PCLATH
`INTCON
`PIR1
`
`INDF(1)
`OPTION
`PCL
`STATUS
`FSR
`TRISA
`TRISB
`
`PCLATH
`INTCON
`PIE1
`
`PCON
`
`CMCON
`
`VRCON
`
`General
`Purpose
`Register
`
`General
`Purpose
`Register
`
`Bank 0
`
`Bank 1
`
`FFh
`
`7Fh
`
`Bank 0
`
`Bank 1
`
`80h
`81h
`82h
`83h
`84h
`85h
`86h
`87h
`88h
`89h
`8Ah
`8Bh
`8Ch
`8Dh
`8Eh
`8Fh
`90h
`91h
`92h
`93h
`94h
`95h
`96h
`97h
`98h
`99h
`9Ah
`9Bh
`9Ch
`9Dh
`9Eh
`9Fh
`A0h
`
`BFh
`C0h
`
`FFh
`
` Unimplemented data memory locations, read as '0'.
`Note 1: Not a physical register.
`
` Unimplemented data memory locations, read as '0'.
`Note 1: Not a physical register.
`
` 1998 Microchip Technology Inc.
`
`Preliminary
`
`DS30235G-page 15
`
`Exhibit LG-1014 Page 15
`
`(cid:211)
`

`

`PIC16C62X
`
`FIGURE 4-6: DATA MEMORY MAP FOR THE
`PIC16C620A/
`CR620A/621A
`
`File
`Address
`
`File
`Address
`
`00h
`01h
`02h
`03h
`04h
`05h
`06h
`07h
`08h
`09h
`0Ah
`0Bh
`0Ch
`0Dh
`0Eh
`0Fh
`10h
`11h
`12h
`13h
`14h
`15h
`16h
`17h
`18h
`19h
`1Ah
`1Bh
`1Ch
`1Dh
`1Eh
`1Fh
`20h
`
`6Fh
`70h
`
`7Fh
`
`INDF(1)
`TMR0
`PCL
`STATUS
`FSR
`PORTA
`PORTB
`
`PCLATH
`INTCON
`PIR1
`
`INDF(1)
`OPTION
`PCL
`STATUS
`FSR
`TRISA
`TRISB
`
`PCLATH
`INTCON
`PIE1
`
`PCON
`
`CMCON
`
`VRCON
`
`General
`Purpose
`Register
`
`Accesses
`70h-7Fh
`
`Bank 0
`
`Bank 1
`
`80h
`81h
`82h
`83h
`84h
`85h
`86h
`87h
`88h
`89h
`8Ah
`8Bh
`8Ch
`8Dh
`8Eh
`8Fh
`90h
`91h
`92h
`93h
`94h
`95h
`96h
`97h
`98h
`99h
`9Ah
`9Bh
`9Ch
`9Dh
`9Eh
`9Fh
`A0h
`
`F0h
`
`FFh
`
` Unimplemented data memory locations, read as '0'.
`Note 1: Not a physical register.
`
`FIGURE 4-7: DATA MEMORY MAP FOR
`THE PIC16C622A
`
`File
`Address
`
`File
`Address
`
`00h
`01h
`02h
`03h
`04h
`05h
`06h
`07h
`08h
`09h
`0Ah
`0Bh
`0Ch
`0Dh
`0Eh
`0Fh
`10h
`11h
`12h
`13h
`14h
`15h
`16h
`17h
`18h
`19h
`1Ah
`1Bh
`1Ch
`1Dh
`1Eh
`1Fh
`20h
`
`6Fh
`70h
`
`7Fh
`
`INDF(1)
`TMR0
`PCL
`STATUS
`FSR
`PORTA
`PORTB
`
`PCLATH
`INTCON
`PIR1
`
`INDF(1)
`OPTION
`PCL
`STATUS
`FSR
`TRISA
`TRISB
`
`PCLATH
`INTCON
`PIE1
`
`PCON
`
`CMCON
`
`VRCON
`
`General
`Purpose
`Register
`
`General
`Purpose
`Register
`
`Accesses
`70h-7Fh
`
`Bank 0
`
`Bank 1
`
`80h
`81h
`82h
`83h
`84h
`85h
`86h
`87h
`88h
`89h
`8Ah
`8Bh
`8Ch
`8Dh
`8Eh
`8Fh
`90h
`91h
`92h
`93h
`94h
`95h
`96h
`97h
`98h
`99h
`9Ah
`9Bh
`9Ch
`9Dh
`9Eh
`9Fh
`A0h
`
`BFh
`C0h
`
`F0h
`
`FFh
`
` Unimplemented data memory locations, read as '0'.
`Note 1: Not a physical register.
`
`DS30235G-page 16
`
`Preliminary
`
` 1998 Microchip Technology Inc.
`
`Exhibit LG-1014 Page 16
`
`(cid:211)
`

`

`PIC16C62X
`
`4.2.2
`
`SPECIAL FUNCTION REGISTERS
`
`The special function registers are registers used by the
`CPU and Peripheral functions for controlling the
`desired operation of the device (Table 4-1). These
`registers are static RAM.
`
`The special registers can be classified into two sets
`(core and peripheral). The special function registers
`associated with the “core” functions are described in
`this section. Those related to the operation of the
`peripheral features are described in the section of that
`peripheral feature.
`
`TABLE 4-1:
`
`SPECIAL REGISTERS FOR THE PIC16C62X
`
`Address Name
`
`Bit 7
`
`Bit 6
`
`Bit 5
`
`Bit 4
`
`Bit 3
`
`Bit 2
`
`Bit 1
`
`Bit 0
`
`Value on
`POR Reset
`
`Value on all
`other
`resets(1)
`
`xxxx xxxx
`
`xxxx xxxx
`
`xxxx xxxx
`
`uuuu uuuu
`
`0000 0000
`
`0000 0000
`
`0001 1xxx
`
`000q quuu
`
`xxxx xxxx
`
`uuuu uuuu
`
`---x 0000
`
`---u 0000
`
`xxxx xxxx
`
`uuuu uuuu
`
`—
`
`—
`
`—
`
`—
`
`—
`
`—
`
`Bank 0
`
`00h
`
`01h
`02h
`
`03h
`
`INDF
`
`TMR0
`PCL
`
`STATUS
`
`FSR
`04h
`PORTA
`05h
`PORTB
`06h
`Unimplemented
`07h
`Unimplemented
`08h
`Unimplemented
`09h
`PCLATH
`0Ah
`INTCON
`0Bh
`PIR1
`0Ch
`0Dh-1Eh Unimplemented
`1Fh
`CMCON
`
`Addressing this location uses contents of FSR to address data memory (not a physical
`register)
`Timer0 Module’s Register
`Program Counter's (PC) Least Significant Byte
`IRP(2)
`RP1(2)
`Indirect data memory address pointer
`—
`—
`—
`RA4
`RB7
`RB6
`RB5
`RB4
`
`RP0
`
`TO
`
`PD
`
`Z
`
`DC
`
`C
`
`RA3
`RB3
`
`RA2
`RB2
`
`RA1
`RB1
`
`RA0
`RB0
`
`—
`GIE
`—
`
`—
`PEIE
`CMIF
`
`—
`T0IE
`—
`
`Write buffer for upper 5 bits of program counter
`INTE
`RBIE
`T0IF
`INTF
`RBIF
`—
`—
`—
`—
`—
`
`---0 0000
`
`---0 0000
`
`0000 000x
`
`0000 000u
`
`-0-- ----
`
`-0-- ----
`
`C2OUT
`
`C1OUT
`
`CM1
`
`CM0
`
`00-- 0000
`
`00-- 0000
`
`—
`
`—
`
`Addressing this location uses contents of FSR to address data memory (not a physical
`register)
`T0SE
`T0CS
`INTEDG
`RBPU
`Program Counter's (PC) Least Significant Byte
`IRP(2)
`RP1(2)
`Indirect data memory address pointer
`—
`—
`—
`TRISA4
`TRISB7
`TRISB6
`TRISB5
`TRISB4
`
`TRISA3
`TRISB3
`
`TRISA2
`TRISB2
`
`FSR
`84h
`TRISA
`85h
`TRISB
`86h
`Unimplemented
`87h
`Unimplemented
`88h
`Unimplemented
`89h
`PCLATH
`8Ah
`INTCON
`8Bh
`PIE1
`8Ch
`Unimplemented
`8Dh
`PCON
`8Eh
`8Fh-9Eh Unimplemented
`VRR
`VROE
`VREN
`9Fh
`VRCON
`VR0
`VR1
`VR2
`VR3
`—
`000- 0000
`000- 0000
`Legend: — = Unimplemented locations read as ‘0’, u = unchanged,