`________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________
`
`INTEL CORPORATION,
`
`Petitioner,
`
`v.
`
`ALACRITECH INC.,
`
`Patent Owner
`________________
`
`Case IPR2017-01713
`U.S. Patent 7,337,241
`________________
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 35 U.S.C. § 313 AND 37 C.F.R. § 42.107
`
`
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`U.S. Patent No. 7,337,241
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` Case No. IPR2017-01713
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`TABLE OF CONTENTS
`
`Page
`
`I.
`II.
`
`V.
`
`INTRODUCTION.................................................................................1
`OVERVIEW OF THE ‘241 PATENT ..................................................4
`A.
`The ‘241 Patent Specification.....................................................4
`B.
`The ‘241 Patent Claims...............................................................9
`PROSECUTION HISTORY OF THE ‘241 PATENT ...................... 14
`III.
`IV. OVERVIEW OF THE ASSERTED PRIOR ART............................. 16
`A.
`U.S. Patent No. 5,937,169 (“Connery”)................................... 17
`B.
`Dr. Min Testified He Had “No Opinion” on the Prior Art ...... 18
`CLAIM CONSTRUCTION ............................................................... 19
`A.
`Intel’s Petition Should Be Denied Because It Alleges The
`Challenged Claims Are Indefinite............................................ 20
`“[first/second] mechanism” (claim 17).................................... 21
`B.
`“without an interrupt dividing” (claim 17) .............................. 23
`C.
`“prepending” (claim 17)........................................................... 25
`D.
`VI. CONNERY, WHICH IS THE SOLE GROUND FOR THE
`PETITION, IS NOT PRIOR ART TO THE CHALLENGED
`CLAIMS ............................................................................................. 26
`A.
`All Claims of The ‘241 Patent Are Fully Supported By
`The Provisional Application, and Therefore Connery is
`Not Prior Art............................................................................. 26
`1.
`Prepending headers to segments.................................... 28
`2.
`Prepending at one time as a sequence of bits ................ 32
`3. Without an interrupt dividing the prepending ............... 33
`VII. THE BOARD SHOULD DENY THE PETITION BECAUSE
`IT FAILS TO DISCLOSE ALL REAL PARTIES IN
`INTEREST ......................................................................................... 35
`A.
`Intel Effectively Controls Dell................................................. 36
`B.
`The Relationship Between Intel and Dell is Sufficiently
`Close......................................................................................... 38
`Dell Desires Review of the ‘241 Patent................................... 40
`
`C.
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`E.
`
`F.
`
`D.
`
`Intel and Dell Have Coordinated Interest and Action in
`Challenging the ‘241 Patent..................................................... 41
`Intel Has Effective Choice as to the Legal Theories and
`Proofs of Dell and Cavium....................................................... 42
`Finding Dell and Cavium Are Real Parties in Interest Is
`Consistent with Legislative Intent............................................ 43
`VIII. THE BOARD SHOULD DECLINE INSTITUTION UNDER
`35 U.S.C. § 325(D) BECAUSE ALL THE PRIOR ART HAS
`ALREADY BEEN CONSIDERED BY THE OFFICE..................... 44
`IX. CONCLUSION .................................................................................. 46
`
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`TABLE OF AUTHORITIES
`
`Cases
`Apple Inc. v. Immersion Corp.,
`Case IPR2016-01372, Paper 7 (Jan. 11, 2017) ..................................... 3, 20
`Ariad Pharm., Inc. v. Eli Lilly & Co.,
`598 F.3d 1336 (Fed. Cir. 2010)................................................................ 27
`Benson & Ford, Inc. v. Wanda Petroleum Co.,
`833 F.2d 1172 (5th Cir. 1987).................................................................. 39
`Cox Commc’ns, Inc. v. Sprint Commc’n Co. LP,
`838 F.3d 1224 (Fed. Cir. 2016)................................................................ 22
`In re Herschler,
`591 F.2d 693 (CCPA 1979)...................................................................... 28
`In re Kaslow,
`707 F.2d 1366 (Fed. Cir. 1983)................................................................ 28
`LizardTech, Inc. v. Earth Res. Mapping, Inc.,
`424 F.3d 1336 (Fed. Cir. 2005)................................................................ 27
`Nautilus, Inc. v. Biosig Instruments, Inc.,
`134 S. Ct. 2120 (2014) ............................................................................. 25
`Oil States Energy Servs. LLC v. Greene’s Energy Group, LLC,
`Case No. 16-712, certiorari granted (U.S. Jun. 12, 2017)............ 4, 45, 46
`Space Exploration Technologies Corp. v. Blue Origin LLC,
`Case IPR2014-01378, Paper 6 (Mar. 3, 2015)...................................... 3, 20
`Vas-Cath, Inc. v. Mahurkar,
`935 F.2d 1555 (Fed. Cir. 1991)................................................................ 27
`Williamson v. Citrix Online, LLC,
`792 F.3d 1339 (Fed. Cir. 2015).......................................................... 21, 22
`Statutory Authorities
`35 U.S.C. § 102......................................................................................... 3, 20
`35 U.S.C. § 103(a) .......................................................................................... 1
`35 U.S.C. § 112......................................................................................... 3, 21
`35 U.S.C. § 112(6) ........................................................................................ 20
`35 U.S.C. § 312(a)(2).................................................................................... 35
`35 U.S.C. § 313............................................................................................... 1
`35 U.S.C. § 314............................................................................................... 4
`35 U.S.C. § 314(a) .................................................................................. 26, 46
`35 U.S.C. § 316(e) .................................................................................. 26, 27
`35 U.S.C. § 325(D) ................................................................................. 44, 45
`
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`Rules and Regulations
`37 C.F.R. § 42.6(e) ....................................................................................... 49
`37 C.F.R. § 42.24.......................................................................................... 48
`37 C.F.R. § 42.24(a)(i).................................................................................. 48
`37 C.F.R. § 42.100(b)................................................................................... 19
`37 C.F.R. § 42.107(a) ..................................................................................... 1
`37 C.F.R. § 42.108.......................................................................................... 4
`37 CFR § 42.8(b)(1) ..................................................................................... 35
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48.................................... 26
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48756, 48759-60
`(Aug. 14, 2012).................................................................................... 36, 37
`Legislative Materials
`157 Cong. Rec. S1034, S1041 (Mar. 1, 2011)........................................ 43, 44
`Additional Authorities
`U.S. Patent No. 5,937,169 .................................................................... 1, 2, 17
`U.S. Patent No. 7,337,241(Ex. 1001............................................................... 1
`
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`PATENT OWNER’S LIST OF EXHIBITS
`
`Declaration of Paul Prucnal, Ph.D.
`
`Intel Corporation’s Motion to Intervene, Case No. 2:16-
`cv-00693-JRG-RSP, Dkt. 71 (E.D. Tex., Oct. 31, 2016)
`
`Declaration of Christopher Kyriacou, Case No. 2:16-cv-
`00693-JRG-RSP, Dkt. 71-5 (E.D. Tex., Oct. 31, 2016)
`
`Jonathan Corbet; Alessandro Rubini; Greg Kroah-
`Hartman (2005), Linux Device Drivers, 3rd edition,
`Chapter 10, “Interrupt Handling”
`
`Defendant Dell Inc.’s First Supplemental Responses to
`Plaintiff’s Second Set of Common Interrogatories to
`Defendants and Intervenors (No. 11)
`
`Memorandum Opinion and Order on Claim
`Construction, Case No. 2:16-cv-00693-JRG-RSP, Dkt.
`362 (E.D. Tex., September 21, 2017)
`
`Declaration of Garland Stephens, Case No. 2:16-cv-
`00693-JRG-RSP, Dkt. 71-2 (E.D. Tex., Oct. 31, 2016)
`
`Excerpts of Declaration of Mr. Mark R. Lanning
`Regarding Claim Construction, Case No. 2:16-cv-00693-
`JRG-RSP, Dkt. 303-5 (E.D. Tex. Jul. 6, 2017)
`
`Cavium’s Motion to Intervene, Case No. 2:16-cv-00693-
`JRG-RSP, Dkt. 109 (E.D. Tex., Jan. 13. 2017)
`
`Ex. 2001
`
`Ex. 2002
`
`Ex. 2003
`
`Ex. 2004
`
`Ex. 2005
`
`Ex. 2006
`
`Ex. 2007
`
`Ex. 2008
`
`Ex. 2009
`
`Ex. 2010
`
`Curriculum Vitae of Paul Prucnal, Ph.D.
`
`v
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`U.S. Patent No. 7,337,241
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`I.
`
`INTRODUCTION
`
`Pursuant to 35 U.S.C. § 313 and 37 C.F.R. § 42.107(a), Patent Owner
`
`Alacritech Inc. (“Alacritech”) submits this Preliminary Response to the Petition for
`
`Inter Partes Review (“the Petition”) filed in this matter. Petitioner Intel
`
`Corporation (“Intel”) seeks Inter Partes Review (“IPR”) of claims 9-15, 17, and
`
`19-21 of U.S. Patent No. 7,337,241 (Ex. 1001, “the ‘241 patent”), as allegedly
`
`being unpatentable under 35 U.S.C. § 103(a) in view of U.S. Patent No. 5,937,169
`
`to Connery et al. (Ex. 1043, “Connery”). The ‘241 patent is assigned to Alacritech
`
`and is the subject of co-pending litigation, Alacritech, Inc. v. CenturyLink, Inc.,
`
`2:16-cv-00693-JRG-RSP (E.D. Tex.); Alacritech, Inc. v. Wistron Corp., 2:16-cv-
`
`00692-JRG-RSP (E.D. Tex.); and Alacritech, Inc. v. Dell Inc., 2:16-cv-00695-
`
`RWS-RSP (E.D. Tex.), which were all consolidated for pre-trial purposes (“the
`
`Litigation”).
`
`The ‘241 patent is directed to accelerated network processing using an
`
`“intelligent” network interface card (INIC). Through a series of novel
`
`improvements over traditional network interface cards, the claimed invention is
`
`able to reduce (or completely eliminate) the number of times the host CPU is
`
`interrupted when preparing new packets to be transmitted or processing received
`
`packets. As explained in more detail below, by relieving the host CPU of frequent
`
`and debilitating interrupts, the claimed invention provides enhanced network and
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`system performance, faster data throughput, increased system stability, and an
`
`overall better user experience.
`
`In its Petition,1 Intel asserts that the ‘241 patent is invalid on only one
`
`ground: that claims 9-15, 17, and 19-21 of the ‘241 patent are obvious over U.S.
`
`Patent No. 5,937,169 to Connery et al. (“Connery”) (Ex. 1043). As set forth
`
`below, Intel’s Petition is deficient on numerous grounds; thus, the Board should
`
`not institute this IPR on the ground enumerated in the Petition.
`
`First, Petitioner has not established that Connery is prior art to the ‘241
`
`patent. As acknowledged in Intel’s Petition, the ‘241 patent claims priority to U.S.
`
`Provisional Application No. 60/061,809, filed October 14, 1997 (“the ‘241
`
`Provisional”). (Petition at 35.) Connery, in contrast, was filed on October 29,
`
`1997—some fifteen days later—and does not claim the benefit of any earlier-filed
`
`applications. (Ex. 1043.) Connery therefore does not constitute prior art. As
`
`described in more detail below, Petitioner’s arguments regarding the written
`
`description of the ‘241 Provisional consist exclusively of conclusory attorney
`
`argument and are unpersuasive.
`
`Second, Connery was already considered by the Office during the original
`
`prosecution of the ‘241 patent. This Petition is therefore merely cumulative of the
`
`1 As noted in Intel’s “Statement of Non-Redundancy,” this is Intel’s second
`
`petition against the ‘241 patent. (Petition at 15.)
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`2
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`arguments already considered and rejected by the Office in initial examination.
`
`The Board should not second guess the Examiner and substitute its own opinion
`
`for that of the original Examiner.
`
`Third, Petitioner alleges certain claim terms and phrases are indefinite
`
`because they are either (1) governed by 35 U.S.C. § 112 ¶ 6 and not adequately
`
`defined in the specificaiton or (2) incapable of being understood by a person of
`
`ordinary skill in the art (“POSA”). Because under Petitioner’s own contention
`
`these terms are indefinite, Petition’s obviousness challenges cannot be sustained in
`
`this Petition. See Space Exploration Technologies Corp. v. Blue Origin LLC, Case
`
`IPR2014-01378, Paper 6, at 8-9 (Mar. 3, 2015) (“inter partes review is limited to
`
`grounds of anticipation and obviousness under 35 U.S.C. §§ 102 and 103, not
`
`indefiniteness under 35 U.S.C. § 112”); Apple Inc. v. Immersion Corp., Case
`
`IPR2016-01372, Paper 7, at 20-21 (Jan. 11, 2017) (where Board is “unable to
`
`determine the scope and meaning of [the challenged] claims . . . we cannot conduct
`
`the necessary factual inquiry for determining obviousness with respect to these
`
`claims, such as ascertaining differences between the claimed subject matter and the
`
`prior art”).
`
`Fourth, Petitioners have failed to name all real parties in interest. For the
`
`reasons discussed below, both Dell and Cavium are unnamed real parties in interest
`
`to this Petition. (See infra § VI.) Because this threshold requirement has not been
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`met, the Board should deny institution.
`
`Accordingly, the Connery reference and Intel’s arguments in the Petition do
`
`not give rise to a reasonable likelihood that Intel will prevail with respect to any
`
`challenged claim of the ‘241 patent. The Board should therefore not institute
`
`review on any claim of the ‘241 patent.2 See 35 U.S.C. § 314; 37 C.F.R. § 42.108.
`
`II. OVERVIEW OF THE ‘241 PATENT
`
`A.
`
`The ‘241 Patent Specification
`
`The ‘241 patent describes a novel system for accelerating network
`
`processing. An intelligent network interface card (INIC) communicates with a
`
`host computer. The INIC provides “a fast-path that avoids protocol processing for
`
`most large multi-packet messages, greatly accelerating data communication.” (Ex.
`
`1001 at Abstract.) In some embodiments, the INIC “contains specialized hardware
`
`circuits that are much faster at their specific tasks than a general purpose CPU.”
`
`(Id.)
`
`As explained in the background of the ‘241 patent, when a conventional
`
`network interface card prepares to send data from a first host to a second host,
`
`“some control data is added at each layer of the first host regarding the protocol of
`
`
`2 Alacritech also respectfully reserves its rights under the Oil States case pending
`
`before the United States Supreme Court, as set forth in Section IX of this
`
`Preliminary Response.
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`that layer, the control data being indistinguishable from the original (payload) data
`
`for all lower layers of that host.” (Id. at 3:67-4:3.) For example, an application
`
`layer attaches an application layer header to the payload data and sends the
`
`combined data to the presentation layer of the sending host, which receives the
`
`combined data, operates on it and adds a presentation layer header to the data,
`
`resulting in another combined data packet. The data resulting from combining the
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`payload data, application layer header, and presentation layer header is then passed
`
`to the session layer, which performs required operations including attaching a
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`session layer header to the data and presenting the resulting combination of data to
`
`the transport layer. This process continues as the information moves to lower
`
`layers, with a transport layer header, network layer header, and data link layer
`
`header and trailer attached to the data at each of those layers, with each step
`
`typically including data moving and copying, before sending the data as bit packets
`
`over the network to the second host. (Id. at 4:4-20.)
`
`This process of adding a layer header to the data from the preceding layer is
`
`sometimes referred to as “encapsulation” because the data and layer header is
`
`treated as the data for the immediately following layer, which, in turn, adds its own
`
`layer header to the data from the preceding layer. (Ex. 2001 at ¶¶ 66-67.) Each
`
`layer is generally not aware of which portion of the data from the preceding layer
`
`constitutes the layer header or the user data; as such, each layer treats the data it
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`receives from the preceding layer as some generic payload. (Id.)
`
`(Ex. 1008, Stevens at .034, Figure 1.4 (adapted from Petition at 1).)
`
`On the receiving side, the receiving host generally performs the reverse of
`
`the sending process, beginning with receiving the bits from the network. Headers
`
`are removed, one at a time, and the received data is processed, in order, from the
`
`lowest (physical) layer to the highest (application) layer before transmission to a
`
`destination within the receiving host (e.g., to the operating system space where the
`
`received data may be used by an application running on the receiving host). (Ex.
`
`1001 at 4:20-26.) Each layer of the receiving host recognizes and manipulates
`
`only the headers associated with that layer, since to that layer the higher layer
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`header data is included with and indistinguishable from the payload data.
`
`“Multiple interrupts, valuable central processing unit (CPU) processing time and
`
`repeated data copies may also be necessary for the receiving host to place the data
`
`in an appropriate form at its intended destination.” (Id. at 4:30-33.)
`
`Because the processing of each layer typically involves a copy and data
`
`manipulation operation (for example a checksum computation operation), the host
`
`CPU must be “interrupted” at least one time per layer in order to process the data
`
`and construct (transmit side) or deconstruct (receive side) the packet. An interrupt
`
`is a signal to the processor emitted by hardware or software indicating an event
`
`that needs immediate attention. (Ex. 2001 at ¶ 68.) An interrupt alerts the
`
`processor to a high-priority condition requiring the interruption of the current code
`
`the processor is executing. (Id.) This process involved with traditional network
`
`interface cards results in “repeated copying and interrupts to the CPU” of the host
`
`computer. (Ex. 1001 at 5:24-28.) When the host CPU is interrupted, it generally
`
`must stop all other tasks it is currently working on, including tasks completely
`
`unrelated to the network processing. (Ex. 2001 at ¶ 69.) Frequent interrupts to the
`
`host CPU can be very disruptive to the host system generally and cause system
`
`instability and degraded system performance. (Id.)
`
`The invention of the ‘241 patent includes a “fast-path” where the host CPU
`
`is relieved of certain TCP/IP processing, which is instead performed by the INIC.
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`In other words, the invention “allows data from the message to be processed via a
`
`fast-path which accesses message data directly at its source or delivers it directly to
`
`its intended destination.” (Ex. 1001 at 5:18-22.) The fast-path “bypasses
`
`conventional protocol processing of headers that accompany the data” and
`
`“employs a specialized microprocessor designed for processing network
`
`communication, avoiding the delays and pitfalls of conventional software layer
`
`processing, such as repeated copying and interrupts to the CPU.” (Id. at 5:22-28).
`
`The fast-path is shown in Figure 24 of the ‘241 patent, which is reproduced
`
`below. In this embodiment, the INIC performs at least the IP and TCP layer
`
`processing, freeing up the CPU on the host (“client”) computer to do other tasks.
`
`The fast-path also reduces or eliminates the number of interrupts sent to the CPU
`
`on the host/client. The more traditional “slow-path” is also shown, where the
`
`host/client is responsible for the IP and TCP layer processing. In the slow-path,
`
`the CPU on the host/client is interrupted at least one time for each layer or
`
`processing.
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`(Ex. 1001.026 at Fig. 24.)
`
`The results of the claimed invention include more efficient network
`
`processing and “a huge reduction in interrupts.” (Id. at 11:37-42.) For fast-path
`
`communications, only one interrupt occurs at the beginning and end of an entire
`
`upper-layer message transaction, and “there are no interrupts for the sending or
`
`receiving of each lower layer portion or packet of that transaction.” (Id. at 11:42-
`
`46.) As stated above, the claimed arrangement allows for enhanced network and
`
`system performance, faster data throughput, increased system stability, and an
`
`overall better user experience.
`
`B.
`
`The ‘241 Patent Claims
`
`The ‘241 patent includes three independent claims (only two of which are
`
`challenged in this Petition). Independent claim 1 (reproduced below) is not
`
`challenged in this Petition, but is presented below for completeness. Claim 1
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`recites a method for network communication. Notably, claim 1 recites, inter alia,
`
`“processing the packets by a first mechanism, so that for each packet the network
`
`layer header and the transport layer header are validated without an interrupt
`
`dividing the processing of the network layer header and the transport layer header.”
`
`As described above, by preparing packets for transmission using an INIC instead
`
`of the host CPU, interrupts to the host CPU can be reduced or eliminated
`
`altogether. This claimed feature is not found in any of the prior art cited by
`
`Petitioner.
`
`Claim 1. A method for network communication, the
`method comprising:
`receiving a plurality of packets from the network,
`each of the packets including a media access control
`layer header, a network layer header and a transport
`layer header;
`processing the packets by a first mechanism, so
`that for each packet the network layer header and the
`transport layer header are validated without an interrupt
`dividing the processing of the network layer header and
`the transport layer header;
`the
`sorting
`the packets, dependent upon
`processing, into first and second types of packets, so that
`the packets of the first type each contain data;
`sending, by the first mechanism, the data from
`each packet of the first type to a destination in memory
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`allocated to an application without sending any of the
`media access control layer headers, network layer
`headers or transport layer headers to the destination.
`
`(Ex. 1001.142 at 98:32-49). Claim 2 depends from claim 1 and adds the further
`
`limitation that the media access control layer header for each packet is processed
`
`without an interrupt dividing the processing of the media access control layer
`
`header and the network layer header. (Id. at 98:50-55.) Claim 3 also depends from
`
`claim 1 and additionally requires that an upper layer header of at least one of the
`
`packets is processed by a second mechanism, thereby determining the destination,
`
`wherein the upper layer header corresponds to a protocol layer above the transport
`
`layer. (Id. at 98:56-60.) Likewise, claim 4 depends from claim 1 and adds the
`
`limitation that an upper layer header of at least one of the packets of the second
`
`type is processed by a second mechanism, thereby determining the destination.
`
`(Id. at 98:61-64.) Claim 5 depends from claim 1 and adds the limitation that a
`
`transport layer header of another packet is processed by a second mechanism, prior
`
`to receiving the plurality of packets from the network, thereby establishing a
`
`Transmission Control Protocol (TCP) connection for the packets of the first type.
`
`(Ex. 1001.142-43 at 98:65-99:3). Claim 6 recites that the sorting of the packets
`
`includes classifying each of the packets of the first type as having an Internet
`
`Protocol (IP) header and a Transmission Control Protocol (TCP). (Ex. 1001.143 at
`
`11
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`99:4-7). Claim 7 depends from claim 1 and adds the limitation that a second
`
`plurality of packets is transmitted to the network, each of the second plurality of
`
`packets containing a media access control layer header, a network layer header and
`
`a transport layer header, the method further including processing the second
`
`plurality of packets by the first mechanism, so that for each packet the media
`
`access control layer header, the network layer header and the transport layer header
`
`are prepended at one time as a packet header. (Id. at 99:8-17.) Claim 8 specifies
`
`that the first mechanism is a sequencer running microcode. (Id. at 99:18-19.)
`
`Independent claim 9 (reproduced below) recites a method for
`
`communicating information over a network. Notably, claim 9 recites, inter alia,
`
`“wherein the network layer header is Internet Protocol (IP), the transport layer
`
`header is Transmission Control Protocol (TCP) and the media access control layer
`
`header, the network layer header and the transport layer header are prepended at
`
`one time as a sequence of bits during the prepending of each packet header.” As
`
`described above, by preparing packets for transmission using an INIC instead of
`
`the host CPU, multiple headers can be prepended at one time instead of
`
`interrupting the host CPU between each header operation. This claimed feature is
`
`not found in any of the prior art cited by Petitioner.
`
`Claim 9. A method for communicating information over
`a network, the method comprising:
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`obtaining data from a source in memory allocated
`by a first processor;
`dividing the data into multiple segments;
`prepending a packet header to each of the
`segments by a second processor, thereby forming a
`packet corresponding to each segment, each packet
`header containing a media access control layer header, a
`network layer header and a transport layer header,
`wherein the network layer header is Internet Protocol
`(IP), the transport layer header is Transmission Control
`Protocol (TCP) and the media access control layer
`header, the network layer header and the transport layer
`header are prepended at one time as a sequence of bits
`during the prepending of each packet header; and
`transmitting the packets to the network.
`(Ex. 1001.143 at 99:19-35.)
`
`Independent claim 17 (reproduced below) recites a method for
`
`communicating information over a network. Notably, claim 17 recites, inter alia,
`
`“prepending, by the second mechanism, an outbound packet header to each of the
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`segments . . . wherein the prepending of each outbound packet header occurs
`
`without an interrupt dividing the prepending of the outbound media access control
`
`layer header, the outbound (IP) header and the outbound TCP header.” This
`
`claimed feature is not found in any of the prior art cited by Petitioner.
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`Claim 17. A method for communicating information
`over a network, the method comprising:
`providing, by a first mechanism, a block of data
`and a Transmission Control Protocol (TCP) connection;
`dividing, by a second mechanism, the block of data
`into multiple segments;
`the second mechanism, an
`prepending, by
`outbound packet header to each of the segments, thereby
`forming an outbound packet corresponding to each
`segment, the outbound packet header containing an
`outbound media access control
`layer header, an
`outbound Internet Protocol (IP) header and an outbound
`TCP header, wherein the prepending of each outbound
`packet header occurs without an interrupt dividing the
`prepending of the outbound media access control layer
`header, the outbound (IP) header and the outbound TCP
`header; and
`transmitting the outbound packets to the network.
`(Ex. 1001.143 at 100:3-18.)
`III. PROSECUTION HISTORY OF THE ‘241 PATENT
`
`The ‘241 patent issued on February 26, 2008. It was filed on September 27,
`
`2002 as Application No. 10/260,878 as a continuation of Application No.
`
`10/092,967 filed March 6, 2002, which in turn claims the benefit of Application
`
`No. 10/023,240, filed December 15, 2001, which in turn claims the benefit of
`
`Application No. 09/464,283, filed December 15, 1999, which in turn claims the
`
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`U.S. Patent No. 7,337,241
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` Case No. IPR2017-01713
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`benefit of Application No. 09/439,603, filed November 12, 1999, which in turn
`
`claims the benefit of Application No. 09/067,544, filed April 27, 1998, which in
`
`turn claims the benefit of Provisional Application No. 60/061,809, filed on Oct.
`
`14, 1997.3
`
`The ‘241 patent was subject to a thorough examination by Examiners Eric J.
`
`Kuiper and Jerry B. Dennison, who allowed the application on July 30, 2007 after
`
`two rounds of claim amendments and arguments. (Ex. 1002 at 597-602.) In
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`connection with claim 1, the applicants explained that the prior art of record did
`
`not “teach any processing of a network layer header or a transport layer header, let
`
`alone ‘processing the packets by a first mechanism, so that for each packet the
`
`network layer header and the transport layer header are validated without an
`
`interrupt dividing the processing of the network layer header and the transport
`
`layer header.’” (Id. at 333-334 (emphasis added).)
`
`Similar arguments were made with response to independent claims 9 and 17.
`
`(Id. at 341-43, 345-46.) In connection with claim 9, the applicants argued that the
`
`prior art of record did not show or suggest “wherein the prepending of each packet
`
`header occurs without an interrupt dividing the prepending….” (Id. at 342
`
`
`3 See Ex. 1001.094 at 1:8-2:23 for a listing of other related applications.
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`(emphasis added).)4 In connection with claim 17, the applicants argued that the
`
`prior art of record did not show or suggest “the processing and validating of these
`
`headers all occurring without interrupts between each layer.” (Id. at 346
`
`(emphasis added).)
`
`Accordingly, on July 30, 2007, the Examiner issued a Notice of Allowance
`
`granting claims 1-24 of the ‘241 patent. (Id. at 597-602.) An Issue Notification
`
`was then mailed on February 6, 2008. (Id. at 627.)
`
`IV. OVERVIEW OF THE ASSERTED PRIOR ART
`
`As described above, Intel relies on the Connery reference. Petitioner has not
`
`established that Connery is prior art to the ‘241 patent; all of Petitioner’s
`
`arguments therefore fail.
`
`Assuming the Connery reference is prior art, the following section
`
`summarizes the Connery reference and underscore its shortcomings when
`
`compared to the challenged claims of the ‘241 patent.
`
`
`4 In response to the second Office Action, the interrupt language was replaced
`
`with language requiring “the network layer header and the transport layer header
`
`are prepended at one time as a sequence of bits during the prepending….” (Ex.
`
`1002 at 567-68 (emphasis added).) The patent applicants argued that the prior art
`
`of record did not show this claimed feature. (Id. at 574-75.)
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`A.
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`U.S. Patent No. 5,937,169 (“Connery”)
`
`Connery appears on the face of the ‘241 patent under “References Cited”
`
`and was initialed by the Examiner in an Information Disclosure Statement (IDS)
`
`dated December 20, 2007. (Ex. 1002 at 312.) Connery was therefore already
`
`considered by the Examiner during the prosecution of the ‘241 patent, which was
`
`found to be allowable over Connery .
`
`Connery discloses a data processing system with program memory that
`
`includes a TCP/IP protocol stack and a “segmentation mode.” (Ex. 1001 at 5:44-
`
`50.) A MAC driver is included in the program memory which supports the
`
`segmentation mode. (Id. at 5:51-58.) The s