111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US007337241B2
`
`(12) United States Patent
`Boucher et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,337,241 B2
`Feb. 26,2008
`
`(54) FAST-PATH APPARATUS FOR RECEIVING
`DATA CORRESPONDING TO A TCP
`CONNECTION
`
`(75)
`
`Inventors: Laurence B. Boucher, Saratoga, CA
`(US); Stephen E. J. Blightman, San
`Jose, CA (US); Peter K. Craft, San
`Francisco, CA (US); David A. Higgen,
`Saratoga, CA (US); Clive M. Philbrick,
`San Jose, CA (US); Daryl D. Starr,
`Milpitas, CA (US)
`
`(73) Assignee: Alacritech, Inc., San Jose, CA (US)
`
`( *) Notice:
`
`Subject to any disclaimer, the tenn of this
`patent is extended or adjusted under 35
`U.S.c. 154(b) by 879 days.
`
`(21) Appl. No.: 101260,878
`
`(22) Filed:
`
`Sep. 27, 2002
`
`(65)
`
`Prior Publication Data
`
`US 2004/0064578 Al
`
`Apr. 1,2004
`
`(51)
`
`Int. Cl.
`(2006.01)
`G06F 15116
`(52) U.S. Cl. ...................................................... 7091250
`(58) Field of Classification Search ................. 709/250
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
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`(Continued)
`
`FOREIGN PATENT DOCUMENTS
`
`WO
`
`WOl98119412
`511998
`(Continued)
`
`OTHER PUBLICATIONS
`Internet pages entitled "Hardware Assisted Protocol Processing",
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`1998.
`
`(Continued)
`
`Primary Examiner-David Wiley
`(74) Attorney, Agent, or Firm-Mark Lauer; Silicon Edge
`Law Group LLP
`
`(57)
`
`ABSTRACT
`
`A system for protocol processing in a computer network has
`an intelligent network interface card (INIC) or communica(cid:173)
`tion processing device (CPD) associated with a host com(cid:173)
`puter. The INIC provides a fast-path that avoids protocol
`processing for most large multi-packet messages, greatly
`accelerating data communication. The INIC also assists the
`host for those message packets that are chosen for process(cid:173)
`ing by host software layers. A communication control block
`for a message is defined that allows DMA controllers of the
`INIC to move data, free of headers, directly to or from a
`destination or source in the host. The context is stored in the
`INIC as a communication control block (CCB) that can be
`passed back to the host for message processing by the host.
`The INIC contains specialized hardware circuits that are
`much faster at their specific tasks than a general purpose
`cpu. A preferred embodiment includes a trio of pipelined
`processors with separate processors devoted to transmit,
`receive and management processing, with full duplex com(cid:173)
`munication for four fast Ethernet nodes.
`
`24 Claims, 89 Drawing Sheets
`
`50
`
`46
`
`48
`
`UPPER
`LAYER
`UPPER LAYER
`INTERFACE
`
`TRANSPORT
`
`NETWORK
`
`DATA LINK
`
`\
`
`44
`
`56
`
`INIC/CPD
`
`40
`
`38
`
`36
`
`30
`
`52
`"-
`
`35
`
`58
`
`INTEL Ex.1001.001
`
`

`

`US 7,337,241 B2
`Page 2
`
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`
`INTEL Ex.1001.002
`
`

`

`US 7,337,241 B2
`Page 3
`
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`
`INTEL Ex.1001.003
`
`

`

`US 7,337,241 B2
`Page 4
`
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`which Berend Ozceri is developing, printed Nov. 25, 1998.
`Internet pages of Xaqti corporation entitled "GigaPower Protocol
`Processor Product Review," printed Nov. 25, 1999.
`Internet pages entitled "DART: Fast Application Level Networking
`via Data-Copy Avoidance," by Robert J. Walsh, printed Jun. 3,
`1999.
`Internet pages of InterProphet entitled "Frequently Asked Ques(cid:173)
`tions", by Lynne Jolitz, printed Jun. 14, 2000.
`Internet pages entitled "iReady Products," printed Nov. 25, 1998.
`Andrew S. Tanenbaum, "Computer Networks," Third Edition, 1996,
`ISBN 0-13-349945-6.
`Form lO-K for Exelan, Inc., for the fiscal year ending Dec. 31, 1987
`(10 pages).
`Form lO-K for Exelan, Inc., for the fiscal year ending Dec. 31, 1988
`(10 pages).
`"Second Supplement Information Disclosure Statement per 37
`C.F.R. § 1.97(i)", dated Jui. 29, 2002 relating to Exelan Inc. as
`submitted in U.S. Appi. No. 09/464,283.
`WindRiver article entitled "Tornado: For Intelligent Network Accel(cid:173)
`eration", copyright Wind River Systems, 2001, 2 pages.
`WindRiver White Paper entitled "Complete TCP/IP Offload for
`High-Speed Ethernet Networks", Copyright Wind River Systems,
`2002, 7 pages.
`Intel article entitled "Solving Server Bottlenecks with Intel Server
`Adapters", Copyright Intel Corporation, 1999, 8 pages.
`Schwaderer et ai., IEEE Computer Society Press publication
`entitled, "XTP in VLSI Protocol Decomposition for ASIC Imple(cid:173)
`mentation", from 15th Conference on Local Computer Networks, 5
`pages, Sep. 30-0ct. 3, 1990.
`Beach, Bob, IEEE Computer Society Press publication entitled,
`"UltraNet: An Architecture for Gigabit Networking", from 15th
`Conference on Local Computer Networks, 18 pages, Sep. 30-0ct. 3,
`1990.
`Chesson et ai., IEEE Syposium Record entitled, "The Protocol
`Engine Chipset", from Hot Chips III, 16 pages, Aug. 26-27, 1991.
`Maclean et ai., IEEE Global Telecommunications Conference,
`Globecom '91, presentation entitled, "An Outboard Processor for
`High Performance Implementation of Transport Layer Protocols", 7
`pages, Dec. 2-5, 1991.
`
`Ross et ai., IEEE article entitled "FXI000: A high performance
`single chip Gigabit Ethernet NIC", from Compcon '97 Proceedings,
`7 pages, Feb. 23-26, 1997.
`Strayer et ai., "Ch. 9: The Protocol Engine" from XTP: The Transfer
`Protocol, 12 pages, Jui. 1992.
`Publication entitled "Protocol Engine Handbook", 44 pages, Oct.
`1990.
`Koufopavlou et al., IEEE Global Telecommunications Conference,
`Globecom '92, presentation entitled, "Parallel TCP for High Per(cid:173)
`formance Communication Subsystems", 7 pages, Dec. 6-9, 1992.
`Lilienkarnp et ai., Publication entitled "Proposed Host-Front End
`Protocol", 56 pages, Dec. 1984.
`Thia, YH. Publication entitled "High-Speed OSI Protocol Bypass
`Algorithm with Window Flow Control", Protocols for High Speed
`Networks, pp. 53-68, 1993.
`Thia, YH. Publication entitled "A Reduced Operational Protocol
`Engine (ROPE) for a multiple-layer bypass architecture", Protocols
`for High Speed Networks, pp. 224-239, 1995.
`U.S. Appi. No. 601283,896, Titled: CRC Calculations for Out of
`Order PUDs, filed Apr. 12, 2003, Inventor: Amit Oren, Assignee:
`Siliquent Technologies Ltd.
`U.S. Appi. No. 08/964,304, by Napolitano, et ai., entitled "File
`Array Storage Architecture", filed Nov. 4, 1997.
`"File System Design For An NFS File Server Appliance", Article by
`D. Hitz, et ai., 13 pages, Jui. 17, 2003.
`Adaptec Press Release article entitled "Adaptec Announces
`EtherStorage Technology", 2 pages, May 4, 2000, printed Jun. 14,
`2000.
`Adaptec article entitled "EtherStorage Frequently Asked Ques(cid:173)
`tions", 5 pages, printed Jui. 19, 2000.
`Article from Rice University, Department of Computer Science
`entitled "Lazy Receiver Processing (LRP): A New Network Sub(cid:173)
`system Architecture for Server Systems", by Peter Druschel and
`Gaurav Banga, 15 pages.
`Internet RFC/STD/FYI/BCP Archives article with heading
`"RFC2140" entitled "TCP Control Block Interdependence", web
`address http://www.faqs.org/rfcs/rfc2140.htrnl.9pages.printed
`Sep. 20, 2002.
`* cited by examiner
`
`INTEL Ex.1001.004
`
`

`

`u.s. Patent
`
`Feb. 26,2008
`
`Sheet 1 of 89
`
`US 7,337,241 B2
`
`r - - - - - - - - - - - - - - - - - - - - - - - - . . . ,
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`
`INTEL Ex.1001.005
`
`

`

`u.s. Patent
`
`Feb. 26,2008
`
`Sheet 2 of 89
`
`US 7,337,241 B2
`
`RECEIVE PACKET
`FROM NETWORK
`BYCPD
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`VALIDATE PACKET,
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`
`FIG. 3
`
`CREATE CCB FOR
`MESSAGE
`
`51
`
`INTEL Ex.1001.006
`
`

`

`u.s. Patent
`
`Feb. 26,2008
`
`Sheet 3 of 89
`
`US 7,337,241 B2
`
`REMOTE
`HOST
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`25
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`INTEL Ex.1001.007
`
`

`

`u.s. Patent
`
`Feb. 26,2008
`
`Sheet 4 of 89
`
`US 7,337,241 B2
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`INTEL Ex.1001.008
`
`

`

`u.s. Patent
`
`Feb. 26,2008
`
`Sheet 5 of 89
`
`US 7,337,241 B2
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`MEDIA ACCESS ~ 172
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`INTEL Ex.1001.009
`
`

`

`u.s. Patent
`
`Feb. 26,2008
`
`Sheet 6 of 89
`
`US 7,337,241 B2
`
`176
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`INTEL Ex.1001.010
`
`

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`u.s. Patent
`
`Feb. 26,2008
`
`Sheet 7 of 89
`
`US 7,337,241 B2
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`270
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`
`INTEL Ex.1001.011
`
`

`

`u.s. Patent
`
`Feb. 26,2008
`
`Sheet 8 of 89
`
`US 7,337,241 B2
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`INTEL Ex.1001.012
`
`

`

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`
`

`

`u.s. Patent
`
`Feb. 26,2008
`
`Sheet 10 of 89
`
`US 7,337,241 B2
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`INTEL Ex.1001.014
`
`

`

`u.s. Patent
`
`Feb. 26,2008
`
`Sheet 11 of 89
`
`US 7,337,241 B2
`
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`INTEL Ex.1001.015
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`

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