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`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________
`
`
`INTEL CORPORATION,
`Petitioner
`
`v.
`
`ALACRITECH INC.,
`Patent Owner
`
`___________________
`
`Case IPR2017-01713
`Patent No. 7,337,241
`___________________
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`
`
`
`
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`PATENT OWNER’S EXHIBIT 2001
`DECLARATION OF PAUL PRUCNAL, PH.D.
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`06973-00001/9638491.1
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`
`
`
`Alacritech Exhibit 2001
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`
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`
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`1.
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`I have been retained on behalf of Alacritech, Inc. (“Alacritech” or
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`“Patent Owner”) for the above-captioned inter partes review (IPR) proceeding. I
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`understand that this proceeding was filed by Intel Corporation (“Intel”) and
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`involves U.S. Patent No. 7,337,241 (“the ’241 Patent”), titled “Fast-path apparatus
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`for receiving data corresponding to a TCP connection.” The ’241 Patent is
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`currently assigned to Alacritech. I have been retained to provide my opinions in
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`support of Alacritech’s Preliminary Response Pursuant to 35 U.S.C. § 313 and 37
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`C.F.R. § 42.107 pursuant to the legal standards set forth below. I am being
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`compensated for my time at the rate of $650 per hour. I have no interest in the
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`outcome of this proceeding.
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`2.
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`In preparing this declaration, I have reviewed and am familiar with the
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`following prior art reference:
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`Connery (Ex. 1043) is U.S. Patent No. 5,937,169, which
`issued on August 10, 1999 and is assigned to 3Com
`Corporation.
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`I have also considered all other materials cited and discussed herein,
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`3.
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`including all other materials cited and discussed in Intel’s Petition for Inter Partes
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`Review of U.S. Patent No. 7,337,241 (Case IPR2017-01392).
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`4.
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`I have also considered the following:
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`No.
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`2004
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`06973-00001/9638491.1
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`
`Short Name
`
`Interrupts
`
`Exhibit
`Jonathan Corbet; Alessandro Rubini; Greg
`Kroah-Hartman (2005), Linux Device Drivers,
`Alacritech Exhibit 2001, Page 1
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`
`
`
`
`Claim
`Construction
`Order
`
`3rd edition, Chapter 10, “Interrupt Handling”
`Memorandum Opinion and Order on Claim
`Construction, Case No. 2:16-cv-00693-JRG-
`RSP, Dkt. 362 (E.D. Tex., September 21, 2017)
`
`The ’241 Patent describes a system for protocol processing in a
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`2006
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`5.
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`computer network that has an “intelligent network interface card” (INIC) or
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`“communication processing device” (CPD) associated with a host computer. (Ex.
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`1001 at Abstract). The INIC provides a “fast-path” that avoids some or all
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`protocol processing f or large multi-packet messages, greatly accelerating data
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`communication. (Id.) The INIC can also assist the host for those message packets
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`that are chosen for processing by host software layers. A communication control
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`block for a message is defined that allows Direct Memory Access (DMA)
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`controllers of the INIC to move data, free of headers, directly to or from a
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`destination or source in the host. (Id.) A context, for example, can be stored in the
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`INIC as a communication control block (CCB) that can be passed back to the host
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`for message processing by the host. (Id.) I am familiar with the technology
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`described in the ’241 Patent as of its October 14, 19971 effective filing date.
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`6.
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`The statements made herein are based on my own knowledge and
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`opinion. This Declaration represents only the opinions I have formed to date. I
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`1 The ’241 Patent claims the benefit of U.S. Provisional App. Ser. No.
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`60/061,809, filed on Oct. 14, 1997.
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 2
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`may consider additional documents as they become available or other documents
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`that are necessary to form my opinions. I reserve the right to revise, supplement,
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`or amend my opinions based on new information and on my continuing analysis.
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`II. QUALIFICATIONS
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`7. My qualifications can be found in my Curriculum Vitae, which
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`includes a complete list of my publications. (Ex. 2010).
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`8.
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`I am a professor of Electrical Engineering at Princeton University, in
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`Princeton, NJ. I received my undergraduate education at Bowdoin College, where
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`I graduated summa cum laude in 1974 with an A.B. in Mathematics and Physics. I
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`then graduated from Columbia University in 1976 with a M.S. in Electrical
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`Engineering, and went on to receive an M.Phil. from Columbia University in 1978
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`in Electrical Engineering and a Ph.D. from Columbia University in 1979 in
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`Electrical Engineering.
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`9.
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`Upon graduation from Columbia in 1979, I joined Columbia
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`University as an Assistant Professor of Electrical Engineering, and in 1984 I was
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`promoted to Associate Professor. In 1988, I joined the faculty of Princeton
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`University as an Associate Professor of Electrical Engineering. My responsibilities
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`included teaching and research. At that time, I also was the Founding Director of
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`the New Jersey Advanced Technology Center for Photonics and Optoelectronic
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 3
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`Materials. My responsibilities included leading a $10 million research center
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`involving approximately thirty faculty members.
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`10.
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`In 1990, I was promoted to the position of full Professor of Electrical
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`Engineering at Princeton University. My teaching responsibilities have included
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`courses in electronic circuits, signal processing, communications and fiber-optic
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`networks. My broad research interests have included communications networks
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`and switching, computer interconnects, and network security. I also head the
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`Lightwave Communications Research Laboratory and the Center for Network
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`Security and Access at Princeton University, through which much of my present
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`research is conducted.
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`11. While at Princeton University, I received several awards and
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`recognitions, including: (a) becoming a Fellow of the Institute for Electrical and
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`Electronics Engineers (IEEE) where my fellow citation is, “For contributions to
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`photonic switching and fiber-optic networks;” (b) becoming a Fellow of the
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`Optical Society of America (OSA); (c) receiving the Rudolf Kingslake Medal and
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`Prize from the Society of Photo-Optical Instrumentation Engineers (SPIE) for the
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`most noteworthy original paper in Optical Engineering, titled, “Self-routing
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`photonic switching with optically processed control;” (d) receiving the
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`international Gold Medal Award from the Faculty of Mathematics, Physics, and
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`Informatics from Comenius University; (e) receiving the Princeton University
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 4
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`Graduate Mentoring Award; (f) receiving the Lifetime Achievement Award for
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`Excellence in Teaching from the Engineering Council at Princeton; (g) receiving
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`the Walter Curtis Johnson Prize for Excellence in Teaching; (h) receiving the
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`Princeton School of Engineering and Applied Science Distinguished Teacher
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`Award; (i) receiving the President’s Award for Distinguished Teaching at
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`Princeton.
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`12.
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`I am the author of the books, “Optical Code Division Multiple Access:
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`Fundamentals and Applications” (2005) and “Neuromorphic Photonics (2017),
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`both of which relate to networking. I am a co-author or contributor to
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`approximately thirty additional book chapters, as well as over 300 peer-reviewed
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`publications in peer-reviewed journals and conference proceedings including
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`papers in the area of communications networks and packet switching.
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`13.
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`In addition to the activities, education, and professional experience
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`listed above, I have been involved in numerous research projects that contribute to
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`my expertise relating to this report. My work in these projects have included,
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`among other things, multiple access techniques for high-speed communication
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`networks and fast packet switching techniques. More information on several of
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`these research projects is provided below.
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 5
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`14.
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`In 1982, I worked with Optical Information Systems, Inc. on a project
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`that involved transceiver design for communications systems. My responsibilities
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`included the investigation of high-speed clock recovery.
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`15.
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`In 1983-1984, I worked with GTE Labs on a project that involved
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`performance analysis of communication systems. My responsibilities included the
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`investigation of high performance modulation formats.
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`16.
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`In 1985-1986, I worked with AT&T Bell Laboratories on a project
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`that involved research on multiple access techniques. My responsibilities included
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`investigating multiplexing techniques for telecommunications networks.
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`17.
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`In 1987-1988, I worked with IBM on a project that involved research
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`on multiple access techniques and switching for computer communication
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`networks.
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`18.
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`In 1987-1989, I worked with Dove Electronics on a project that
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`involved research on communication switching technology and architectures. My
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`responsibilities included the design and analysis of fast packet switching
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`architectures.
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`19.
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`In 1992-1995, I worked with Siemens Corporate Research on a
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`project that involved research on switching technology. My responsibilities
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`included the investigation of technologies for high speed multiplexing and
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 6
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`switching, and performing an analysis of the potential application of these
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`technologies to telecommunications networks that carried TCP/IP traffic.
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`20.
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`In 1999-2000, I worked with SAIC on a project that involved research
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`on network architectures. My responsibilities included the investigation of fast
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`switching and multiplexing techniques for high-speed communication networks.
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`21.
`
`In 1999-2002, I worked with Multi Link Technologies, Inc. on a
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`project that involved communication transceiver design. My responsibilities
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`included the design and analysis of high-speed transmitters and receivers.
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`22.
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`In 2000-2002, I worked with Ultra-Fast Optical Systems on a project
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`that involved research and development on packet switching technology. My
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`responsibilities included the design and testing of switch technology.
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`23.
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`In 2000-2003, I was a member of the advisory board on optical
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`network technology for Alphion, Inc. My responsibilities included providing
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`guidance on the development of technology in the communication networks space.
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`24.
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`In 2003-2006, I worked with Kailight Inc. on a project that involved
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`research and development on switching technology. My responsibilities included
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`the design and testing of an optical switch for communication networks.
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`25.
`
`In 2006-2008, I led a DARPA-funded project developing an add drop
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`multiplexer for a metropolitan area networks.
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 7
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`26.
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`In 2004-2011, I worked with NEC Laboratories on a project that
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`involved research on physical layer security in communication networks. My
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`responsibilities included the design and analysis of techniques for steganography
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`and data encryption.
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`27.
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`I am also a named inventor on at least 27 issued U.S. patents, and at
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`least 5 additional U.S. patent applications.
`
`28.
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`I have extensive experience in the communication networks field
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`throughout my career, including being an editor for the IEEE Transactions on
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`Communications.
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`29. Also, during the past 10 years I have taught several undergraduate and
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`graduate courses at Princeton on communications, such as “Photonics and
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`Lightwave Communications,” which includes digital communications systems and
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`networks, including protocols such as TCP/IP; “Electronic Circuit Design,” which
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`covers basic circuit design and implementation; and “An Introduction to
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`Engineering,” which includes basic communication networks. I am also involved
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`with independent research projects involving senior thesis works, the majority of
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`which pertain to communications systems and networking.
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`30. My research focuses on advanced topics in lightwave and radio
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`frequency communication systems, networks and switching. My research has been
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`supported by contracts and grants from the National Science Foundation (NSF),
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 8
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`the U.S. Army Communication Electronics Command, the Office of Naval
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`Research, the Defense Advanced Research Projects Agency (DARPA) and the
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`National Security Agency, among others.
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`31.
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`I also have extensive experience consulting for the communications
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`industry, including AT&T Bell Laboratories, NEC Labs, Alphion Inc. and the
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`Institute for Defense Analyses. In particular, my work at the Institute relates to
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`computers and communication networks.
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`32.
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`I have been a technical advisor to several startup companies in the
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`telecommunications industry. Based on my patents, Kalight Photonics developed
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`all-optical communication switching technology, before being acquired by a
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`publicly traded company. Another company, Bascom Hunter Technologies, in
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`conjunction with L3 Telemetry East, developed anti-jamming systems for wireless
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`networks. This work is also based on my patents.
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`33. From my education, teaching, and consulting experience, I am
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`familiar with networking protocols in general and in particular the TCP/IP
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`protocol. I am also familiar with TCP offload engines (sometime referred to as
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`TOE) that offload the processing of the entire TCP/IP stack to the network
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`controller. I am also familiar with the technologies sometimes referred to as Large
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`Segmentation Offload (LSO) and Receive Side Coalescing (RSC).
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`III. LEGAL UNDERSTANDING
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 9
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`A. The Person of Ordinary Skill in the Art
`34.
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`I understand that a person of ordinary skill in the relevant art (also
`
`referred to herein as “POSA”) is presumed to be aware of all pertinent art, thinks
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`along conventional wisdom in the art, and is a person of ordinary creativity—not
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`an automaton.
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`35.
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`I have been asked to consider the level of ordinary skill in the field
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`that someone would have had at the time the claimed invention was made. In
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`deciding the level of ordinary skill, I considered the following:
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`• the levels of education and experience of persons working in the
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`field;
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`• the types of problems encountered in the field; and
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`• the sophistication of the technology.
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`36. My opinion below explains how a person of ordinary skill in the art
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`would have understood the technology described in the references I have identified
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`herein around the October 1997 timeframe. I have been advised that the earliest
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`possible effective filing date of the ’241 Patent is October 14, 1997.
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`37.
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`In my opinion, a POSA at that time would be a person with (i.) at least
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`four years of relevant work or research experience in the field of network
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`engineering and/or design; (ii.) a Bachelor’s of Science degree in electrical
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`engineering, computer science, or a related field plus at least two to three years of
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 10
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`relevant work or research experience in the field of network engineering and/or
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`design, or (iii) an advanced degree (e.g., Master’s or Ph.D.) and one to two years
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`of relevant work or research experience in the field of network engineering and/or
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`design.
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`38.
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`I am well-qualified to determine the level of ordinary skill in the art
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`and am personally familiar with the technology of the ’241 Patent in the October
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`1997 timeframe. By 1997, I had completed my formal education and had been
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`working in the relevant field as a professor, researcher, or consultant for more than
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`15 years. I have supervised, recruited, advised, and taught individuals at all levels
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`of training in the relevant field. I have also worked with individuals in the industry
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`at all levels of training in the relevant field.
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`39.
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`I was a person of at least ordinary skill in the art at this timeframe.
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`Regardless if I do not explicitly state that my statements below are based on this
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`timeframe, all of my statements are to be understood as a POSA would have
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`understood something as of the alleged effective filing date of the ’241 patent.
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`B. My Understanding of Obviousness Law
`40.
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`I am not a lawyer and will not provide any legal opinions. Though I
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`am not a lawyer, I have been advised that certain legal standards are to be applied
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`by technical experts in forming opinions regarding the meaning and validity of
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`patent claims.
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 11
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`41.
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`I understand that a patent claim is invalid if the claimed invention
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`would have been obvious to a person of ordinary skill in the field at the time the
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`application was filed. This means that even if all of the requirements of the claim
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`cannot be found in a single prior art reference that would anticipate the claim, the
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`claim can still be invalid.
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`42. To obtain a patent, a claimed invention must have, as of the priority
`
`date, been nonobvious in view of the prior art in the field. I understand that an
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`invention is obvious when the differences between the subject matter sought to be
`
`patented and the prior art are such that the subject matter as a whole would have
`
`been obvious at the time the invention was made to a person having ordinary skill
`
`in the art.
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`43.
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`I understand that to prove that prior art, or a combination of prior art,
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`renders a patent obvious, it is necessary to: (1) identify the particular references
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`that singly, or in combination, make the patent obvious; (2) specifically identify
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`which elements of the patent claim appear in each of the asserted references; and
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`(3) explain how the prior art references could have been combined to create the
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`inventions claimed in the asserted claim.
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`44.
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`I understand that certain objective indicia can be important evidence
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`regarding whether a patent is obvious or nonobvious. Such indicia include: (1)
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`commercial success of products covered by the patent claims; (2) a long-felt need
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 12
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`for the invention; (3) failed attempts by others to make the invention; (4) copying
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`of the invention by others in the field; (5) unexpected results achieved by the
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`invention as compared to the closest prior art; (6) praise of the invention by the
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`infringer or others in the field; (7) the taking of licenses under the patent by others;
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`(8) expressions of surprise by experts and those skilled in the art at the making of
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`the invention; and (9) the patentee proceeded contrary to the accepted wisdom of
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`the prior art.
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`45.
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`I understand that in evaluating the validity of the ’241 Patent claims,
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`the content of a patent or printed publication prior art should be interpreted the way
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`a person of ordinary skill in the art would have interpreted the prior art as of the
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`effective filing date (October 1997) of the challenged patent. My full analysis
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`below is based upon these understandings.
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`C. My Understanding of Claim Construction
`46.
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`I have been instructed by counsel on the law regarding claim
`
`construction and patent claims, and understand that a patent may include two types
`
`of claims––independent claims and dependent claims. An independent claim
`
`stands alone and includes only the features it recites. A dependent claim can
`
`depend from an independent claim or another dependent claim. I understand that a
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`dependent claim includes all the features that it recites in addition to all of the
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`features recited in the claim from which it depends.
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 13
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`47.
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`I understand that in this inter partes review the claims must be given
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`their broadest reasonable interpretation, but that interpretation must be consistent
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`with the patent specification.
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`48.
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`I understand that claim terms are given their plain and ordinary
`
`meaning as would be understood by a person of ordinary skill in the art, unless the
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`inventor provides a special meaning for a term.
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`49.
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`I understand that if there are specific statements in the specification
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`that define the invention, those statements are strong evidence of a definition for a
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`term.
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`50. Additionally, I understand and have been instructed that, when a
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`claim’s recitation is purely functional and does not include any definite structure
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`for performing the function claimed, the term is a “means-plus-function” claim. It
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`is my understanding that means-plus-function claims are construed using a two-
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`step process: first, determination of the claimed function, and second, identification
`
`of the corresponding structure. If the term is understood by a POSA as referring to
`
`a particular structure, however, this two-step process is not followed.
`
`51.
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`I understand and have been instructed that, where the claim uses the
`
`word “means,” there is a presumption that it is a means-plus-function claim term. I
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`also understand and have been instructed that an applicant for a patent must
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`disclose adequate structure in the specification to perform the recited function, and
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 14
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`that if adequate structure is not recited, the claim is indefinite. I am further
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`instructed that when the corresponding structure is a general purpose computer or
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`microprocessor, the specification must disclose the algorithm or process to be
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`performed by the general purpose computer or microprocessor, or the claim is
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`indefinite.
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`52.
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`In this Declaration, I have used the broadest reasonable interpretation
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`(“BRI”) standard when interpreting the claim terms.
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`53.
`
`I reserve my right to amend or alter my analysis and opinions in view
`
`of the Patent Owner’s proposed claim constructions, if any.
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`IV. BACKGROUND OF THE TECHNOLOGY DISCLOSED IN THE ’241
`PATENT
`
`54.
`
`I understand Petitioner has filed for Inter Partes Review of eight
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`related Alacritech patents: U.S. Patent No. 7,124,205, 7,237,036, 7,337,241,
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`7,673,072, 7,945,699, 8,131,880, 8,805,948, and 9,055,104 (“the Alacritech
`
`Patents”). The Alacritech Patents reflect inventions relating to offloading certain
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`tasks traditionally performed by the CPU to a Network Interface Device.
`
`55. The transmission of data over a network usually requires multiple
`
`steps. For example, the data has to be broken up into packets of a certain size that
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`can be sent over the network. Information needs to be added to packets that, for
`
`example, helps them get to the right recipient. Then, once the intended recipient
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`receives the data packets, additional processing often needs to be done. For
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 15
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`
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`example, packets often need to be reassembled and sent to a location in memory
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`where they can be accessed by programs that use the data.
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`56. The steps involved in the process of data transmission are each
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`typically performed by different software, in a particular order, and without
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`bypassing any steps. This is what is known as a “multi-layered software
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`architecture.” At each layer, the sending computer performs additional processing
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`on the data received from the previous layer, for example adding new metadata,
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`dividing the data into packets, or addressing the data. Once the data reaches the
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`final layer, it is ready to be transmitted over the network.
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`57. The receiving computer uses the same multi-layered software
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`architecture to process incoming data packets. Layers are processed in the reverse
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`order on the receive-side. So, the network interface layer or physical layer receives
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`packets from the network medium. Then the data is reassembled and the metadata
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`is accessed and used to ensure the data is provided to the correct destination and in
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`the correct format. The data is stored until it is ready to be used by another
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`program.
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`58. Although this traditional approach for transferring data is functional
`
`and well-established, it can also be slow and inefficient. The central processor
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`(CPU), which is responsible for the software layers, uses a lot of processing power
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`to do this type of layer-by-layer processing. Additionally, moving from one
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 16
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`processing layer to the next may involve making a new copy of the data, further
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`burdening the CPU.
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`59.
`
`In the 1990s, network traffic exploded through the advent of the
`
`Internet and related technologies. The burden of traditional layer-by-layer
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`processing in computer networks—long a recognized but unsolved problem—
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`became a fundamental threat to the efficient expansion of computer networking
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`scope and volume. Overburdened host CPUs constituted a bottleneck in a variety
`
`of network computing contexts.
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`60. Engineers and scientists in both the public and private sectors worked
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`extensively on the problem of network acceleration throughout the late 1980s and
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`throughout the 1990s. A few academics and industry groups proposed and/or
`
`theorized that some kind of offloading procedure or architecture could improve
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`network processing speeds, but none of these proposals was sufficiently developed
`
`or explained to actually solve the growing problem of overburdened network CPUs
`
`by the late 1990s.
`
`61.
`
`It was not enough to simply theorize that processing could be split or
`
`offloaded from the host CPU in a computer network (this is a basic premise of
`
`distributed processing architectures, after all) —there needed to be concrete
`
`solutions as to how this split or offload would be achieved. None of the proposals
`
`in the 1980s and 1990s—including proposed standards—actually solved the
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`06973-00001/9638491.1
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`Alacritech Exhibit 2001, Page 17
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`problem of host CPU overload. And many, many engineers and academics were
`
`working directly on this problem over this time period.
`
`62.
`
`In the late 1990s and early 2000s, Alacritech invented several
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`improvements over the traditional approach to network data processing.
`
`Alacritech’s inventions, which are disclosed and claimed in the Alacritech Patents,
`
`went well beyond earlier theories and proposals that CPU processing could
`
`somehow be offloaded: the Alacritech Patents describe a unique, novel architecture
`
`in which critical portions of network processing are offloaded to a dedicated
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`processor on a network interface device, rather than a general purpose CPU.
`
`63. The inventions embodied in the Alacritech Patents largely solved the
`
`tricky and growing problem of network host CPU overload, and they were greeted
`
`as paradigm-shifting advances in the industry.
`
`V. THE ’241 PATENT
`A. Overview
`64. As explained herein, the ’241 patent describes a novel system for
`
`accelerating network processing. An intelligent network interface card (INIC)
`
`communicates with a host computer. The INIC provides “a fast-path that avoids
`
`protocol processing for most large multi-packet messages, greatly accelerating data
`
`communication.” Ex. 1001 at Abstract. In some embodiments, the INIC
`
`“contains specialized hardware circuits that are much faster at their specific tasks
`
`than a general purpose CPU.” (Id.).
`Alacritech Exhibit 2001, Page 18
`06973-00001/9638491.1
`
`
`
`
`
`
`65. As explained in the background of the ’241 patent, when a
`
`conventional network interface card prepares to send data from a first host to a
`
`second host, “some control data is added at each layer of the first host regarding
`
`the protocol of that layer, the control data being indistinguishable from the original
`
`(payload) data for all lower layers of that host.” (Id. at 3:67-4:3). For example, an
`
`application layer attaches an application layer header to the payload data and sends
`
`the combined data to the presentation layer of the sending host, which receives the
`
`combined data, operates on it and adds a presentation layer header to the data,
`
`resulting in another combined data packet. The data resulting from combining the
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`payload data, application layer header, and presentation layer header is then passed
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`to the session layer, which performs required operations including attaching a
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`session layer header to the data and presenting the resulting combination of data to
`
`the transport layer. This process continues as the information moves to lower
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`layers, with a transport layer header, network layer header, and data link layer
`
`header and trailer attached to the data at each of those layers, with each step
`
`typically including data moving and copying, before sending the data as bit packets
`
`over the network to the second host. (Id. at 4:4-20).
`
`66. This process of adding a layer header to the data from the preceding
`
`layer is sometimes referred to as “encapsulation” because the data and layer header
`
`is treated as the data for the immediately following layer, which, in turn, adds its
`
`06973-00001/9638491.1
`
`
`Alacritech Exhibit 2001, Page 19
`
`
`
`
`
`own layer header to the data from the preceding layer. Each layer is generally not
`
`aware of which portion of the data from the preceding layer constitutes the layer
`
`header or the user data; as such, each layer treats the data it receives from the
`
`preceding layer as some generic payload. The figure below, which I annotated
`
`with colors, illustrates the encapsulation process. The user data (payload) is
`
`colored in purple. In the example below, layer headers in the form of an
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`application layer header (in yellow), TCP layer header (in blue), IP layer header (in
`
`orange), and Ethernet header and trailer (in green) each encapsulate the user or
`
`application data received from the layer immediately above.
`
`
`
`06973-00001/9638491.1
`
`
`Alacritech Exhibit 2001, Page 20
`
`
`
`
`
`
`
`Ex. 1008, Stevens at .034, Figure 1.4 (adapted from Petition at 1).
`
`67. On the receiving side, the receiving host generally performs the
`
`reverse of the sending process, beginning with receiving the bits from the network.
`
`Headers are removed, one at a time, and the received data is processed, in order,
`
`from the lowest (physical) layer to the highest (application) layer before
`
`transmission to a destination within the receiving host (e.g., to the operating system
`
`space where the received data may be used by an application running on the
`
`receiving host). (Ex. 1001 at 4:20-26). Each layer of the receiving host
`
`recognizes and manipulates only the headers associated with that layer, since to
`
`that layer the higher layer header data is included with and indistinguishable from
`
`the payload data. “Multiple interrupts, valuable central processing unit (CPU)
`
`processing time and repeated data copies may also be necessary for the receiving
`
`host to place the data in an appropriate form at its intended destination.” (Id. at
`
`4:30-33).
`
`68. Because the processing of each layer typically involves a copy and
`
`data manipulation operation (for example a checksum computation operation), the
`
`host CPU must be “interrupted” at least one time per layer in order to process the
`
`data and construct (transmit side) or deconstruct (receive side) the packet. An
`
`interrupt is a signal to the processor emitted by hardware or software indicating an
`
`event that needs immediate attention. One popular textbook explains “[a]n
`
`06973-00001/9638491.1
`
`
`Alacritech Exhibit 2001, Page 21
`
`
`
`
`
`interrupt is simply a signal that the hardware can send when it wants the
`
`processor’s attention.” (Ex. 2004 at 258 (emphasis in original)). The purpose of
`
`the interrupt is to “let the processor know when something has happened.” (Id.)
`
`69. An interrupt alerts the processor to a high-priority condition requiring
`
`the interruption of the current code the processor is executing. The interrupt
`
`process used in connection with traditional network interface cards results in
`
`“repeated copying and interrupts to the CPU” of the host computer. (Ex. 1001 at
`
`5:24-28). When the host CPU is interrupted, it generally must stop all other tasks
`
`it is currently working on, including tasks completely unrelated to the network
`
`processing. “For the most part, a driver need only register a handler for its
`
`device’s interrupts, and handle them properly when they arrive.” (Ex. 2004 at
`
`258). The “interrupt handler” is a piece of software that is executed by the CPU
`
`after receiving the interrupt. “If the [operating system] hasn’t been told to expect
`
`[the] interrupt, it simply acknowledges and ignores it.” (Ex. 2004 a
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