`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Patent of:
`
`Lebens et al.
`
`U.S. Patent No.:
`
`6,095,661
`
`
`
`Issue Date:
`
`August 1, 2000
`
`Appl. Serial No.:
`
`09/044,559
`
`Filing Date:
`
`March 19, 1998
`
`Title:
`
`METHOD AND APPARATUS FOR AN L.E.D.
`
`FLASHLIGHT
`
`
`PETITION FOR INTER PARTES REVIEW OF UNITED STATES PATENT
`NO. 6,095,661 PURSUANT TO 35 U.S.C. §§ 311–319, 37 C.F.R. § 42
`
`
`Exhibit LG-1013
`
`Philips Semiconductor Application Note AN170 (1988)
`
`

`

`INTEGRATED CIRCUITS
`
`APPLICATION NOV.
`
`NE555 and NE556 applications
`
`AN170
`
`1988 Dec
`
`Semiconductors
`
`
`
`PHILIPS
`
`Exhibit LG 1013 Page 1
`
`Exhibit LG 1013 Page 1
`
`

`

`Philips Semiconductors
`
`NE555 and NE556 applications
`
`Application note
`
`AN170
`
`INTRODUCTION
`In mid 1972, Philips Semiconductors introduced the 555timer, a
`unique functional building block that has enjoyed unprecedented
`popularity. The timer's success can be attributed to several inherent
`characteristics foremost of which are versatility, stability and low
`cost, There can be no doubtthat the 555 timer has altered the
`course of the electronics industry with an Impact not unlike that of
`the IC operational amplifier.
`
`oscillator, only one additional resistor is necessary. By proper
`selection of external components,oscillating frequencies from one
`cycle per half hour to 500kHz can be realized, Duty cycles can be
`adjusted from less than one percent to 99 percent over the
`frequency spectrum. Voltage controlof timing and oscillation
`functionsis also available,
`
`Timer Circuitry
`The timer is comprised of five distinct circuits: two voltage
`comparators; a resistive voltage divider reference; a bistable
`The simplicity of the timer, In conjunction with its ability to produce
`long time delays in a variety of applications, has lured many
`flip-flop; a discharge transistor, and an output stage that is the
`designers from mechanical timers, op amps, and various discrete
`"totem-pole” design for sink or source capability. Q;9-Q43 comprise
`circuits into the ever increasing ranksoftimer users.
`a Darlington differential pair which serves asatrigger comparator.
`Starting with a positive voltage on the trigger, Q49 and Qy4 tum on
`when the voltage at Pin 2 is moved below one third of the supply
`voltage. The voltagelevelis derived from a resistive divider chain
`consisting of R7, Ra and Rg, All three resistors are of equal valle
`(5K22). At 15V supply, the triggering level would be SV.
`When Q49 and Qy, turn on, they provide a base drive far Q45,
`turning if on. Qy5 and Q47 form a bistable flip-flop, When Qy4s is
`saturated, Qyg is “off and Qy7 is saturated, Qyg and Qy7 will remain
`in these states evenif the trigger Is removed and Qys is turned "off.
`While Q47 is saturated, Qa9 and Qy4q are turned off.
`
`DESCRIPTION
`The 555 timer consists of two voltage comparators,a bistable
`flip-flop, a discharge transistor, and a resistor divider network. To
`understand the basic concept ofthe timerlet's first examine the
`timer in block form as in Figure 1.
`
`
`
`The output structure of the timeris a “lotem-pole" design, with Qag
`and Q24 being large geometry transistors capable of providing
`200mA with a 15V supply. While Qopis “off, base drive is provided
`for Qo2 by Qz4, thus providing a high output.
`For the duration that the outputis in a high state, the discharge
`transistoris "off. Since the collector of Q4,4 is typically connected Io
`the external timing capacitor, GC, while Qy,4 is off,the timing capacitor
`now can charge through thetiming resistor, Ra,
`
`The capacitor voltage is monitored by the threshold comparator
`(Qy-Q4) which is a Darlington differential pair. When the capacitor
`voltage reachestwo thirds of the supply voltage, the currentis
`directed from Qg and Qy thru Qy and Qs. Amplification of the current
`change Is provided by Qs and Q¢, Qs-Qg and Q7-Qg comprise a
`diode-biased amplifier. The amplified current change from Qg now
`provides a base drive for Qy, whichis part of the bistable flip-flop, to
`changestates. In doing so, the outputis driven "low", and Qy4, the
`dischargetransistor, is turned "on", shorting the timing capacitor to
`ground,
`
`The discussion to this point has only encompassed the most
`fundamental of the timer's operating mades and circuitry, Several
`points of the circuit are brought out to the real world which allow the
`timer to function In a variety of modes.It is essential that one
`understands all the variations possible In orderto utilize this device
`to its fullest extent.
`
`Reset Function
`Regressing to the trigger mode,it should be noted that once the
`device has triggered and the bistable flip-flop is set, continued
`triggering will not interfere with the timing cycle. However, there may
`come a time when itis necessary to interrupt or halt a timing cycle.
`This Is the function that the reset accomplishes.
`
`In the normal operating modethe resettransistor, Qos, is off with its
`base held high. When the base of Qys is grounded, it turns on,
`providing base drive to Qy4, turning it on. This discharges the timing
`capacitor, resets the flip-flop at Qy7, and drives the output low. The
`reset overridesall other functions within the timer.
`
`Exhibit LG 1013 Page 2
`
`a
`RESET
`
`sLuogs4
`—s
`Figure 1. 555/556 Timer Functional Block Diagram
`
`capacitor voltage exceeds 2/3 of the supply, the threshold
`comparator resets the flip-flop which in turn drives the output to a
`low state. When the outputis in a low state, the dischargetransistor
`is “on", thereby discharging the external timing capacitor. Once the
`capacitor is discharged, the timer will await anothertrigger pulse, the
`timing cycle having been completed.
`
`The 555 and its complement, the 556 Dual Timer, exhibit a typical
`initial timing accuracy of 1% with a 50ppnvV/Ctiming drift with
`temperature, To operate the timer as a one-shot, only two external
`components are necessary,resistance & capacitance. For an
`
`1988 Dec
`
`Theresistive divider network is used to set the comparatorlevels.
`Since all three resistors are of equal value, the threshold comparator
`is referenced internally at 2/3 of supply voltage level and the trigger
`comparator is referenced at 1/3 of supply voltage. The outputs of the
`comparators aretied to the bistable flip-flop. Whenthe trigger
`voltage is moved below 1/3 of the supply, the comparator changes
`stata and sets the flip-flop driving the output to a high state, The
`threshold pin normally monitors the capacitor voltage of the RC
`timing network, When the
`Veco
`|
`555 OR 1/2 556
`
`DISCHARGE |
`~ 7 ]
`SS
`|
`|
`|
`VOLTAGE |
`|
`|
`|
`|
`OUTPUT Sai
`|
`
`L
`“a
`
`|=
`
`FLIP
`FLOP
`
`E
`
`
`
`CONTROL
`
`R
`
`|
`THRESHOLD |
`vonthe
`|
`|
`mt
`|
`|
`
`
`
`Exhibit LG 1013 Page 2
`
`

`

`
`
`Philips Semiconductors Application note
`
`NE555 and NE556applications
`AN170
`
`
`
`FM
`
`
`
`
`
`
`
`TRIGGER
`oe
`RESET
`
`om j—
`DISCHARGE
`GND ce
`hk
`NOTE:
`All resistor values are in ohms. ~S
`
`
`
`‘|
`
`3 63K
`
`
`
`CONTROL VOTLAGE
`
`tRi
`
`
`
`il
`
`
`
`SLOOBSS
`
`Figure 2. Schematic of 555 or 1/2 556 Dual Timer
`voltage function is not used, it is strongly recommended that a
`bypass capacitor (0.01HF) be placed across the control voltage pin
`and ground. This will increase the noise immunity of the timer to
`high frequency trash which may monitor the threshold |evels causing
`timing error.
`
`Trigger Requirements
`Dueto the nature of the trigger circultry, the timer will trigger on the
`negative-going edgeofthe input pulse. For the device to time-out
`properly, itis necessary that the trigger voltage level be retumed to
`some voltage greater than one third of the supply before the timeoul
`period, This can be achieved by makingeither the trigger pulse
`sufficiently short or by AG coupling into the trigger. By AC coupling
`the trigger (see Figure 3), a short negative-going pulse is achieved
`whenthe trigger signal goes to ground. AC coupling is most
`frequently used in conjunction with a switch or a signal that goes to
`ground which initiates the timing cycle. Should the trigger be held
`low, without AC coupling, for a longer duration than the timing cycle
`the output will remain in a high state for the duration of the low
`triggersignal, without regard to the threshold comparatorstate. This
`is due to the predominance of Q;5 on the base of Qj¢, controlling
`the state of the bistable flip-flop. When the trigger signal then retums
`to a high level, the output will fall immediately, Thus, the output
`signal will follow the trigger signalin this case.
`
`Control Voltage
`One additional point ofsignificance, the control voltage, is brought
`out on the timer. As mentioned earlier, both the trigger comparator,
`Q45-Qy3, and the threshold comparator, Q;-Qy, are referenced to an
`internal resistor divider network, Ry, Ry, Re. This network
`establishes the nominal two thirds of supply voltage (Vcc)trip point
`for the threshold comparator and one third of Vcc for the
`
`trigger comparator. The two thirds point at the junction of Ry, Rg and
`the base of Qy is brought out, By imposing a voltage at this point,
`the comparator reference levels may be shifted either higher or
`lower than the nominal levels of one third and twothirds ofthe
`supply voltage. Varying the voltageat this point will vary the timing.
`This feature of the timer opens a multitude of application possibilities
`sUch as Using the timer as a voltage-controllad oscillator,
`pulse-width modulator, etc, For applications where the control
`
`1986 Dec
`
`Monostable Operation
`The timer lends itself to three basic operating modes:
`1, Monostable (one-shot)
`
`2. Astable (oscillatory)
`
`3. Time delay
`
`Byutilizing one or any combination of basic operating modes and
`suitable variations, it is possible to utilize the timer in a myriad of
`applications. The applications are limited only to the imagination of
`the designer.
`
`One of the simplest and most widely used operating modes of the
`timer is the monostable (one-shot). This configuration requires only
`two external components for operation (see Figure 4). The
`sequence of events starts when a voliage below one third Vccis
`sensed by the trigger comparator. The triggeris normally applied in
`the form of a short negative-going pulse, On the negalive-going
`edge of the pulse, the device triggers, the output goes high and the
`dischargetransistor turns off. Note that prior to the input pulse, the
`dischargetransistoris on, shorting the timing capacitor to ground, At
`this point the timing capacitor, C, starts charging through the timing
`resistor, R. The voltage on the capacitor increases exponentially
`with a time constant T=RC, |gnoring capacitor leakage, the capacitor
`will reach the two thirds Vec level in 1,1 time constants or
`
`T=1.1RC
`
`(1)
`
`Exhibit LG 1013 Page 3
`
`Exhibit LG 1013 Page 3
`
`

`

`
`
`Philips Semiconductors Application note
`
`AN170
`NE555 and NE556 applications
`
`
`Where T is in seconds, R is in ohms, and C is in Farads. This
`voltage level trips the threshold comparator, whichin turn drives the
`output low and turns on the discharge
`
`Voc
`
`Voc
`
`O04 \F
`ire
`
`||||||
`
`} |
`
`Voc
`
`13VeC
`
`VOLTS
`
`oy = AunReon:OF
`TRIGGER PULSE AS
`SWITCH ‘elie
`SEEN BY THE TIMER
`AT THIS POINT thaddats
`
`Figure 3. AC Coupling of the Trigger Pulse
`
`
`
`transistor. The transistor discharges the capacitor, C, rapidly. The
`timer has completedits cycle and will now await another trigger
`pulse.
`
`Astable Operation
`In the astable (free-run) mode, only one additional component, Rg,
`is necessary. Thetrigger Is now tied to the threshold pin, At
`power-up, the capacitoris discharged, holding the trigger low. This
`triggers the timer, which establishes the capacitor charge path
`through Ra and Rg. When the capacitor reaches the threshold level
`of 2/3 Vee, the output drops low and the discharge transistor turns
`on.
`
`The timing capacitor now discharges through Rp. When the
`capacitor voltage drops to 1/3 Vee, the trigger comparatortrips,
`automatically retriggering the timer, creating an oscillator whose
`frequency is given by:
`
`f=
`
`1.49
`(R, + QR) c
`
`(2)
`
`Selecting the ratios of Ra and Rg Varies the duty cycle accordingly.
`Lo and behold, we have a problem.If a duty cycle of less than fifty
`percent is required, then what? Even if Ra=0, the charge time
`cannot be made smaller than the discharge time because the
`charge path Is Ra+Rg while the discharge path is Rg alone. In this
`case it becomes necessary to insert a diodein parallel with Ra,
`cathode toward the timing capacitor. Anotherdiode is desirable, but
`not mandatory (this one in series with Ra), cathode away from the
`timing capacitor. Now the charge path becomes Ra, through the
`parallel diode Into C. Discharge is through the series diode and Rg
`to the dischargetransistor. This scheme will afford a duty cycle
`range from less than 5% to greater than 95%, It should be noted that
`for reliable operation a minimum value of 3kQ2 for Re is
`recommended to assurethatoscillation begins.
`
`Time Delay
`In this third basic operating mode, we aim to accomplish something
`a little different fram monostable operation, In the monostable mode,
`when a trigger Was applied, immediately changed to the high state,
`timed out, and returned to its pre-trigger low state, In the time delay
`mode, we require the output not to change state upontriggering, but
`at some precalculated time aftertrigger Is received.
`The threshold and trigger are tied together, monitoring the capacitor
`voltage. The
`
`
`
`
`
`TRIGGER
`ea
`
`DISCHARGE
`
`CONTROL
`VOLTAGE _
`THRESHOLDoO
`
`
`
`
`
`RESET
`SLoOOSST
`
`Figure 4. Monostable Operation
`
`1988 Dee
`
`Exhibit LG 1013 Page 4
`
`Exhibit LG 1013 Page 4
`
`

`

`Philips Semiconductors
`
`NE555 and NE556 applications
`
`Application note
`
`AN170
`
`
`
`
`
`DISCHARGE o=—T ———
`R
`CONTROL
`3
`VOLTAGE ~
`THRESHOLO ©
`
`
`
`
`
`TRIGGER ©
`
`
`
`Ml
`[—|OuTPUT|—2
`
`FLIP
`foe
`
`
`
`RESET
`
`sLoogsa
`
`
`
` =
`
`OPTIONAL
`
`|
`TAL
` / Re
`x
`—*
`|[toischiarce|
`ey
`v
`SLOO859
`|
`=
`Figure 6, Method of Achieving Duty
`Cycles Less Than 50%
`
`Selecting External Components
`In selecting the timing resistor and capacitor, there are several
`considerations to be taken into account.
`
`Stable external components are necessary for the RC network if
`good timing accuracyis to be maintained. The timing resistor(s)
`should be of the metalfilm variety if timing accuracy anc
`repeatability are important design criteria. The timer exhibits a
`typical Initial accuracy of one percent. That is, with any one RC
`network, from timer to timer only one percent change is to be
`expected, Mostoftheinitial timing error(i.e., deviation from the
`formula) is due to inaccuracies of external components, Resistors
`range from their rated values by 0.01% to 10% and 20%. Capacitors
`may have a 5% to 10% deviation from rated capacity. Therefore, in a
`system wheretimingis critical, an adjustable timing resistor or
`precision components are necessary, For best results, a good
`quality trim pot, placed in series with the largest feasible resistance,
`will allow for best adjustability and performance.
`
`The timing capacitor should be a high quality, stable component with
`very low leakage characteristics. Under no circumstances should
`ceramic disc capacitors be used in the timing network! Ceramic disc
`capacitors are not sufficiently stable in capacitance fo operate
`properly in an RC mode. Several acceptable capacitor types are:
`silver mica, mylar, polycarbonate, polystyrene, tantalum, orsimilar
`types.
`
`The timer typically exhibits a srnall negative temperature coefficient
`(50ppm/°C). If timer accuracy over temperature is a consideration,
`timing components with a small positive temperature coefficient
`should be chosen. This combination will tend to cancel timing drift
`due to temperature.
`
`In selecting the values for the timing resistors and capacitor, several
`points should be considered. A minimum value of threshold current
`is necessary to trip the threshold comparator, This value Is 0,254.
`To calculate the maximum value of resistance, keep in mind that at
`the time the threshold current is required, the voltage potential on
`the threshold pin is twothirds of supply, Therefore:
`
`Vootentiat = Veo - Veapacitor
`Vootential = Veo - 2/8Vecg= 1/8Vcc
`
`Figure 5. Astable Operation
`
`discharge function is not used. The operation sequence begins as
`transistor (T;) is turned on, keeping the capacitor grounded. The
`trigger sees a low state and forces the timer output high. When the
`transistoris turned off, the capacitor commences its charge cycle.
`When the capacitor reaches the threshold level, only then does the
`output change from its normally high state to the low state, The
`output will remain low until T is again turned on.
`
`GENERAL DESIGN CONSIDERATIONS
`The timer will operate over a guaranteed voltage range of 4.5V to
`15Voc with 16Voc being the absolute maximum rating, Most of the
`devices, however, will operate at voltage levels as low as 3Voc. The
`timing Interval is Independentof supply voltage since the charge rate
`and threshold level of the comparator are both directly proportional
`to supply. The supply vollage may be provided by any numberof
`sources, however, several precautions should be taken. The most
`important, the one which provides the most headachesif not
`practiced, is good power supply filtering and adequate bypassing.
`Ripple on the supply line can cause loss oftiming accuracy. The
`threshold level shifts, causing a change of charging current. This will
`cause a timing error forthat cycle.
`Dueto the nature of the output structure, a high power totem-pole
`design, the output of the timer can exhibit large current spikes on the
`supplyline. Bypassing is necessary to eliminate this phenomenon, A
`capacitor across the Vee and ground, directly across the device, is
`necessary and ideal, The size of a capacitor will depend on the
`specific application. Values of capacitance from 0.01yF to 10uF are
`not uncommon, but note that the bypass capacitor would be as
`close to the device as physically possible.
`
`1988 Dec
`
`Exhibit LG 1013 Page 5
`
`Exhibit LG 1013 Page 5
`
`

`

`Application note
`Philips Semiconductors
`
`AN170
`NE555 and NE556applications
`
`
`(3)
`
`The mostimportant characteristic of the capacitor should be as low
`a leakage as possible. Obviously, any leakage will subtract fram the
`charge count, causing the calculated time to be longerthan
`anticipated,
`
`Maximum resistance is then defined as
`
`Ruan =
`
`Vecap
`Veco
`7THRESH
`
`Example: Veco = 15V
`
`10
`15
`*,
`Ruax = paso 6) ~ “MG
`
`Veco =5V
`
`Control! Voltage
`Regressing momentarily, we recall that the control voltage pin is
`connected directly to the threshold comparatorat the junction of R;,
`or
`
`Reg. The combination of R7, Rg and Rg comprisesthe resistive
`voltage divider network that establishes the nominal Veéc trigger
`comparatorlevel (junction Rg, Rg) and the Vcc level for the
`threshold comparator(junction Rz, Rg).
`
`For most applications, the control voltage function is not Used and
`therefore is bypassed to ground with a small capacitor for noise
`filtering. The control voltage function, in other applications, becomes
`an integral part of the design. By Imposing a voltage at this pin, it
`becomes possible to vary the threshold comparator“set” level above
`or below the 2/3 Vee nominal, thereby varying the timing. In the
`monostable mode, the control voltage may be varied fram 45% to
`90% of Vee. The 45-90% figure is not firm, but only an indication to
`a safe usage. Control voltage levels below and above those stated
`have been used successfully in some applications,
`
`In the oscillatory (free-run) mode, the control voltage limitations are
`from 1.7V ta Voc. These values should be heededforreliable
`operation, Keep in mind that in this mode the trigger level is also
`important. When the control voltage ralses the threshold comparator
`level, it also raise the trigger comparator level by one-half that
`amount due to Rg and Rg of Figure 2. As a voltage-controlied
`oscillator, ane can expec! +25% around center frequency (fg) to be
`virtually linear with a normal RC timing circuit. For wider linear
`variations around fg it may be desirable to replace the charging
`resistor with a constant-current source,In this manner, the
`exponential charging characteristics of the classical configuration
`will be altered to linear charge time.
`
`Reset Control
`The only remaining function now is the reset. As mentioned earlier,
`the reset, when taken to ground, inhibits all device functioning. The
`output is driven low,the bistable flip-flop is reset, and the timing
`capacitor is discharged. In the astable (oscillatory) mode, the reset
`can be used to gate the oscillator. In the monostable, it can be used
`as a timing abort to either interrupt a timing sequence or establish a
`standby mode (i.¢., device off during power-up). It.can also be used
`in conjunction with the trigger pin to establish a positive
`edge-triggered circuit as opposed to the normal negative
`edge-trigger mode. One thing to keep in mind when using the reset
`function is that the reset voltage (switching) point is between 0.4
`and 1,0V (min/max). Therefore, if used in conjunction with the
`trigger, the device will be out of the reset modeprior to reaching 1V.
`At that point the triager is in the “turn on" region, below 1/3 Vee. This
`will cause the device to trigger immediately, effectively triggering on
`the positive-going edge if a pulse is applied to Pins 4 and 2
`simullaneously.
`
`FREQUENTLY ASKED APPLICATIONS
`QUESTIONS
`Thefollowing is a harvest of various maladies, exceptions, and
`idiosyncrasies that may exhibit themselves from timeto time in
`
`Exhibit LG 1013 Page 6
`
`3.33
`5
`= 2s = HEM
`0.25(10 ®)
`oon
`
`Ruwax
`NOTE:
`(fusing a large value oftiming resistor, be certain that the capacitor leakage |s significantly
`lower than the charging current available to minimize timing error.
`
`On the other end of the spectrum, there are certain minimum values
`of resistance that should be observed, The discharge transistor,
`Q44, is current-limited at 35mA to 55mAinternally. Thus, at the
`currentlimiting values, Q;4 establishes high saturation voltages.
`When examining the currents at Q)4, remember that the transistor,
`when turned on, will be carrying two current loads, The first being
`the constant current through timing resistor, Ra. The secandwill be
`the varying discharge current from the timing capacitor. To provide
`best operation, the current contributed by the Ra path should be
`minimized so that the majority of discharge current can be used to
`resetthe capacitor voltage. Henceit is recommended that a 5kQ2
`value be the minimum feasible value for Ra. This does not mean
`lower values cannot be Used successfully in certain applications, yet
`there are extreme cases that should be avoidedif at all possible.
`
`SLOO960
`it
`
`
`DISCHARGE o-——
`
`CONTROL
`VOLTAGE
`
`THRESHOLD 5
`
`fp
`
`TRIGGER
`
`
`o— I
`
`
`
`RESET
`
`Figure 7, Time Delay Operation
`
`Capacitor size has not proven to be a legitimate design criteria.
`Values ranging from picofarads to greater than one thousand
`microfarads have been used successfully, One precaution need be
`utilized, though. (It should be a cardinal rule that applies to the
`usage ofall ICs.) Make certain that the package powerdissipation is
`not exceeded, With extremely large capacitor values, a maximum
`duty cycle which allows some cooling time for the discharge
`transistor may be necessary,
`
`1988 Dec
`
`Exhibit LG 1013 Page 6
`
`

`

`Application note
`Philips Semiconductors
`
`AN170
`NE555 and NE556 applications
`
`
`Various applications. Rather than cast aspersions, a quick review of
`this list may Uncover a solution to the problem at hand,
`= _In the oscillator mode when resetis released thefirst lime
`constant is approximately twice as long as the rest, Why?
`Answer: In the oscillator mode the capacitor voltagefluctuates
`between 1/2 and 2/3 of the supply voltage. When reset is pulled
`down, the capacitor discharges completely. Thus for the first cycle
`it must charge from ground to 2/3 Voc, which takes twice as long.
`
`2. What is maximum frequency of oscillations?
`Answer. Most devices will oscillate about 1MHz. However, in the
`interest of temperature stability, one should operate only up to
`about 500kHz.
`
`3. What Is temperature drift for oscillator mode?
`Answer: Temperature drift of oscillator mode is 3 times that of
`one-shot mode due to the addition of a second voltage
`comparator. Frequency always increases with an increasing
`temperature, Therefore it is possible to partially offset this drift
`with an offsetting temperature coefficientin the external
`resistor/capacitor combination.
`
`4, Oscillator exhibits spurious oscillations on crossover points. Why?
`Answer: The 555 can oscillate due to feedback from power
`supply. Always bypass with sufficient capacitance close to the
`device for all applications.
`
`5, Trying to drive a relay bul 555 hangs up. How come?
`Answer: Inductive feedback. A clamp diode across the coil
`prevents the coll from driving Pin 3 below a negative 0.6V. This
`negative voltage is sufficient in some cases to cause thetimerto
`malfunction, The solution is to drive the relay through a diode,
`thus preventing Pin 3 from ever seeing a negative voltage.
`a . Double triggering of the TTL loads sometimes occurs. Why?
`Answer: Dueto the high current capability and fast rise andfall
`times of the output, a totem-pole structure different from the TTL
`classical structure was used, Near TTL threshold this output
`exhibits a crossover distortion which may double triggerlogic. A
`1000pF capacitor from the output to ground will eliminate any
`false triggering.
`7. Whatis the longest time | can get out of the timer?
`Answer: Times exceeding an hour are possible, but not always
`practical, Large capacitors with low leakage specs are quite
`expensive. It becomes cheaperto use a countdown scheme (see
`Figure 15) at some point, dependent on required accuracy.
`Normally 20 to 30 min, is the longest feasible time.
`
`DESIGN FORMULAS
`Before entering the section on specific applications itis
`advantageousto review the timing formulas. The formulas given
`here apply to the 555 and 556 devices.
`
`APPLICATIONS
`The timer, since introduction, has spurred the Imagination of
`thousands. Thus, the ways in whichthis device has been used are
`far too numerous to present each one. A review of the basic
`operation and basic modes has previously been given. Presented
`
`here are some ingenious applications devised by our applications
`engineers and by some of our customers,
`
`Missing Pulse Detector
`Using the circuit of Figure 10a, the timing cycle is continuously reset
`by the input pulsetrain, A change in frequency, or a missing pulse,
`allows completion of the timing cycle which causes a changein the
`output level. For this application, the time delay should be set to be
`slightly longer than the normal time between pulses. Figure 10b
`showsthe actual waveforms seen In this mode of operation.
`
`Figure 11b shows the waveforms of the timer in Figure 11a when
`used as a divide-by-three circuit, This application makes use of the
`fact that this circuit cannot be retriggered during the timing cycle.
`
`Pulse Width Modulation (PWM)
`In this application, the timer is connected in the monostable mode as
`shownin Figure 12a. The circuitis triggered with a continuous pulse
`train and the threshold voltage is modulated bythe signal applied to
`the control voltage terminal (Pin 5). This has the effect of modulating
`the pulse width as the contro! voltage varies. Figure 12b shows the
`actual waveform generated with this circuit.
`
`Pulse Position Modulation (PPM)
`This application uses the timer connected for astable (free-running)
`operation, Figure 13a, with a modulating signal again applied to the
`control voltage terminal. Now the pulse position varies with the
`modulating signal, since the threshold voltage, and hence the time
`delay, is varied, Figure 13b shows the waveform generated for
`trangle-wave modulation signal.
`
`Tone Burst Generator
`The 556 Dual Timer makes an excellent tone burst generator, The
`first half is connected as a one-shot and the second half as an
`oscillator (Figure 14).
`
`The pulse established by the one-shot turns on the oscillator,
`allowing a burstto be generated,
`
`Sequential Timing
`One feature of the dualtimer is that by utilizing both halves itis
`possible to obtain sequential timing. By connecting the output of the
`first half to the input of the second half via a 0,001\.F coupling
`capacitor, sequential timing may be obtained. Delayt; is determined
`by the first half and tz by the secondhalf delay (Figure 15).
`
`Vec0 SLO0861
`
`Figure 8. Driving High Q Inductive Loads
`
`4988 Dec
`
`Exhibit LG 1013 Page 7
`
`Exhibit LG 1013 Page 7
`
`

`

`
`
`Philips Semiconductors Application note
`
`AN170
`NE555 and NE556applications
`
`
`
`
`ee
`SR
`
`A
`
`T (OUTPUT HIGH) = 1.7 RAS
`
`a. Monostable Timing
`
`eo
`.
`
`Re
`
`FT|—
`
`6
`
`-
`
`(7 = TIME BEFORE
`QUTPUT GOES LOW)
`
`Voc
`
`R
`
`c
`
`Ap ett Rac
`tI]o—I
`
`b. True Time Delay
`
`Re
`
`=e
`14 (OUTPUT HIGH) = 2-67 (Ra * (Raye
`WACATROT WAC). 5 REY AB
`3
`4) (GUTPUT HIGH) = 9.87 Rac
`>= Cc
`T=1y + tg(TOTAL PERIOD)
`°
`4 (QUTPUT ILOW) = 6.67 Rac
`1
`149
`a
`
`Tey * ta{TOTAL PERIOD) "7 7ik,+2p)©
`J
`= 7
`_ Rat Rp
`OMDUTY CYCLE) =Ra+2Rg
`c. Modified Duty Cycle (Astable)
`d. Astable Timing
`ssLuiciaes
`7
`Figure 9,
`
`Thefirst half of the timer is started by momentarily connecting Pin 6
`to ground. Whenit is timed-out (determined by 1.1 R,C;) the
`second half begins.Its duration is determined by 1.1 RoCo.
`
`
`
`
`
`
`Yee (§T0 15V)
`
`‘|
`
`OUTPUTO——
`
`CAPACITOR VOLTAGE 5V/CM
`Ra 1Kic =.09—F
`
`b, Expected Waveforms
`SL0086a
`Figure 10.
`
`1988 Dec
`
`i
`
`Exhibit LG 1013 Page 8
`
`Exhibit LG 1013 Page 8
`
`

`

`Application note
`Philips Semiconductors
`
`AN170
`NE555 and NE556 applications
`
`
`
`
`
`
`+*Vec & TO 15V)
`RESET 4
`o— +
`
`b. Expected Waveforms
`a
`sL00864 |
`
`Figure 11.
`
`4. CONTROL
`“T. VOLTAGE
`
`a. Schematic Diagram
`INPUT
`
`= oF
` CAPACITOR VOLTAGE 5V/CM
`
`t= 0.1 MS/CM
`
`Ra 112500 C = .02uF —F
`
`+Voc (5 TO 5V)
`
`
`
`|
`
`Ra
`
`Cc
`
`c
`MODULATION
`INPUT
`
`a. Schematic Diagram
`
`T=0,5 MSICM
`MODULATION INPUT 2V/CM
`
`OUTPUT VOLTAGE 5ViCM “|SO
`
`OUTPUT VOLTAGE sviCM
`
`
`b. Expected Waveforms
`SLO0955
`Figure 12.
`
`
`
`
`
`
`
`* Vcc (5 TO 5V)
`
`
` eh te
`
`MODULATION
`INPUT
`
`a. Schematic Diagram
`T=0.1 MSICM
`MODULATION INPUT 2V/CM
`
` CAPACITOR VOLTAGE — 2V/CM
`
`Ra — 3KRg —S00Ne = .01r
`SLOOBEE |
`b. Expected Waveforms
`Figure 13.
`
`Long Time Delays
`In the 556 timer the timing is a function of the charging rate of the
`external capacitor. For long time delays, expensive capacitors with
`extremely low leakage are required. The practicality of the
`components involvedlimits
`Vec
`Vec
`
`oOM052222
`TRIGGER
` o=~
`|
`
`INPUT, |
`
`i.
`
`
`
`NOTE:
`All resistor values ara in ohms.
`SLOOSGT
`
`Figure 14, Tone Burst Generator
`the time between pulses to around twenty minutes.
`
`To achieve longer time periods, both halves may be connected in
`tandem with a “divide-by" network in between.
`
`
`
`
`1986 Dec
`
`Exhibit LG 1013 Page 9
`
`Exhibit LG 1013 Page 9
`
`

`

`Application note
`Philips Semiconductors
`
`AN170
`NE555 and NE556 applications
`
`
`Thefirst timer sectian operates in an oscillatory mode with a period
`of 1/fg. This signal is then applied to a “divide-by-N" network to give
`an output with the period of N/fg. This can then be Used to trigger
`the second haif of the 556. The total time is now a function of N and
`fo (Figure 16).
`
`Speed Warning Device
`Utilizing the “missing pulse detector" concept, a speed warning
`device, such as depicted, becomesa simple and inexpensivecircuit
`(Figure 17a).
`
`Car Tachometer
`The timer receives pulses from the distributor points. Meter M
`receives a calibrated current thru Rg when the timer output is high.
`After time-oul, the meter receives no current for that part of the duty
`cycle. Integration of the variable duty cycle by the meter movement
`ce
`ee
`ad
`:
`providesa Visible indication of engine speed (Figure 18).
`
`that capacitor C can charge. When capacitor voltage reaches the
`timer's control voltage (0.33Vec), the flip-flop resets and the
`transistor conducts, discharging the capacitor (Figure 19).
`
`Greaterlinearity can be achieved by substituting a constant-current
`source for the frequency adjust resistor (R).
`
`Vee Vec
`
`Vec
`j
`
`Voc Voc
`Rz
`130KS
`
`c3
`= ay
`=Pourur
`© OUTPUT 2
`
`= iV}
`
`cc
`
`
`10K
`
`
`
`Oscilloscope-Triggered Sweep
`The 555 timer holds down the cost of adding a triggered sweep to
`an economy oscilloscope. The circuit's input op amp triggers the
`swooasa|
`timer, setting its flip-flop and cutting off its discharge transistor so
`Figure 15. Sequential Timer
`
`:
`LONG TIME COUNTER
`—
`.
`7
`(HOURS, DAYS, WEEKS,, ETC.)
`
`~~
`*
`Tt
`|
`
`inpuTFRom 1
`it
`
`N82B81 COUNTER
`13 4490771314 6 }—
`5} dg (30 MIN.)
`
`O()ROUR)\.0ipF
`
`-O (2HOUR) G—||-4—
`© (4 HOUR)
`
`+
`cea
`=r,
`8287
`_—
`} THF “]ote
`FOR LONGER TIMES
`
`:
`——— §
`aL
`NOTE:
`sLogsed
`>
`All resistor values are in ohms,
`
`- Figure 16. Method of Achieving Long Time Delays
`
`
`
`iL
`=
`=
`=
`
`|
`
`
`
`
`RBUFFER
`
` © Veco = 12V
`10K
`
`a. Schematic of Speed Warning Device
`
`b. Operating Waveforms
`Speed Warning Device
`
`SLOOS7O
`
`Figure 17.
`
`1988 Dec
`
`10
`
`Exhibit LG 1013 Page 10
`
`Exhibit LG 1013 Page 10
`
`

`

`sloo973 Figure 20. Square Wave Tone Burst