`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Patent of:
`
`Lebens et al.
`
`U.S. Patent No.:
`
`6,095,661
`
`
`
`Issue Date:
`
`August 1, 2000
`
`Appl. Serial No.:
`
`09/044,559
`
`Filing Date:
`
`March 19, 1998
`
`Title:
`
`METHOD AND APPARATUS FOR AN L.E.D.
`
`FLASHLIGHT
`
`
`PETITION FOR INTER PARTES REVIEW OF UNITED STATES PATENT
`NO. 6,095,661 PURSUANT TO 35 U.S.C. §§ 311–319, 37 C.F.R. § 42
`
`
`Exhibit LG-1013
`
`Philips Semiconductor Application Note AN170 (1988)
`
`

`

`INTEGRATED CIRCUITS
`
`APPLE©ATH©N N©TE
`
`NE555 and NE556 applications
`
`AN170
`
`1988 Dec
`
` PHILIPS
`
`Exhibit LG 1013 Page
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`Exhibit LG 1013 Page 1
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`

`

`Philips Semiconductors
`
`NE555 and NE556 applications
`
`Application note
`
`AN170
`
`lN TRODU CTION
`In mid 1972. Philips Semiconductors introduced the 555 timer. a
`unique lunctionel building block that has enjoyed unprecedented
`popularity. The timer's success can be attributed to several inhalant
`meracterlsiics foremost of which are versatility. stability and low
`cost. There can be no doubt that the cos-timer has altered the
`course oi the electronics industry with an impact not unlike thatof
`the It: operational amplifier.
`
`The simplicity of the timer. in conjunction with its-ability to produce
`long time delays in a variety of application's. has lured meny
`designers irom mechanical timers. op amps. and various discrete
`circuits Into the ever increasing ranks of timer users.
`
`DESCRIPTION
`The 555 timer consists of two voltage comparators. a bistable
`flip-lion. a discharge transistor. and a resistor divider network. To
`understand the basic concept of the timer let‘s first examine the
`timer in block form as In Figure ‘l.
`
`The resistive divider network is used to set the comparator levels.
`Since all three resistors are or equal value. the threshold comparator
`is referenced internally at Zlo of supply voltage level and the trigger
`comparator is referenced at ill! of supply voltage. The outputs of the
`comparators are lied to the bistable flip-flop. When the trigger
`voltage is moved below lid of the supply. the comparator changes
`state and Sets the flip-flop driving the output to a high state. The
`threshold pin non-nelly monitors the paoltor voltage oi the RC
`timing netvrodr. When the
`
`555 OR 111553
`
`ODNT‘RIJI.
`l
`morass |
`
`
`
`
`Figure 1. 555l558 Timer Functional Block Diagram
`
`capacitor voltage exceeds 213 of the supply. the threshold
`comparator resets the flip-flop which in turn drives the outputtoa
`low state. When the output is in a low state. the discharge transistor
`is 'on". thereby dischargan the extemel timing capacitor. once the
`capacitor is discharged. the-timer will await another trigger pulse. the
`timing cycle having been completed.
`The 555 and its complement. the 556 Dual Timer. exhibit a typical
`initial timing accuracy of 1% with a 5Dppmlc tinting chill with
`temperature. To operate the timer as a one-shot, only two external
`components are necessary: resistance a capacitance. For an
`
`1988 Dec
`
`oscillator. only one additional resistor is necessary: 83! proper
`selection of eartemal components. oscillating rreqUenoies from one
`cycle per half hour to SOBkHz can be realized. Duty cycles can be
`adjusted from less than one percent to 99 percent over the
`frequency spemrum. Voltage control chiming and oscillation
`Motions is also available.
`
`Timer Circuitry
`The tlmr ls comprised of five distinct circuits: two voltage
`comparetms.‘ a resistive voltage divider reference; a bistable
`flip-flop: a discharge transistor: and an output stage that is the
`"totem-pole“ design for sink or source capability. 010—013 comprise
`a Darlington differential pair Which serves as a trigger comparator.
`Starting with a positive voltage on the trigger. Q19 and 011 turn on
`when the voltage at Pin 2 is moved below one third of the supply
`voltage. The voltage level is derived from a resistive divider chain
`consisting oi R7. R3. and Fig. All three resistors are of equal value
`(5K3). At 15v supply. the triggering level would be 5v.
`When Q19 and o“ turn on. they provide a base ddveiorois.
`tuming it on. 015 and 017 form a bistable fllp~llop. When 015 Is
`saturated. 016 is "off' and 01? is saturated, Q13 and on will remain
`in these states even If the trigger is removed and 015 is turned "oil".
`While on is saturated. 020 and 014 are turned oil.
`The output structure of the limeris a ‘totem~pole" design. with 022
`and 024 being large geometry transistors capable of providing
`'ZDomA with a 15V supply. White 02;; is “off. base drive Is provided
`for {223 by 0”. thus providing a high output.
`For the duration that the output is in a high state. the discharge
`transistor is "cfi'.. Since the collector of Q14 is typically BenneotEEd to
`the external timing capacitor. C. While (:14 is oil. the timing capacitor
`now can charge through the timing resistor. RA.
`
`The capacitor voltage is monitored by'the threshold comparator
`[(21-90 which is a Darlington difierential pair. When the capacitor
`Voltage reaches two thirds of the supply voltage. the current is
`directed from 03 and {2‘ thru 01 and Q2. Amplification of the current
`change ls provided by 05am 03. 05-05 and Q‘r-Qa comprise a
`diode-biased amplifier. The amplified current change item 05 now
`provides a base drive for 015 which is part of the bistable flip-flop. to
`change states. In doing so. the output is driven “low”. and 014. the
`discharge transistor. is turned “on”. shorting thetlrrling capacitor to
`ground.
`
`The discussion to this point has only encompassed the most
`fundamental of the timers operallng modes and circuitry. Several
`points of the circuit are brought out to the real world which allow the
`timer to function in a variety of modes. It is essential that one
`understands all the variations possible in order to utilize this device
`to its fullest extent.
`
`Reset Function
`Regressin‘g to- the trigger mode. it should be noted that once the
`device has triggered and the bistable flip-flop is set. continued
`triggering will not interfere with the timing cycle. However. there may
`come a time when his necessary to interrupt or halt a timing cycle.
`This Is the function that the reset accomplishes.
`
`In the normal operating mode the reset transistor. 025. is off with its
`base held high. When the base of 025 is grounded. it turns on.
`providing base drive to 014. tumlng it on. This discharges the timing
`capacitor. resets the flip-flop at Q”. and drives the output low. The
`reset overrides all other functions within the timer.
`
`Exhibit LG 1013 Page 2
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`

`

`
`
`Philips Semiconductors Application note
`
`AN170
`NE555 and NE556 applications
`
`
`
`
`
`
`
`
`
`
`am o:|__
`NOTE:
`All resistor ill-lire. are lot ohms.
`
`SLUEBSS
`Figure 2. Schematic of 555 or 132 556 Dual Timer
`voltage function is not used. it is strchgiy recommended that a
`bypass capacitor (0.01ij be placed across the control voltage pin
`and ground. This will increase the noise immunity of the timer to
`high frequency trash which may motor the threshold levels sensing
`timing error.
`
`Trigger Requirements
`Due to the nature of the trigger circuitry. the timerwifl trigger on the
`negative-going edge of the input pulse. For the device to time~out
`properly. it is necessary that the tdgger voltage level be 'retumed to
`some voltage greater than one third of the supply before the timeout
`period. This can he achieved by making either the trigger pulse
`sufficiently short or by AG coupling into the trigger. By AC coupling
`the trigger (see Figure 3). a short negativergclng pulseis achieved
`When the trigger signal goes to ground. AC coupling ismost
`fi'equently used in conjunction with a switch or a signal that goes to
`ground which initiates the timing cycle. Should the triggarbo held
`low. without AG coupling. for a longerduration than the timing cycle
`the culputwiil remain in a'high state tonne-duration ofthe low
`trigger signal. without regard to the threshold comparator state. This
`is due to the predominance of 015. on the base of Gig. controlling
`the state of the bistable flip-flop. When the trigger signal then returns
`to a high level. the output will fall immediately. Thus. the output
`signal will follow the trigger signal in this case.
`
`Control Voltage
`One additiOnal point of significance. the control voltage. is brought
`outon the timer. As mentioned riler. both the trigger comparator:
`Orig-Q”. and the threshold con'Iparator, (31-61;. are referenced to an
`internal resistor divider network. R}. 9.3. R9. This network
`establlshes the nominal two thirds of supply voltage (Veg) trip pint
`tor the threshold comparator and one third ochc tor the
`
`trigger comparator. The two thirds point at theiunctlon of R1. R5 and
`the base of Q4 is brought out. By- lmpodrig a voltage at this point.
`the comparator reference levels may be shllted either higher or
`lower than the nominal levels of one third and two thirds of the
`supply voltage. Varying the voltage at this point will vary the timing.
`This feature of the timer opens a multitude of application possibilities
`such as Using the timer as a voltage-controlled oscillator.
`pulse-width modulaionetc, For applications wheretha control
`
`1988 Dec
`
`Monostable Operation
`The timer lends itsell'to three basic operating modes:
`1. Monostable (one-shot)
`
`2 Asteble {oscillatory}
`3. Time delay
`
`By utilizing one or any combination of basic operating modes and
`suitable variations. it is possible to uti|i2e the timer in a myriad of
`applications. The applications sreil'r'nited cnty to the Imagination oi
`the designer.
`
`One of the simpteet and mosther used operating modes oi the
`timer is the 'mcnostsble (one-shot). This oonfigumtion requires only
`five external components for operation (see Figure .4). The
`sequence of events starts when a voltage below one third Vac is
`sensed by the trigger comparator. The trigger is normally applied in-
`the form at a short negative-going pulse. On the negativesgoing
`edge of the pulse, the derrice triggers. the output goes high and the
`discharge transistor turns oft. Note thatpricrto the Inputpulso. the
`discharge transistor is on. shorting the timing capacitor to ground. At
`this point the timing capacitor. C. starts charging through the timing
`resistor. 'R‘. The voltage on the capacitor increases exponentially
`with a tlma constant T=RC. ignoring capacitor leakage. the ceoadtcr
`will reach the two thirds Vcc level in 1.1 time constants or
`
`r=1.1nc
`
`{1)
`
`Exhibit LG 1013 Page 3
`
`Exhibit LG 1013 Page 3
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`

`

`
`
`Philips Semicondudors Application note
`
`AN170
`NE555 and NE556 applications
`
`
`Where Tis in seconds. R is in ohms. and C is in Parade. This
`voltage level trips the threshold comparator. which in turn drives the
`output low-and {Lima on the discharge
`
`transistor. The transistor discharges the capacitor. C. rapidly. The
`timer has completed its cycle and will now await another trigger
`pulse.
`
`Astahle Operation
`in the asteble {free-run) mode. only oneeddltionel component. R9.
`is necessary. The. trigger is now tied to the threshold pin. At
`power-up. the capacitor isdlscharged. holding the trigger low. This
`triggers the timer. which establishes the capacitor charge path
`through RA and R5. When the capacitor reaches the threshold level
`of 2:3 Vac. the-output drops low end the discharge transistor turns
`on.
`
`The-timing capacitor now discharges through Rg. thn the
`Capacitor voltage drops to U3 tree. the trigger comparator trips.
`automatically retriggering the timer. creating an oscillator whose
`frequency is given by:
`
`1.49
`g
`r ‘ {RA + 2R3} c
`
`{2)
`
`Selecting the ratios Df'RA and Fig varies the duty cycle accordingly.
`Lo and behold. we have a problem. lie doty cycle oilass than tiny
`percent is required. then what? Even if Rffl. the til-large time
`cannot be made smaller than the discharge time because the
`charge path is RA+R3 while the discharge path is Ra alone. In this
`case it becomes necessary to insert a diode in parallel with R3.
`cathode toward the timing capacitor. Another diode is desirable. but
`not mandatory (this one in series with R5). cathode away from the
`timing capacitor. Now the charge path becomes RA. through the
`parallel diode into 0. Discharge is through the series diode and R3
`to the discharge transistor. This scheme will afford a duty cycle
`range from less than 5% to greater than 95%.. it should be noted that
`for-reliable operation a minimum velueot am for Ra is
`recommended to assure that oscillation begins.
`
`Time Delay
`In this third basic operating mode. we aim to accomplish something
`a little different from nionostabie operation. in the rmncstable mode.
`when a triggerwas applied. immediater mangled to the high state.
`timed out. and returned to its prehigger low state. In the time delay
`mode. we require the output notto change state upon triggering. but
`at some [recalculated tirne alter bigger is resettled.
`The threshold and trigger are tied together. monitoring the capacitor
`voltage. The
`
`SLmfi
`
`1—D-
`OUMFIcAflON OF
`seen er THE mes
`TRIGGER Puts: as
`
`,4
`stillneH enouuoso
`AT THIS POINT
`Figure 3. Ac Coupling of the Trigger Pulse
`
`
`
`
`
`
`
`
`Figure 4. Monoetabie Operation
`
`1983 Dec
`
`Exhibit LG 1013 Page 4
`
`Exhibit LG 1013 Page 4
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`

`

`Application note
`Philips Semiconductors
`
`AN170
`'NE555 and NE’556 applications
`
`
`
`
`
`DISCHARGE -
`
`CONTROL
`VOLTAGE
`THHBLD
`
`
`
`
`
`TRIGGER '
`
`SHINE!
`er
`Flgure 5. Astahle Operation
`
`discharge filtration is not used. The operation sequence begins as
`transistor (T1) is turned on. keeping the capacitor grounded. The
`trigger sees a low state and forces the timer output high. When the
`transistor is tumed off. the capacitor commences its charge cycle.
`When the capacitor reaches the threshold level. only then does the
`output change from Its normally high state to the low state. The
`output will remain low until T1 Is again turned on.
`
`GENERAL DESIGN CONSIDERATIONS
`The timer will operate over a guaranteed voltage range of 4.5V to
`15VDC with 16%;; being the absolute maximum rating. Most of the
`devices. however. will operate at voltage levels as low as SVDG. The
`timing interval is independent or sup-ply voltage since the charge rate
`and threshold level of the comparator are both directly proportional
`to supply. The supply voltage may beprovided by any number of
`amroes. however. several precautions should be taken. The most
`important. the one which provides the most headaches it not
`practiced. is good power supply filtering and adequate bypassing.
`Ripple on the supply line can cause loss oftiming accuracy. The
`threshold level shifts, using a change of charging current. This Will
`cause a timing error for that cycle.
`Due to the nature of the otdput structure. a high poWer totei'n-pole
`design. the output of the timer can exhibit large cun'ent spikes on the
`supply line. Bypassing is necessary to eliminate this phenomenon. A
`capacitor across the V35 and ground. directly across the device. is
`necessary and ideal. The size of a capacitor will depend on the
`specific application. Values of capacitance from 0.01pF to lflliF are
`not uncommon. but note that the bypass capacitor would be as
`close to the device as physically possible.
`
`
`
`
`
`Figure B. Method of Achieving Duty
`Cycles Less Than 50%
`
`Selecting External components
`in selecting the tinting resistor and capacitor: there are several
`considerations to be taken into account.
`
`Stable external components are necessary for the RC network it
`good timing accuracy is to be maintained. The timing resistorts}
`should be of the metal film variety if liming accuracy and
`repeatability are important design criteria. The timer exhibits a
`typical initial accuracy of one percent. That is. with any one RC
`network. from timer to timer only one percent change is to be
`expected. Most of the Initial liming error ([.e.. deviation from the
`formula) ie-due to inaccuracies of external components. Resistors
`range from their rated values by 0.01% to who and 20%. Capacitors
`may house 5% to 10% deviation from rated capacity. Therefore. in a
`system where timing is critical. an adjustable timing resistor or
`precision components are necessary For-beet results. a good
`quality trim pot. placed in series with the largest feasible resistance.
`Mil allow-for best adjustability and perfomrance.
`
`The timing capacitor should be a high quality, stable component with
`very low leakage characteristics. Under no circumstances should
`ceramic disc capacitors be used in the timing network! Ceramic disc
`capacItors are not sulllciently stable in capacitance to operate
`properly in an RC mode. Several acceptable capacitor types are:
`silver mica. myiar. polycarbonate. pclystyrene. tantalum. or similar
`types.
`
`The timer typically exhibits a small negatlvo tamperature ooefilcient
`(onppmi‘cl. If timer accuracy over temperature is a consideration.
`timing components with a small positive temperature coefficient
`should be chosen. This combination will tend to cancel timing drl'lt
`due to temperature.
`
`In selecting the values for the timing resistors and capacitor. several
`points should be considered. A minimum value of threshold current
`is necessary to trip the threshold comparator. This value is 0251A
`To calculate the maximum value of resistance. keep in mind that at
`the time the threshold current is. required. the voltage potehtial on
`the threshold pin is two thirds of supply. Therefore:
`
`Vpoterrlial = Vco ‘ Vespsclror
`
`Vnotential = Vcc - Woo = 1l3Vcc
`
`1933' Dec:
`
`Exhibit LG 1013 Page 5
`
`Exhibit LG 1013 Page 5
`
`

`

`Application note
`Philips Semiconductors
`
`AN170
`NE555 and NE556 applications
`
`
`Maximum melatance is then defined as
`
`R
`
`V
`
`V
`
`=
`one
`as
`m ‘THRESH
`
`The most important characteristic of the capacitor should be as low
`a leakage as possible. ObVi'Dthly. any leakage will subtract from the
`charge count. causing the calculated time to be longer than
`anticipated.
`
`(3]
`
`Example: Vac = 15V
`
`_
`10
`_ 15
`RM“ ' ozone E) ‘ 20”“
`
`Vcc=5V
`
`2
`
`3.33
`_ s
`RM” ' c.25rio 6}
`NOTE:
`"using a large value of timing resistor. be cadalnthal the capemw leakage is aignillcsimy
`lower than the charging current available in Minimize lining error.
`
`E'EMQ
`
`On the other end of the spectrum. there are certain minimum valuae
`of resimance that should be observed. The discharge transistor.
`014. is current-limited at 35m to 55m intemaily. Thus. at the
`current limiting values. OH establishes high saturation voltages.
`When examining the currents ate)“. remember that the transistor.
`when turned on. will be carrying two percent loads. The first being
`the constant current through timing resistor. RA. The second will be
`the varying discharge current from the timing capacitor. To provide
`best operation. the current contributed by the Fly; path should be
`minimized so that the majority of discharge current can be used to
`reset the capacitor voltage. Hence it is recommended that a Skill
`value be the minimum feasible value for RA- This does not mean
`louver values cannot be used successfully in certain applications, yet
`there are extreme see that should be avoided if at all possible.
`
`
`
`
`
`
`Figure 1. Time Delay Operation
`
`Capacitor size has not proven to be a legitimate design criteria.
`Values ranging from picofarads to greater titan one-thousand
`microla'rads have been used successfully. One precaution need be
`utilized. though. (it should be a cardinal rule that applies to the
`usage-cf all IGs.) Maire certain that the package. porter dissipation is
`not exceeded. With extremely large capacitor values. a maximum
`duty cycle Which allow: some cooling time for the discharge
`transistor may be necessary.
`
`1935 DEG
`
`Control Voltage
`Regreesing momentarily. we recall that the control voltage pin is
`connected directly to the threshold comparator at the junction of R1.
`or
`
`R5. The oombinationof Rh R3 anng comprises ihe resistors
`voltage divider network that establishes the nominal Ver trigger
`comparator level (junction R3. R9] and the Vcc level for the
`threshold comparator [junction Ra. Ra).
`
`For most applications. the control Voltage function is not used and
`therefore is bypassed to ground with a small capacitor for noise
`flitering.'The control voltage function. In other applications. becomes
`an integral part of the design. Ely imposing a'vcltage at this pin. it
`becomes possibistc vary the threshold comparator'“set" level above
`or below the 246 V3; nominal. thereby varying the timing. In the
`monostable mode. the control voltage may be varied from d5'li: to
`90% of Vcc. The 45-90% figure is not firm. but only an indication to
`a safe usage. Control voltage levels below and above those stated
`have been used successfully in some applications.
`
`in the oscillatory lireean) mooe. the control voltage limitations are
`from 1.7V to Vac. These values should be heeded for reliable
`operation. Keep in mind that in this mode the trigger level is also
`important. When the control voltage retrace the threshold Gomnamtor'
`level. it also raise the trigger comparator level by one—half that
`amount due to R5 and R3 of Figure 2. As a voltagevcontrolled
`oscillator. one can expect 125% around center frequency (to) to be
`virtually linear with a ncrrnal RC timing circuit. For wider linear
`variations around to. it may be desirable to replace the charging
`resistor with a constant-current source. In this manner. the
`exponential charging characteristics at the classical configuration
`will be altered to linear charge time.
`
`Reset Control
`The only remaining function new is the reset. As mentioned earlier.
`the reset. when taken to ground. inhibits all device functioning. The
`output is driven low. the bistable flip-flop is reset. and the timing
`capacitor is discharged. In the astable (oscillatory) mode. the reset
`can housed to gate the oscillator. in the rnono'stable. it can be used
`as a timing abort to eitherintenupt a timing sequence or establish a
`standby mode (Le. device all during powar-up). It-can also be used
`in conjunction With the trigger pin to establish a positive
`edge-triggered circultas opposed to the normal negative
`edge-trigger mode. Cine thing to keep In mind when using the reset
`function is that the reset voltage isvntching} point is between 0.4V
`and 1.0V (mlnfmaxl. Therefore. if Used in conjunction with the
`bigger. the device will be out of the reset mode prior to reaching 1V.
`At that point the trigger is in the “turn cn’l region. below 1l3 Vac. This
`will cause the device to trigger immediately. effectiver triggering on
`the positive-going edge if a pulse is applied to Pins 4 and 2
`simultaneously.
`
`FREQUENTLY ASKED APPLICATIONS
`QUESTIONS
`The following is a harvest of various maladies. exceptions. and
`idiosyncrasies that may exhibit themselves from time to time in
`
`Exhibit LG 1013 Page 6
`
`Exhibit LG 1013 Page 6
`
`

`

`Application note-
`Philips Semiconductors
`
`AN170
`NE555 and NE556 applications
`
`
`various applications. Rather than cast esperslons. a quick review of
`this list may uncover a solution to the problem at hand.
`1. In the oscillator mode when reset is released the first time
`constant Is approximately twice as long as the rest. Why?
`Answer: In the oscillator mode the tapacltor vultaga fliJctuates
`between 112 and 2c of the supply voltage. When reset is pulled
`down, the capacitor discharges completely. Thus for the first cycle
`it must ohargefrorn ground tea-'3 Vgc. which takes Mice as long.
`
`. What is maximum frequancy of oscillations?
`Answer“. Most devices will oscillate about ‘lMHz. However. in the
`interest of temperature stability. one should operate only up to
`about 500kHz.
`
`. What is temperature drift for osciltator mode?
`Answer: Temperature drift of oscillator models 3 times that of
`one~shot mode due to the addition of a second voltage
`comparator: Frequency always increases with an increasing
`temperature. Therefore it is possible to partially offset this drift
`with an offsetting temperature confident in the extramai
`resistorlcapacitor combination.
`
`. Oscillator exhibits spurious oscillations on crossover points. Why?
`Answer: The- 555 can oscillate clue to feedbackfrom poorer
`supply. Always bypass with sutticient capacitance close to the
`device for all applications.
`
`5. Trying to drive a relay but 555 hangs up. How come?
`Answer: Indutdive feedback. A clamp diode across the coil
`prevents the coil from driving Pin 3 below a negative 0.5V. This
`negative voltage is sufficientin some uses to cause the timer to
`malfunction. The solution is to drive the relay through adiode.
`thus preventing Pin 3 from ever seeing a negative voltage.
`. Double triggering of the ‘l'rL loads sometimes occurs. Why?
`Answer-z Due to the high current capability and fast. rise and fall
`times oithe output. a totem-pole structure different from the ‘I'I'L
`classical structure was used. Near ‘t‘l’Lthreshold this output
`exhibitsa crossover distortion which may double trigger logic. A
`tOOOpF oapadtor from the output to ground will eliminate any
`false triggering.
`
`. What is the longest time I can get out of the timer?
`Answer: Times exceeding an hour are possible. but not always
`practical. Large capacitors with low leakage specs are quite
`expensive. It commas cheaper to use-a countdown scheme [see
`Figure 15) atsorne point. dependent on required accuracy.
`Normally 201p 30 min. Is the longest feasible time.
`
`DESIGN FORMULAS
`Before entering the section on specific applications it is
`advantageous to review the timing l'onnuias. The formulas given
`here apply-to the 555 and 556 devices.
`
`APPLICATIONS
`The timer, slnoe introduction. has stunned the imagination of
`thoUsands. Thus. the ways in which this device has been used are
`far-too numerous to present each one. A review of the basic
`operation and basic modes has previousiy been given. Presented
`
`here are some ingenious applications devised by our applications
`engineers and by some of our custarneis.
`
`Missing Pulse Detectttr
`Using the circuitof Figure 109. the timing cycle is oonilnuousiyreSat
`bythe input pulae'traln. A change in frequency..or a missing pulse.
`allows completion of the timing cycle which causes a change in the
`output level. For this applifion. the time delay should be setto be
`slightly longer than the normal time between pulses. Figure 10b
`shows the actual wavrsfonns seen In this mode of operation.
`
`Figure 11b shows the waveforms of thetimer in Figure 11a when
`used as a dlvlde-by—three circuit. This application makes use of the
`fact that this circuit cannot be retriggered during the timing cycle.
`
`Pulse-Width Modulation (awn)
`In this application. the timer is connected in the monostable mode as
`shown in Figure 12a. The circuit is triggered with a continuous pulse
`train and the threshold voltage is modulated by the signal applied to
`the control voltage terminal (Pin 5). This has the effect of modulating
`the pulse-math as the control voltage varies. Figure 12b shoWs-the
`actual waveform generated with this circuit.
`
`Pulse Position Modulation (PPM)
`This application uses the timer connected for astable (freemnnihgl
`operation. Figure 13s. with a modulating signal again applied to the
`control voltage terminal. Now the pulse position varies with the
`modulating signal. since the threshold-voltage. and hence the time
`delay. is varied. Figure 131:: shows the waveform generated tor
`triangle-Wave modulation signal.
`
`Tone Burst Generator
`The 55$ Dual Timer makes an excellent tone burst generator. The
`first hallI is connected as a one-shot and the second half as an
`oscillator (Figure 14}.
`
`The pulse established by the one-shot tums on the oscillator.
`allowing a burst to be generated.
`
`Sequential Timing
`one feature-oi the dual timer is that by utilizing both halves it is
`possible to obtain sequential timing. By connecting the output of the
`first half to the inputot the second hall via a 0,001uF coupling
`capacitor. sequential timing may be obtained. Delay t1 is determined
`by the firsthalf and l: by the ascend halt delay [Figure 15}.
`
` anneal
`
`Figure 8. driving High Q Inductive Loads
`
`1988 Dec
`
`Exhibit LG 1013 Page 7
`
`Exhibit LG 1013 Page 7
`
`

`

`
`
`
`
`b. “Ii-Lie Time Delay
`
`V
`cc
`
`RA
`
`BB
`
`I:
`
`11 {WWW HIGH} = 0mm * mng
`I1 [OUTPUT LOW) = w map
`=
`7:11 i. tsz [:5QO
`[ . 11F .
`
`R8 + Ra
`A
`Dinlmr CYCLE} =fiA—+§fi;
`d, A533”, 11mins
`
`Application note
`Philips Semiconductors
`
`AN170
`NE555 and NE556 applications
`
`
` r =
`
`
`same
`wrpu-r 5055 Law;
`
`
`
`[I
`
`T (OUTPUT HIGH} ’13 RAG I
`a. Munostahla “In—lug
`
`I
`“CC
`
`RA
`
`i1 {OUTPUT mom = 0’3? HA“
`1| {OUTPUT ILOW} :05? BBC
`T;-t11-.l2.:TCIT§|LPERIflD]
`i‘ * '4’
`
`I G
`
`c. Madman! Duty Cycle Insatiable]
`Figum 9.
`The first half of the timer is started by momentarily connecting Pin 3
`1“cc {5 ' - 1m
`to gmund. When It Is tlmad-aut (datannined by 1.1 R101} iha
`second hair begins. Its durauon Is detennlned by 1.1 R262.
`
`3.00352
`
`
`
`a. Schematic Diagram
`
`I,
`,
`I
`INPUTIWCM .
`
`F171 l“- T'" F—‘Efi
`I TNT '
`'
`
`_._.!-_...._ ..-—-.
`r-
`
`ouqu-VDLTmeicM :
`‘
`
`.
`
`
`
`l—I.
`l:
`
`
`
`camcrma mumsi
`RA 1m 0 = .119 — F
`
`b. Expected Waveforms
`
`Figure 1a.
`
`
`
`1988 Dec:
`
`8
`
`Exhibit LG 1013 Page 8
`
`Exhibit LG 1013 Page 8
`
`

`

`
`
`Philips Semlconduotors Application note
`
`AN1TO
`NE555 and NE556 applications
`
`
`
`
`
`
`*illct: 5TO 15w
`
`I
`
`* Vccrs To an
`
`
` RA
`
`Schematic Die
`INPUT I am
`
`3‘
`INPU'I' mom
`
`m
`
`
`
`
`inoouumon
`INPUT
`a.- Echematlc Diagram
`‘r - In Heroin
`MODULATION INPUT 2W0”
`
`R5-
`
`1:
`
` CAFAOITDR VOLTAGE swan!
`
`
`
`zTiIff'“71""—
`
`.
`gr
`aerPIJrVoLmGE mam ;
`
`|
`
`I = 0.1 MSJBII
`
`RA 11250:: c - flair—— F
`h“ amend wavefom
`Figure 11.
`
`swam
`
`
`
`
` DUTP 34 g
`
`’NEI'SE 555 B
`CLO
`INP
`
`
`
`“A
`
`.
`_
`.
`came VOLTAGE + New
`RA — cm fig —ouurac = ‘0qu
`
`b. Expected wavefanne
`Figure 13.
`
`Long Time Delays
`In the 5561lmer the liming Is a function of the charging rate at the
`extemal capacitor. For long time delays. expansive capacitors with
`extremely low leakage are required. The practicality of the-
`componente involved limits
`
` NOTE:
`
`
`
`All nelsiorveluee are in ohms.
`may
`
`Figure 14. Tone Burs! Generator
`the time between pulses to around Monty minutes.
`
`MODULATION
`INPUT
`
`3!. Schematic Diagram
`
`T: 0.5 H516"
`HDDULATION INPUT ZWCM
`
`
`
`ouwu'rvorrnoe man
`
`
`J J‘
`
`I
`
`
`
`b- 53991-11“ Wavmms
`Figure 12
`
`am“;
`
`To eduieve longer time periods. both halves may be connected In
`tandemwlih a "dlvide-by' network in between.
`
`1968 Dec
`
`9‘
`
`Exhibit LG 1013 Page 9
`
`Exhibit LG 1013 Page 9
`
`

`

`Application note
`Philips SemiconduCtors
`
`AN‘lTG
`NE555 and NE556 applications
`
`
`The first timer section operates in an oscillatory mode with a period
`of title. This signal is then applied to a "divide-by—N" network to give
`an output with the period of i‘li‘i'mr This can then be Used to trigger
`the second half of the 556. The total time is now a function oi N and
`to (Figure 13).
`
`Speed Warning Device
`Utilizing the 'missing pulse detector" concept. a speed Naming
`device. suoh as depicted. hecomese simpieand inexpensive eirwit
`(Figure 17's).
`
`Car Tachometer
`The timer receives pulses from the distributor points. Meter lvl
`receives a calibrated entrant thru Ra when the timer output is high.
`After time-cut. the meter receives no current for that part of the duty
`cycle. integration of the variable duty cycle by the meter movement
`provides a visible indication of engine speed (Figure 18).
`
`that capacitor C can charge. When capacitor voltage reaches the
`timer's control voltage {633Vch the flip-flop resets and the
`transistor conducts. discharging the capacitor [Figure 191‘
`
`Greater linearity n be achieved by substituting a constantaourrent
`source for the itequeney adjust resistor (Rt
`
`
`
`Oscilloscope-Triggered Sweep
`The slits-timer holds down the cost of adding a triggered sweep to
`an economy oscilloscope. The circuits input op amp triggers the
`timer. setting Its flip-flop. and cutting off its discharge transistor so
`LONG 11MB SOUNTER
`(HOURS. DflYE. WEEKS“ ETC.)
`
`
` INPUT FROM
`
`'Nflel coun‘rER
`
`
`
`
` NIIM COUNTER
`Foe LONGER TIMES
` NOTE:
`All resistor value! It: In chills.
`:
`
`
`swam
`
`
`
`
`b. Operating Waveforms
`Speed Warning Device
`SLMWO
`a. Schematic eft‘ipeed Warning Device
`
`
`
`Figure 17.
`
`1985 Dec
`
`10
`
`Exhibit LG 1013 Page 10
`
`Exhibit LG 1013 Page 10
`
`

`

`
`
`Philips Semicondudors Applicaflun note
`
`AN170
`NE555 and NE556 applications
`
`
`.-
`DIWBUTDR
`POINTS
`
`RE
`MK
`CALIBRATION
`DI:
`
`Elll'llk
`FULL
`
`NOTE:
`—
`WLE
`All 'I'naim valuas arairl ahrnx.
`'
`smog”
`
`
`FROM
`VERTICAL
`MIPUFIER
`
`
`
`
`
`
`
`
`
`
`NOTE;
`
`NI msmruam: m In ohms.
`
`SL009”
`
`
` NOTE: _
`
`fill minim values arch-Hum.
`
`'Flgure 20. Square Wava Tone Burst Generator
`
`19831330
`
`11
`
`Exhibit LG 1013 Page 11
`
`Exhibit LG 1013 Page 11
`
`

`

`e GND OUT
`
`(:12
`“OTEE'.
`0.1 11F
`All result-Jr values are in ohms
`
`‘Shlier Magnetics
`o -1§ V GUT
`
`Davina. Calif.
`SL009?!
`(2131331aa115
`
`
`
`PULSE GENERATOR
`GR SYSTEM BLOCK
`
`
`'Vm is Ilrniled to 2 diode drops within ground or below Vac.
`
`
`
`Philips Semiconductors Application note
`
`AN‘170
`NE555 and NE556 applications
`
`
`
`
`REMOTE enumown
`
`PEAKIWEREE 11w
`
`1. 15V UHREG
`
`a +1SVDLIT
`
`C11.
`Elli-IF
`
`
`
`NOTES:
`Ail mislor values In ohms;
`
`Fig