111111111111 m 1111111111111111111111111111111111111111111111111111
`US005682484A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,682,484
`Oct. 28, 1997
`
`5,502,824
`5,519,839
`5,526,017
`5,530,902
`5,533,205
`5,557,757
`5,564,001
`
`3/1996 Heil ......................................... 395/293
`5/1996 Culley et al. .
`6/1996 Wilkie ..................................... 345/115
`6/1996 McRoberts et al ..
`7/1996 Blackledge, Jr. et al ..
`9/1996 Gephardt et al ..
`10/1996 Lewis .
`
`OTHER PUBLICATIONS
`
`PCI Local Bus -PC/ Multimedia Design Guide -Revision
`1.0 -Mar. 29, 1994, 43 pages.
`
`Primary Examiner-Jack B. Harvey
`Assistant Examiner-Ario Etienne
`Attorney, Agent, or Finn-Conley, Rose & Tayon; Jeffrey C.
`Hood
`
`[57]
`
`ABSTRACT
`
`A computer system optimized for real-time applications
`which provides increased performance over current com(cid:173)
`puter architectures. The system includes a standard local
`system bus, such as the PCI bus, and also includes a
`dedicated real-time bus or multimedia bus. Thus multimedia
`devices such as video cards, audio cards, etc., as well as
`communications devices, transfer real-time data through a
`separate bus without requiring arbitration for the PCI bus.
`The computer system of the present invention thus provides
`much greater performance for real-time applications than
`prior systems. In various embodiments, multimedia devices
`transmit addressing and control information for a multime(cid:173)
`dia bus transfer either over the PCI bus or using a separate
`serial control channel. The multimedia bus may also com(cid:173)
`prise separate multimedia channels for different data types.
`Methods are also disclosed for transferring periodic multi(cid:173)
`media data over the multimedia bus.
`
`8 Claims, 25 Drawing Sheets
`
`110
`
`MAIN
`I.IEMORY
`
`08
`
`107
`
`144
`
`146
`
`I.IULTIMEDlA
`DEVICE
`
`l,IULTII.IEDIA
`DEVICE
`
`United States Patent [19]
`Lambrecht
`
`[54]
`
`SYSTEM AND METHOD FOR
`TRANSFERRING DATA STREAMS
`SIMULTANEOUSLY ON MULTIPLE BUSES
`IN A COMPUTER SYSTEM
`
`[75]
`
`Inventor: Andy Lambrecht, Austin, Tex.
`
`[73] Assignee: Advanced Micro Devices, Inc.,
`Sunnyvale, Calif.
`
`[21] Appl. No.: 559,664
`
`Nov. 20, 1995
`[22] Filed:
`Int. Cl.6
`...................................................... G06F 13/00
`[51]
`[52] U.S. CI . .......................... 395/308; 395/306; 395/841;
`395/281; 395/154
`[58] Field of Search ..................................... 395/306, 308,
`395/847, 841, 855, 858, 309, 281, 822,
`840, 162, 163, 200.09, 154, 200.04, 200.12;
`370/85.13, 85.9, 85.11; 364/514; 463/43
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,245,344
`4,991,169
`5,072,442
`5,208,745
`5,245,322
`5,274,763
`5,274,784
`5,325,423
`5,345,566
`5,404,463
`5,404,465
`5,450,551
`5,487,167
`
`1/1981 Richter ................................... 371/68.1
`2/1991 Davis et al . .
`12/1991 Todd ....................................... 370/265
`5/1993 Quentin et al ..
`9/1993 Dinwiddie, Jr. et al ..
`12/1993 Banks .
`12/1993 Arimilli et al. ......................... 395/306
`6/1994 Lewis .
`9/1994 Tanji et al. .............................. 395/308
`4/1995 McGarvey .............................. 395/308
`4/1995 Novakovich et al ................... 395/308
`9/1995 Amini et al ..
`1/1996 Dinallo et al ..
`
`102
`
`CPU
`
`06
`
`PCI
`104
`BRIDGE
`1=====1 CHIPSET
`
`142
`
`MULTIMEDIA
`DEVICE
`
`50
`
`152
`
`AT
`BRIDGE
`
`AT BUS
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 1
`
`

`

`.102
`
`CPU
`
`.106
`r
`
`(104
`
`PCI
`BRIDGE
`CHIPSET
`ARB
`LOGIC ... ~ 107
`
`i1os
`
`110
`
`MAIN
`MEMORY
`
`(142
`
`,144
`
`,146
`
`MULTIMEDIA
`DEVICE
`I
`I
`170"
`
`/
`
`\ ,
`
`,
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`
`11
`AT
`BRIDGE
`
`I
`
`11
`\ AT BUS
`
`I
`
`I
`
`~
`
`MULTIMEDIA
`DEVICE
`I
`
`I
`17()
`
`(130
`REAL-TIME BUS (MULTIMEDIA BUS)
`
`PCI EXPANSION BUS
`
`(120
`
`MULTIMEDIA
`DEVICE
`I
`I
`170"
`
`,
`
`l ,
`
`,
`l
`
`FIG. 1
`
`~ •
`rJJ.
`•
`
`~ = "*-
`~ a
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`0
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`QO
`~
`
`~
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 2
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 2 of 25
`
`5,682,484
`
`142
`
`l
`
`210
`,
`
`DSP
`
`170
`.......
`
`PCI EXPANSION
`172.,. BUS INTERFACE
`
`MULTIMEDIA ~ 17 4
`BUS
`INTERFACE
`
`FIG. 2
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 3
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 3 of 25
`
`5,682,484
`
`MULTIMEDIA
`BUS lRANSFER
`
`302
`
`TRANSFER CONTROL
`INFORMATION ON
`PCI EXPANSION BUS
`
`304
`
`TRANSFER DATA
`ON MULTIMEDIA
`BUS
`
`END
`
`FIG. 3A
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 4
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 4 of 25
`
`5,682,484
`
`PCI/MULTIMEDIA
`BUS TRANSFER
`
`312
`
`TRANSFER CONTROL
`INFORMATION ON
`PCI EXPANSION BUS
`
`314
`
`316
`
`TRANSFER HIGH
`BANDWIDTH
`TRANSFER FlAG
`
`TRANSFER DATA ON
`MULTIMEDIA BUS AND
`PCI EXPANSION BUS
`DATA LINES
`
`FIG. 38
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 5
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 5 of 25
`
`5,682,484
`
`MULTIMEDIA
`BUS TRANSFER
`
`322
`
`TRANSFER CONTROL
`INFORMATION ON
`PCI EXPANSION BUS
`
`324
`
`TRANSFER
`PERIODIC DATA
`REQUEST
`
`N
`
`y
`
`SET PERIODIC
`TRANSFER FLAG
`TO NO
`
`332
`
`338
`
`SET PERIODIC
`TRANSFER FLAG
`TO YES
`
`PERFORM SINGLE
`TRANSFER
`
`334
`
`340
`
`PERFORM PERIODIC
`TRANSFERS
`
`END
`
`END
`
`FIG. 3C
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 6
`
`

`

`.102
`
`CPU
`
`.106
`
`PCI
`BRIDGE
`CHIPSET
`
`110
`
`MAIN
`MEMORY
`
`/VEOO
`
`MULTIMEDIA BUS
`CONNECTOR SLOT 132
`/V
`
`147
`
`MOTHER
`MOTHER
`BOARD
`BOARD
`MM DEVICE MM DEVICE
`
`120
`
`PCI EXPANSION BUS
`
`AT
`BRIDGE
`
`PCI EXPANSION BUS
`/
`- - - - - - - - - - - - -~NNE~R~~ 1~ - - - -
`FIG.
`
`4
`
`•
`~
`
`~ • rJl
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`
`0 p.
`J~
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`00
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`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 7
`
`

`

`U.S. Patent
`U.S. Patent
`
`Oct. 28, 1997
`Oct. 28, 1997
`
`Sheet 7 of 25
`Sheet 7 of 25
`
`5,682,484
`5,682,484
`
`LO
`• c.,
`IG,
`LL
`
`S F
`
`
`
`BUSCONNECTOR
`
`REAL—TIME
`
`404
`
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`
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`• ---
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`402APCl
`
`EXPANSIONBUSCONNECTOR
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 8
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 8
`
`

`

`CPU
`
`r- -- -
`
`PCI
`BRIDGE
`CHIPSET
`ARB
`LOGIC ........ 107A
`
`MAIN
`MEMORY
`
`!142
`
`[144
`
`,146
`
`MULTIMEDIA
`DEVICE
`
`MULTIMEDIA
`DEVICE
`
`MULTIMEDIA
`DEVICE
`
`,
`\ ,.
`
`,
`~ ,
`
`11
`AT
`BRIDGE
`
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`
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`
`REAL-TIME BUS (MULTIMEDIA BUS)
`
`PCI EXPANSION BUS
`
`i120
`
`t130A,,
`( ,,
`
`~
`
`~
`
`FIG. 6
`
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`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 9
`
`

`

`.102
`
`CPU
`
`,- .
`106
`
`,104
`
`PCI
`BRIDGE
`CHIPSET
`ARB
`LOGIC ....... 107
`
`100
`1
`
`.110
`
`MAIN
`MEMORY
`
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`
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`
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`
`MULTIMEDIA
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`I
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`
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`
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`
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`
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`
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`
`REAL-TIME BUS (MULTIMEDIA BUS)
`I
`I
`I
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`
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`PCI EXPANSION BUS
`
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`
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`
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`(
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`
`FIG. 7
`
`Cj
`•
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`,l:ii,.
`~
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`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 10
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 10 of 25
`
`5,682,484
`
`,210
`
`DSP
`ENGINE
`
`512
`
`22
`
`PCI EXPANSION
`BUS INTERFACE
`
`MULTIMEDIA
`BUS
`INTERFACE
`
`CONTROL
`CHANNEL.
`INTERFACE
`
`FIG. 8
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 11
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 11 of 25
`
`5,682,484
`
`MULTIMEDIA
`BUS TRANSFER
`
`542
`
`TRANSFER CONTROL
`INFORMATION ON
`CONTROL CHANNEL
`
`544
`
`TRANSFER DATA
`ON MULTIMEDIA
`BUS
`
`END
`
`FIG. 9A
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 12
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 12 of 25
`
`5,682,484
`
`MULTIMEDIA
`BUS TRANSFER
`
`552
`
`TRANSFER CONTROL
`INFORMATION ON
`. CONTROL CHANNEL;
`GAIN ACCESS
`
`554
`
`TRANSFER PERIODIC
`DATA REQUEST TO
`RECEMNG DEVICE
`
`N
`
`y
`
`SET PERIODIC
`TRANSFER FLAG
`TO NO
`
`562
`
`558
`
`SET PERIODIC
`TRANSFER FlAG
`TO YES.
`
`PERFORM SINGLE
`TRANSFER
`
`564
`
`560
`
`PERFORM PERIODIC
`TRANSFERS
`
`END
`
`END
`
`FIG. 9B
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 13
`
`

`

`.102
`
`CPU
`
`106
`t
`PCI BRIDGE
`CHIPSET
`
`t104
`
`;oe
`
`ARB
`LOGIC ""- 107
`
`.110
`
`MAIN
`MEMORY
`
`142B
`1
`MULTIMEDIA
`DEVICE
`I
`I
`I
`612'
`
`I
`
`,144B
`MULTIMEDIA
`DEVICE
`
`I
`612"
`
`r146B
`MULTIMEDIA
`DEVICE
`I
`
`I
`612
`
`{614
`ARBITRA-
`TION
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`{60 2
`11
`V / / / / / / / / / / / / / / / / / /A
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`
`FIG. 10
`
`~ •
`00
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`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 14
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 14 of 25
`
`5,682,484
`
`MULTIMEDIA BUS
`INTERFACE
`
`f 174A
`
`f644
`
`TIMERS/
`COUNTERS
`
`TIME
`SLOTIING
`LOGIC
`
`PROGRAMMABLE
`TIME SLOT
`REGISTERS
`
`MM BUS
`MONITORING
`LOGIC
`
`BUS
`TRANSCEIVERS
`BUFFERS
`
`f652
`
`COWSION
`DETECTION
`LOGIC
`
`FIG. 11
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 15
`
`

`

`TIME
`
`lvlvlvlvlvlvlAlclvlvlvlvlvlvlAlcl
`
`A) EQUAL SIZED TIME SLOTS WITH NUMBER OF TIME SLOTS
`ALLOCATED TO STREAMS IN PROPORTION TO REQUIRED BANDWIDTH.
`V-VIDEO, A=AUDIO, C=COMMUNICATION
`
`FIG. 12A
`
`GB
`
`V
`
`GB
`
`V
`
`B) NON-EQUAL SIZED TIME SLOTS WITH SIZE OF TIME SLOT
`ALLOCATED TO STREAMS IN PROPORTION TO REQUIRED BANDWIDTH.
`V=VIDEO, A=AUDIO, C=COMMUNICATION
`FIG. 12B
`
`~ •
`7JJ. •
`
`~ = '""'" ~ a
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`
`FIG. 12
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 16
`
`

`

`.102
`
`CPU
`
`106
`r--
`
`r104
`
`PCI
`BRIDGE
`CHIPSET
`ARB
`LOGIC ........ 107
`
`t10B
`
`110
`
`MAIN
`MEMORY
`
`,144
`
`,146
`
`MULTIMEDIA
`DEVICE
`
`MULTIMEDIA
`DEVICE
`
`702
`1/0
`PROCESSOR
`I
`
`/130
`REAL-TIME BUS (MULTIMEDIA BUS)
`
`PCI EXPANSION BUS
`
`)20
`
`,142
`
`MULTIMEDIA
`DEVICE
`
`,/
`
`\ ,
`
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`
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`
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`
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`
`~ •
`00
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`
`,,
`C
`
`IG. 13
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 17
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 17 of 25
`
`5,682,484
`
`f 712
`
`DATA BUS
`REGISTERS
`
`DATA
`RATE
`REGS
`
`DATA
`PERIODIC
`REGS
`
`DATA
`SOURCE
`DESTIN
`REGS
`
`DATA
`TRANSFER
`CONTROL
`LOGIC
`
`BYTE
`SLICING
`LOGIC
`
`FIG. 14
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 18
`
`

`

`102
`
`CPU
`
`1104
`
`106B
`r
`CHIPSET [J'" 164 108
`1
`PCI
`BRIDGE
`
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`
`110
`
`MAIN
`MEMORY
`
`,
`\
`,
`
`~
`
`~
`,
`
`151
`\
`ARB
`LOGIC
`I
`
`MULTIMEDIA
`DEVICE
`
`2 1....r
`
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`
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`
`{
`I
`
`PCI EXPANSION BUS
`
`I I
`MULTIMEDIA f"\..-160
`MEMORY
`
`162
`
`I I
`
`i130
`REAL-TIME BUS (MULTIMEDIA BUS
`
`,I
`
`C
`I
`
`MULTIMEDIA
`DEVICE
`
`MULTIMEDIA
`DEVICE
`
`142B
`
`144B
`
`146B
`
`FIG. 15
`
`~ •
`rJl
`•
`~ = f""t'.
`("t) a
`
`0 p.
`--~
`......
`~ ......
`
`ga
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`......
`00
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`
`Ol
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`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 19
`
`

`

`,..- - - - - -
`
`- - - - - -- -- - - - -- - -
`/106
`
`/102
`
`- -- -- --
`i110
`
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`
`BRIDGE
`LOGIC
`
`MAIN
`MEMORY
`
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`
`~ ;
`
`122A
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`EXPANSION
`BUS
`CONNECTOR
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`
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`
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`MULTIMEDIA BUS
`~ CONNECTOR SLOT
`
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`
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`BOARD
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`DEVICE')_
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`
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`MEMORY
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`j
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`FIG.
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 20
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 20 of 25
`
`5,682,484
`
`MULTIMEDIA MEMORY
`ADDRESS SPACE
`
`GENERAL
`ADDRESS
`SPACE
`
`GENERAL
`ADDRESS
`SPACE
`
`FIG. 1 7
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 21
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 21 of 25
`
`5,682,484
`
`CPU TRANSFERS
`MULTIMEDIA DATA
`TO MAIN MEMORY
`
`I
`
`CPU TRANSFERS
`
`OMA ENGINE
`
`I
`
`602 -
`504 - DATA STRUCTURE TO
`506 -
`608 -
`610 - DATA FROM MAIN MEMORY
`512 - ACCESSES MULTIMEDIA
`
`DMA ENGINE PRIORmZES
`DATA STRUCTURE
`IN COMMAND QUEUE
`
`I
`
`OMA ENGINE
`ARBITRATES FOR
`MAIN MEMORY
`
`I
`DMA ENGINE
`TRANSFERS MULTIMEDIA
`
`TO MULTIMEDIA MEMORY
`I
`MULTIMEDIA DEVICE
`
`DATA FROM
`MULTIMEDIA MEMORY
`I
`
`514 .........
`
`MULTIMEDIA ENGINE
`PERFORMS OPERATIONS
`USING MULTIMEDIA DATA
`
`I
`
`516 - GENERATES MULTIMEDIA
`
`MULTIMEDIA ENGINE
`
`OUTPUTS
`
`FIG. 18
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 22
`
`

`

`102
`-
`
`CPU
`
`,106
`
`1932
`PCI
`BRIDGE
`
`1934
`MEMORY
`CONTROUER
`
`. 110
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`
`MAIN
`MEMORY
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`(916
`
`1
`914
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`d •
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`~
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`GRAPHICS
`I
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`l
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`I
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`FIG.
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`908
`
`'
`l
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`MPEG
`DECODER
`I
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`l
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`
`CD-ROM
`
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`
`I
`
`I
`'
`l
`940
`PCI EXPANSION BUS
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 23
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 23 of 25
`
`5,682,484
`
`902 I
`
`r210
`
`DSP
`
`942
`r
`I
`
`PCI EXPANSION
`BUS INTERFACE
`
`940
`I
`
`944
`r
`)
`UEMORY
`DATA
`CHANNEL
`INTERFACE
`
`FIG. 20
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 24
`
`

`

`!102
`
`CPU
`
`I
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`06
`PCI BRIDGE
`CHIPSET
`
`;o4 I
`MODE
`gso "HLOGIC
`
`108
`
`107
`
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`
`MULTIMEDIA
`DEVICE
`I
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`l_
`962"
`
`142D
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`MULTIMEDIA
`DEVICE
`J
`l
`I
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`FIG. 21
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 25
`
`

`

`U.S. Patent
`
`Oct. 28, 1997
`
`Sheet 25 of 25
`
`5,682,484
`
`142D
`
`i
`
`,210
`
`DSP
`
`962
`I
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`r964
`PCI EXPANSION
`PCI EXPANSION BUS MULTIMEDIA
`BUS INTERFACE MODE INTERFACE
`LOGIC
`CIRCUITRY
`
`FIG. 22
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 26
`
`

`

`5,682,484
`
`1
`SYSTEM AND METHOD FOR
`TRANSFERRING DATA STREAMS
`SIMULTANEOUSLY ON MULTIPLE BUSES
`IN A COMPUTER SYSTEM
`
`FIELD OF THE INVENTION
`
`The present invention relates to a computer system which
`includes a system expansion bus such as the Peripheral
`Component Interconnect (PCI) bus and also includes a
`separate real-time or multimedia bus which transfers peri(cid:173)
`odic and/or multimedia stream data for increased system
`performance for multimedia and real-time applications.
`
`2
`hardware devices are generally required to share bus usage
`with non-real time devices.
`Also, multimedia hardware devices generally do not make
`efficient usage of system resources. As an example, multi-
`5 media hardware cards typically include their own memory in
`addition to system memory. For example, video accelerator
`cards are typically configured with one to four Megabytes of
`video RAM. Audio cards, video capture cards, and other
`multimedia cards are also generally configured with dedi-
`10 cated on-board memory. This requirement of additional
`memory adds undesirable cost to the system.
`As multimedia applications become more prevalent, mul(cid:173)
`timedia hardware will correspondingly become essential
`components in personal computer systems. Therefore, an
`15 improved computer system architecture is desired which is
`optimized for real-time multimedia and communications
`applications as well as for non-realtime applications. In
`addition, improved methods are desired for transferring
`real-time data between multimedia devices.
`Applicant is aware of two new graphics standards from
`the Video Electronics Standards Association (VESA) which
`are designed to improve digital video transfers in computer
`systems. These two standards are referred to as the VESA
`advanced feature connector (VAFC) and the VESA media
`channel (VMC). A third standard has been proposed by Intel
`and ATI referred to as the shared frame buffer interconnect
`(SFBI).
`The V AFC standard is a 32 bit replacement for prior 8 bit
`VGA connectors which supports video at much higher
`resolutions and in better color. The VMC standard also offers
`a 32 data path and supports up to 15 video streams simul-
`taneously. The VMC standard comprises a dedicated chan(cid:173)
`nel for real-time video, and peripherals can communicate
`independently without slowing the system CPU. The VMC
`standard also decouples the memory subsystem from the
`video transfer specification, allowing graphics board manu-
`facturers to offer a variety of boards with differing types of
`graphics memory.
`The SFBI standard combines frame buffers and memory
`use by each multimedia system into a single shared memory
`pool. The SFBI standard also includes a protocol for arbi(cid:173)
`trating among devices attempting to access the memory.
`However, one drawback to this standard is that the standard
`is designed to maintain all of the components on a single
`45 board. The SFBI standard does not provide an external
`feature connector unless SFBI cards are connected to
`another device over the host bus. In addition, SFBI cards can
`include a VMC or VAFC connector for connecting to a VMC
`or V AFC card.
`SUMMARY OF THE INVENTION
`The present invention comprises a computer system and
`method optimized for real-time applications which provides
`increased performance over current computer architectures.
`55 The system preferably includes a standard local expansion
`bus or system bus, such as the PCI bus, and also includes a
`dedicated real-time bus or multimedia bus. Thus multimedia
`devices, such as video devices, audio devices, etc., as well
`as communications devices, transfer real-time data through
`a separate bus without requiring arbitration for or usage of
`the PCI bus. The computer system of the present invention
`thus provides much greater performance for real-time appli(cid:173)
`cations than prior systems. In an alternate embodiment, the
`computer system only includes one or more dedicated
`real-time buses which replace the PCI bus.
`In the preferred embodiment. the computer system com(cid:173)
`prises a CPU coupled through chip set or bridge logic to
`
`25
`
`20
`
`DESCRIPTION OF THE RELATED ARf
`Computer architectures generally include a plurality of
`devices interconnected by one or more various buses. For
`example, modem computer systems typically include a CPU
`coupled through bridge logic to main memory. The bridge
`logic also typically couples to a high bandwidth local
`expansion bus or system expansion bus, such as the periph(cid:173)
`eral component interconnect (PCI) bus or the VESA (Video
`Electronics Standards Association) VL bus. Examples of
`devices which can be coupled to local expansion buses
`include video accelerator cards, audio cards, telephony
`cards, SCSI adapters, network interface cards, etc. An older
`type expansion bus is generally coupled to the local expan(cid:173)
`sion bus for compatibility. Examples of such expansion
`buses included the industry standard architecture (ISA) bus, 30
`also referred to as the AT bus, the extended industry standard
`architecture (EISA) bus, or the microchannel architecture
`(MCA) bus. Various devices may be coupled to this second
`expansion bus, including a fax/modem, sound card, etc.
`Personal computer systems were originally developed for 35
`business applications such as word processing and
`spreadsheets, among others. However, computer systems are
`currently being used to handle a number of real time
`applications, including multimedia applications having
`video and audio components, video capture and playback, 40
`telephony applications, and speech recognition and
`synthesis, among others. These real time applications typi(cid:173)
`cally require a large amount of system resources and band(cid:173)
`width.
`One problem that has arisen is that computer systems
`originally designed for business applications are not well
`suited for the real-time requirements of modem multimedia
`applications. For example, modem personal computer sys(cid:173)
`tem architectures still presume that the majority of applica(cid:173)
`tions executing on the computer system are non real-time 50
`business applications such as word processing and/or
`spreadsheet applications, which execute primarily on the
`main CPU. In general, computer systems have not tradition(cid:173)
`ally been designed with multimedia hardware as part of the
`system, and thus the system is not optimized for multimedia
`applications. Rather, multimedia hardware is typically
`designed as an add-in card for optional insertion in an
`expansion bus of the computer system, wherein the expan(cid:173)
`sion bus is designed for non-realtime applications.
`In many cases, multimedia hardware cards situated on an 60
`expansion bus do not have the required system bus band(cid:173)
`width or throughput for multimedia data transfers. For
`example, a multimedia hardware card situated on the PCI
`expansion bus must first arbitrate for control of the PCI bus
`before the device can begin a data transfer or access the 65
`system memory. In addition, since the computer system
`architecture is not optimized for multimedia, multimedia
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 27
`
`

`

`5,682,484
`
`10
`
`25
`
`3
`main memory. The bridge logic couples to a local bus such
`as the PCI bus. The computer system also includes a
`real-time expansion bus or multimedia bus for transferring
`real-time or multimedia data. A plurality of multimedia
`devices, such video devices, audio devices, MPEG encoders
`and/or decoders, and/or communications devices, are
`coupled to each of the PCI bus and the multimedia bus. In
`one embodiment, the multimedia bus transfers only periodic
`stream data, such as audio data at 44,100 samples per
`second, video data at 30 frames per second, or real-time
`communication streams at rates dependent on the transport
`media.
`The computer system preferably includes a plurality of
`PCI expansion bus connector slots connected to the PCI bus
`for receiving add-in devices, and also preferably comprises 15
`one or more multimedia bus connector slots corresponding
`to respective ones of the PCI expansion bus connector slots.
`Thus, in one embodiment, the PCI bus and the multimedia
`bus are comprised on the motherboard and include respec(cid:173)
`tive connector slots for receiving add-in cards. Multimedia 20
`device expansion cards each include two connectors which
`correspond to the PCI bus and the multimedia bus.
`Alternatively, the multimedia devices are comprised directly
`on the motherboard and connect directly to the PCI bus and
`the multimedia bus, and connector slots are not used.
`In one embodiment, the multimedia bus comprises pri(cid:173)
`marily or only data lines. In this embodiment, control
`information for the periodic stream transfers is transferred
`on the PCI bus by a sourcing device, or is transferred by the
`CPU to the bridge logic. Thus multimedia data transfers 30
`initially involve the transfer of control or setup information
`on the PCI bus, or transfer of control or setup information by
`the CPU, to set up the transfer. This transfer of control
`information is followed by the transfer of the periodic data
`streams on the multimedia bus. Alternatively, once control/ 35
`setup information has been used to set up the transfer, the
`periodic data stream may occupy both the PCI data lines and
`the multimedia bus for increased data throughput. In this
`embodiment, the transferring or source device transfers a
`multiple bus transfer request which requests simultaneous 40
`transfers on both the PCI bus and the multimedia bus. If the
`multiple bus transfer request is accepted, then the source
`device transfers data on both the PCI bus and the multimedia
`bus.
`The present invention further includes an improved
`method for transferring periodic data streams on a bus in the
`computer system, such as periodic video streams or periodic
`audio streams. According to this method, the transferring
`device first transmits addressing and control information to
`set up the transfer. The transferring device then transmits a
`periodic transfer data request to the receiving device. The
`periodic transfer data request includes information regarding
`the frequency and amount of the periodic transfers. The
`receiving device determines if it can guarantee availability at
`the periodic time frequencies requested by the transferring 55
`device. If the receiving device indicates availability for the
`periodic transfers, the transferring device sets a periodic
`transfer flag. The transferring device then performs the
`periodic transfers to the receiving device at the specified
`time frequency. If the receiving device does not indicate 60
`availability for the periodic transfers, the transferring device
`performs only a single transfer and is required to transfer
`control information at the beginning of each subsequent
`periodic transfer.
`In a second embodiment, the computer system includes a 65
`dedicated control channel separate from the PCI bus and the
`multimedia bus for transferring control information for
`
`4
`multimedia bus data transfers. The control channel is pref(cid:173)
`erably a serial bus. Alternatively, the control channel is a
`4-bit, 8-bit or 16-bit bus. Thus a multimedia data transfer
`initially involves the transfer of control information on the
`5 dedicated control channel followed by the transfer of the
`periodic data streams on the multimedia bus.
`In a third embodiment, the multimedia bus comprises
`separate channels for different data types. In the preferred
`embodiment, the computer system includes a first video data
`channel for. transferring video and/or graphics information,
`a second audio channel for transferring audio information,
`and optionally a third channel for transferring communica(cid:173)
`tions information. The video channel is preferably 32 bits,
`24 bits, or 16 bits. Alternatively, the video channelis an 8-bit
`bus or a very high speed serial bus. The audio channel is
`preferably 16 bits or 8 bits. Alternatively, the audio channel
`is also a 32-bit bus or a very high speed serial bus. The
`communications channel is also preferably either 16 or 8
`bits. This third embodiment may use the PCI bus for control
`information transfers, or may use a separate control channel
`separate from the PCI bus and the multimedia bus for
`transferring control information for the periodic stream
`transfers.
`In a fourth embodiment, each multimedia device has a
`high speed link directly to system memory, which is pref-
`erably single or multiple ported memory. These individual
`links are preferably high speed serial interconnects but,
`alternatively, may be 4-bit, 8-bit, 16-bit, 24-bit, 32-bit,
`64-bit or any combination thereof. In this embodiment,
`intelligent buffering is preferably implemented within the
`core logic, and arbitration for access to main memory is
`preferably implemented within the core logic. Each of the
`multimedia devices uses its dedicated memory data channel
`to perform data accesses and transfers directly to the main
`memory, bypassing PCI bus arbitration and PCI bus cycles.
`Alternatively, each of the multimedia devices includes a
`high speed memory channel directly to the memory con(cid:173)
`troller in the core logic for accessing system memory.
`In a fifth embodiment, the multimedia bus is time sliced
`wherein time slices or time slots are allocated in proportion
`to the required bandwidth. In one embodiment, the time
`slices are each a constant size and a number of the equal
`sized time slots are allocated to respective data streams in
`45 proportion to the required bandwidth. In this embodiment.
`for example, video data streams may be allocated more time
`slots than audio data streams because of the increased data
`transfer band width requirements of video streams.
`Alternatively, the time slots are not equally sized, but rather
`50 are dynamically sized or allocated to data streams in pro(cid:173)
`portion to the required bandwidth.
`In a sixth embodiment, multimedia devices that connect
`to the multimedia bus include intelligent controller circuitry
`which includes knowledge of the respective time slice
`allocated to the multimedia device. In this embodiment,
`arbitration for the multimedia bus is not required. Rather, a
`multimedia device which is a transmitter of video data
`monitors the bus and includes controller circuitry which
`begins transmitting the video data when the device's respec(cid:173)
`tive time slot occurs. A corresponding receiver device also
`knows that the current time slot is a video time slot and
`monitors the bus to receive the data.
`In this embodiment, the interface circuitry of each of the
`multimedia devices are programmed at boot time for a static
`allocation of time slots. Alternatively, the interface circuitry
`in the multimedia devices is dynamically programmed by a
`central controller dependent upon the mix of real-time
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1005, p. 28
`
`

`

`5,682,484
`
`5
`
`30
`
`5
`processes and applications and the corresponding data trans(cid:173)
`fer bandwidth requirements. For example, the CPU may
`program each of the multimedia devices with a respective
`time slot at power-on. Alternatively, the CPU dynamically or
`heuristically allocates time slot based on bandwidth require-
`ments.
`In one embodiment of the invention, the computer system
`includes a centralized multimedia I/0 processor which oper(cid:173)
`ates to direct or ''pull" data stream infonnation through the
`system. The multimedia I/0 processor is programmed with
`knowledge of the various data rates, data periodicity, data
`sources and destinations, and coordinates all transfers within
`the system. Thus, the multimedia I/0 processor creates
`' connections between two or more devices and sets up
`transfers between devices. The centralized multimedia I/0
`processor of the present invention may be used exclusively
`in the multimedia bus or may be used on a standard PCI bus.
`In one embodiment, the centralized multimedia I/0 pro(cid:173)
`cessor byte slices the multimedia bus to allow different data
`streams to use different byte channels simultaneously. Thus
`the byte sliced multimedia bus allows different peripherals
`to share the bus simultaneously. The centralized multimedia
`JJO processor thus may assign one data stream to a subset of
`the total byte lanes on the multimedia bus, and fill the unused
`byte lanes with another data stream. For example, with a 25
`32-bit multimedia bus, if an audio data stream is only 16 bits
`wide and thus only uses half of the multimedia data bus, the
`multimedia bus intelligently allows data stream transfers on
`the unused bits of the bus. In this embodiment, the central(cid:173)
`ized multimedia JJO processor includes knowledge of the
`destinations and allows transfers to occur without addressing
`information.
`In one embodiment of the invention, the computer system
`includes a multimedia memory coupled to each of the PCI
`local expansion bus and the real-time bus. One or more 35
`multimedia devices may be coupled to the PCI local expan(cid:173)
`sion bus and the real-time bus. Each of these devices
`accesses the multimedia memory to retrieve necessary code
`and data to perform respective operations. The multimedia
`devices preferably include an arbitration protocol for access- 40
`ing the multimedia memory using the real-time bus.
`In one embodiment, the system bus (preferably PCI)
`implements a new mode of operation specifically for real(cid:173)
`time transfers. A signal (or signals) is used to indicate that
`the system bus should be placed in a special real time mode. 45
`When not in special real time mode, the system bus operates
`as usual. The real time mode is optimized for the transfer of
`high bandwidth real-time infonnation.
`Therefore, the present invention comprises a novel com(cid:173)
`puter system architecture and method which provides one or 50
`more real-time or multimedia buses, optionally with a local
`expansion bus, to increase the perfonnance of real-time
`peripherals and applications. The multimedia bus of the
`present invention provides improved data transfers perfor(cid:173)
`