David H. Albonesi
`
`School of Electrical and Computer Engineering
`333 Rhodes Hall, Cornell University
`Ithaca, NY 14853
`(607) 254-5473
`david.albonesi@cornell.edu
`
`Education
`1996
`Doctor of Philosophy, Computer Engineering, University of Massachusetts Amherst
`
`1986
`
`1982
`
`Master of Science, Electrical Engineering, Syracuse University
`
`Bachelor of Science, Electrical Engineering, University of Massachusetts Amherst
`
`Professional Experience
`2010-
`Professor, Electrical and Computer Engineering, Cornell University
`2013-16 Associate Director, Electrical and Computer Engineering, Cornell University
`2004-10 Associate Professor, Electrical and Computer Engineering, Cornell University
`
`2001-04 Associate Professor, Electrical and Computer Engineering, University of Rochester
`1996-2001 Assistant Professor, Electrical and Computer Engineering, University of Rochester
`
`1993-96 Research Engineer, Electrical and Computer Engineering, University of Massachusetts
`Digital systems consulting, system administration, and evaluation of benchmark perfor-
`mance of supercomputers and workstations.
`
`1992-95
`
`Lecturer, Electrical and Computer Engineering, University of Massachusetts
`Revamped undergraduate digital design and microprocessor systems laboratory courses.
`
`1986-92
`
`1982-86
`
`Section Manager/Principal Engineer, Processor Development, Prime Computer, Inc.
`Project manager and computer architect for high performance uniprocessor and multi-
`processor designs implemented using CMOS and ECL technologies.
`
`Senior Associate Engineer, Memory Development, IBM Corporation
`IBM 3090 mainframe main memory subsystem development including chip design and
`verification, circuit and board-level analysis, and hardware prototype debugging and
`integration with other subsystems.
`
`Honors and Awards
`IEEE Fellow
`
`Three IEEE Micro Top Picks in Computer Architecture Awards
`
`Three IBM Faculty Awards
`
`NSF CAREER Award
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 1
`
`

`

`MICRO Hall of Fame
`
`Michael Tien ’72 Excellence in Teaching Award
`
`Ralph S. Watts ’72 Excellence in Teaching Award
`
`Ruth and Joel Spira Excellence in Teaching Award
`
`IEEE Computer Society Golden Core Award
`
`Prime Computer Patent Plateau Award
`
`Two Prime Computer Excellence Awards
`
`IBM Excellence Award
`
`Book Chapters
`“Alleviating Thermal Constraints while Maintaining Performance Via Silicon-Based On-
`Chip Optical Interconnects,” N. Nelson, G. Briggs, M. Haurylau, G. Chen, H. Chen,
`D.H. Albonesi, E.G. Friedman, and P.M. Fauchet, Unique Chips and Systems, CRC
`Press, 2007.
`
`“Power-Efficient Issue Queue Design,” A. Buyuktosunoglu, D.H. Albonesi, S. Schuster,
`D. Brooks, P. Bose, P. Cook, in Power Aware Computing, R. Graybill and R. Melhem
`(Eds), Kluwer Academic Publishers, Chapter 3, pp. 37-60, 2002.
`
`“Low-Voltage 0.25um CMOS Improved Power Adaptive Issue Queue For Embedded
`Microprocessors,” B.W. Curran, M. Gifaldi, J. Martin, A. Buyuktosunoglu, M. Margala,
`and D.H. Albonesi, in SOC Design Methodologies, M. Robert, B. Rouzeyre, C. Piguet,
`and M.-L. Flottes (Eds), Kluwer Academic Publishers, 2002.
`
`Journal Publications
`“A Phase Adaptive Cache Hierarchy for SMT Processors,” S. Lopez, O. Garnica, D.H.
`Albonesi, S. Dropsho, J. Lanchares, and J.I. Hidalgo, Microprocessors & Microsystems,
`Vol. 35, No. 8, pp. 683-694, November 2011.
`
`“A Low Latency, High Throughput On-Chip Optical Router Architecture for Future
`Chip Multiprocessors,” M.J. Cianchetti and D.H. Albonesi, ACM Journal on Emerg-
`ing Technologies in Computing Systems, Special Issue on Nanophotonic Communication
`Technology Integration, Vol. 7, No. 2, June 2011.
`
`“ReMAP: A Reconfigurable Architecture for Chip Multiprocessors,” M.A. Watkins and
`D.H. Albonesi, IEEE Micro, Special Issue on the Top Picks from the Computer Archi-
`tecture Conferences, pp. 65-77, January/February 2011 (IEEE Micro Top Picks).
`
`“Addressing Thermal Non-Uniformity in SMT Workloads,” J.A. Winter and D.H. Al-
`bonesi, ACM Transactions on Architecture and Code Optimization, Vol. 5, No. 1, May
`2008.
`
`“Predictions of CMOS Compatible On-Chip Optical Interconnect,” G. Chen, H. Chen,
`M. Haurylau, N. A. Nelson, D. H. Albonesi, P. M. Fauchet, and E. G. Friedman, Inte-
`gration, The VLSI Journal, Vol. 40, No. 4, pp. 434-446, July 2007.
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 2
`
`

`

`“On-chip Optical Technology in Future Bus-based Multicore Designs: Opportunities
`and Challenges,” N. Kırman, M. Kırman,, R.K. Dokania, J. Mart´ınez, A.B. Apsel, M.A.
`Watkins, and D.H. Albonesi, IEEE Micro, Special Issue on the Top Picks from the
`Computer Architecture Conferences, pp. 56-66, January/February 2007 (IEEE Micro
`Top Picks).
`
`“On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions,” M. Hau-
`rylau, G. Chen, H. Chen, J. Zhang, N.A. Nelson, D.H. Albonesi, E.G. Friedman, and
`P.M. Fauchet, IEEE Journal of Selected Topics in Quantum Electronics, Special Issue
`on Silicon Photonics, Vol. 12, No. 6, pp. 1699-1705, November/December 2006.
`
`“Power Efficient Error Tolerance in Chip Multi-Processors,” M.W. Rashid, E.J. Tan,
`M.C. Huang, and D.H. Albonesi, IEEE Micro, Special Issue on Reliability-Aware Mi-
`croarchitectures, Vol. 25, No. 6, pp. 60-70, November/December 2005.
`
`“An Evaluation of a Configurable VLIW Microarchitecture for Embedded DSP Applica-
`tions,” W. Liu, D.H. Albonesi, J. Gostomski, L. Palum, D. Hinterberger, R. Wanzenried,
`and M. Indovina, Journal of Circuits, Systems, and Computers, Special Issue on VLSI
`Architectures for Multimedia Applications, Vol. 13, No. 6, pp. 1321-1345, December
`2004.
`
`“Dynamically Tuning Processor Resources with Adaptive Processing,” D.H. Albonesi,
`R. Balasubramonian, S.G. Dropsho, S. Dwarkadas, E.G. Friedman, M.C. Huang, V.
`Kursun, G. Magklis, M.L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu, P.W. Cook,
`and S.E. Schuster, IEEE Computer, Special Issue on Power-Aware Computing, Vol. 36,
`No. 12, pp. 49-58, December 2003.
`
`“Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microproces-
`sor,” G. Magklis, G. Semeraro, D.H. Albonesi, S.G. Dropsho, S. Dwarkadas, and M.L.
`Scott, IEEE Micro, Special Issue on the Top Picks from the Computer Architecture
`Conferences, Vol. 23, No. 6, pp. 62-68, November/December 2003 (IEEE Micro Top
`Picks).
`
`“A Dynamically Tunable Memory Hierarchy,” R. Balasubramonian, D.H. Albonesi, A.
`Buyuktosunoglu, and S. Dwarkadas, IEEE Transactions on Computers, Vol. 52, No. 10,
`pp. 1243-1258, October 2003.
`
`“Power and Complexity Aware Design,” P. Bose, D.H. Albonesi, and D. Marculescu,
`IEEE Micro, Guest Editors’ Introduction for Special Issue on Power and Complexity
`Aware Design, Vol. 23, No. 5, pp. 8-11, September/October 2003.
`
`“Selective Cache Ways: On-Demand Cache Resource Allocation,” D.H. Albonesi, Jour-
`nal of Instruction-Level Parallelism, Special Issue on the Best Papers from the 32nd
`International Symposium on Microarchitecture, Vol. 2, 2000.
`
`“Runtime Reconfiguration Techniques for Efficient General Purpose Computation,” B.
`Xu and D.H. Albonesi, IEEE Design & Test of Computers, Special Issue on Configurable
`Computing, pp. 42-52, January-March, 2000.
`
`“STATS: A Framework for Microprocessor and System-Level Design Space Exploration,”
`D.H. Albonesi and I. Koren, Journal of Systems Architecture, Special Issue on Micro-
`processor Architecture, Vol. 45, No. 12-13, pp. 1097-1110, June 1999.
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 3
`
`

`

`“A Mean Value Analysis Multiprocessor Model Incorporating Superscalar Processors
`and Latency Tolerating Techniques,” D.H. Albonesi and I. Koren, International Jour-
`nal of Parallel Programming, Special Issue on Parallel Architectures and Compilation
`Techniques, Vol. 24, No. 3, pp. 235-263, August 1996.
`
`Refereed Conference and Workshop Publications
`“DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural
`Networks,” T. Rzayev, S. Moradi, D.H. Albonesi, and R. Manohar, International Joint
`Conference on Neural Networks, May 2017.
`
`“Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer
`Interaction,” T. Rzayev, D.H. Albonesi, R. Manohar, F. Guimbretiere, and J. Kihm,
`International Symposium on Performance Analysis of Systems and Software, April 2017.
`
`“Dynamic GPGPU Power Management using Adaptive Model Predictive Control,” A.
`Majumdar, L. Piga, I. Paul, J.L. Greathouse, W. Huang, and D.H. Albonesi, 23rd In-
`ternational Symposium on High Performance Computer Architecture, February 2017.
`
`“Fractured Arithmetic Accelerator for Training Deep Neural Networks,” T. Rzayev,
`S. Moradi, D.H. Albonesi, and R. Manohar, Workshop on Hardware and Algorithms
`for On-chip Learning, held at the International Conference on Computer-Aided Design,
`November 2016.
`
`“Characterizing the Benefits and Limitations of Smart Building Meeting Room Schedul-
`ing,” A. Majumdar, Z. Zhang, and D.H. Albonesi, 7th International Conference on
`Cyber-Physical Systems, April 2016.
`
`“Energy-Comfort Optimization using Discomfort History and Probabilistic Occupancy
`Prediction,” A. Majumdar, J.L. Setter, J.R. Dobbs, B.M. Hencey, and D.H. Albonesi,
`5th International Green Computing Conference, November 2014.
`
`“Flicker: A Dynamically Adaptive Architecture for Power Limited Multicore Systems,”
`P. Petrica, A.M. Izraelevitz, D.H. Albonesi, and C.A. Shoemaker, 40th International
`Symposium on Computer Architecture, pp. 13-23, June 2013.
`
`“Energy-Aware Meeting Scheduling Algorithms for Smart Buildings,” A. Majumdar,
`D.H. Albonesi, and P. Bose, 4th ACM Workshop On Embedded Systems For Energy-
`Efficiency In Buildings, November 2012.
`
`“ReMAP: A Reconfigurable Heterogeneous Multicore Architecture,” M.A. Watkins and
`D.H. Albonesi, 43rd International Symposium on Microarchitecture, pp. 497-508, De-
`cember 2010.
`
`“Scalable Thread Scheduling and Global Power Management for Heterogeneous Many-
`Core Architectures,” J.A. Winter, D.H. Albonesi, and C.A. Shoemaker, 19th Interna-
`tional Conference on Parallel Architectures and Compilation Techniques, pp. 29-39,
`September 2010.
`
`“Dynamically Managed Multithreaded Reconfigurable Architectures for Chip Multipro-
`cessors,” M.A. Watkins and D.H. Albonesi, 19th International Conference on Parallel
`Architectures and Compilation Techniques, pp. 41-52, September 2010.
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 4
`
`

`

`“Adaptive Cache Memories for SMT Processors,” S. Lopez, O. Garnica, D.H. Albonesi,
`S. Dropsho, J. Lanchares, and J.I. Hidalgo, 13th Euromicro Conference on Digital System
`Design, pp. 331-338, September 2010.
`“Dynamic Power Redistribution in Failure Prone CMPs,” P. Petrica, J.A. Winter, and
`D.H. Albonesi, Workshop on Energy Efficient Design, June 2010.
`“Enabling Parallelization via a Reconfigurable Chip Multiprocessor,” M.A. Watkins and
`D.H. Albonesi, Workshop on Parallel Execution of Sequential Programs on Multi-core
`Architectures, June 2010.
`“Phastlane: A Rapid Transit Optical Routing Network,” M.J. Cianchetti, J.C. Kerekes,
`and D.H. Albonesi, 36th International Symposium on Computer Architecture, pp. 441-
`450, June 2009.
`“Shared Reconfigurable Architectures for CMPs,” M.A. Watkins, M.J. Cianchetti, and
`D.H. Albonesi, 18th IEEE International Conference on Field Programmable Logic and
`Applications, September 2008 (Best Paper Award Nomination).
`“The Scalability of Scheduling Algorithms for Unpredictably Heterogeneous CMP Archi-
`tectures,” J.A. Winter and D.H. Albonesi, Workshop on Parallel Execution of Sequen-
`tial Programs on Multi-core Architectures, held at the 35th International Symposium on
`Computer Architecture, June 2008.
`“Scheduling Algorithms for Unpredictably Heterogeneous CMP Architectures,” J.A.
`Winter and D.H. Albonesi, 38th International Conference on Dependable Systems and
`Networks, pp. 42-51, June 2008.
`“On-Chip Optical Interconnects: Challenges and Critical Directions,” G. Chen, H. Chen,
`M. Haurylau, N.A. Nelson, D.H. Albonesi, P.M. Fauchet, and E.G. Friedman, Proceed-
`ings of the European Optical Society Topical Meeting on Optical Microsystems, p. 97,
`October 2007.
`“On-Chip Optical Interconnect for Reduced Delay Uncertainty,” G. Chen, H. Chen, M.
`Haurylau, N.A. Nelson, D.H. Albonesi, P.M. Fauchet, and E.G. Friedman, Proceedings
`of Nano-Net, September 2007.
`“Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches,” S. Lopez, S. Dropsho,
`D.H. Albonesi, O. Garnica, and J. Lanchares, International Conference on High Perfor-
`mance Embedded Architectures and Compilers, pp. 136-150, January 2007.
`“Leveraging Optical Technology in Future Bus-based Chip Multiprocessors,” N. Kırman,
`M. Kırman,, R.K. Dokania, J. Mart´ınez, A.B. Apsel, M.A. Watkins, and D.H. Albonesi,
`39th International Symposium on Microarchitecture, December 2006 (Best Paper Award
`Nomination).
`“Synergistic Temperature and Energy Management in GALS Processor Architectures,”
`Y. Zhu and D.H. Albonesi, International Symposium on Low Power Electronics and
`Design, pp. 55-60, October 2006.
`“On-Chip Copper-Based vs. Optical Interconnects: Delay Uncertainty, Latency, Power,
`and Bandwidth Density Comparative Predictions,” G. Chen, H. Chen, M. Haurylau,
`N.A. Nelson, D.H. Albonesi, P.M. Fauchet, and E.G. Friedman, IEEE International
`Interconnect Technology Conference, pp. 39-41, June 2006.
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 5
`
`

`

`“Localized Microarchitecture-Level Voltage Management,” Y. Zhu and D.H. Albonesi,
`International Symposium on Circuits and Systems, pp. 37-40, May 2006.
`“Compatible Phase Co-Scheduling on a CMP of Multi-Threaded Processors,” A. El-
`Moursy, R. Garg, D.H. Albonesi, and S. Dwarkadas, 20th International Parallel and
`Distributed Processing Symposium, April 2006.
`“Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance,”
`M.W. Rashid, E.J. Tan, M.C. Huang, and D.H. Albonesi, 14th International Conference
`on Parallel Architectures and Compilation Techniques, pp. 315-325, September 2005.
`“On-chip Optical Interconnect Roadmap: Challenges and Critical Directions,” M. Hau-
`rylau, H. Chen, J. Zhang, G. Chen, N.A. Nelson, D.H. Albonesi, E.G. Friedman, and
`P.M. Fauchet, 2nd International Group IV Photonics Conference, pp. 17-19, September
`2005.
`“QUILT: A GUI-based Integrated Circuit Floorplanning Environment for Computer
`Architecture Research and Education,” G.J. Briggs, E.J. Tan, N.A. Nelson, and D.H.
`Albonesi, Workshop on Computer Architecture Education, June 2005.
`“Electrical and Optical On-Chip Interconnects in Scaled Microprocessors,” G. Chen,
`H. Chen, M. Haurylau, N. Nelson, D.H. Albonesi, P.M. Fauchet, and E.G. Friedman,
`International Symposium on Circuits and Systems, pp. 2514-2517, May 2005.
`“Predictions of CMOS Compatible On-Chip Optical Interconnect,” G. Chen, H. Chen,
`M. Haurylau, N. Nelson, P.M. Fauchet, E.G. Friedman, and D.H. Albonesi, 7th Inter-
`national Workshop on System Level Interconnect Prediction, pp. 13-20, April 2005.
`“A High Performance, Energy Efficient, GALS Processor Microarchitecture with Re-
`duced Implementation Complexity,” Y. Zhu, D.H. Albonesi, and A. Buyuktosunoglu,
`International Symposium on Performance Analysis of Systems and Software, pp. 42-53,
`March 2005.
`“Partitioning Multi-Threaded Processors with a Large Number of Threads,” A. El-
`Moursy, R. Garg, D.H. Albonesi, and S. Dwarkadas, International Symposium on Per-
`formance Analysis of Systems and Software, pp. 112-123, March 2005.
`“Alleviating Thermal Constraints while Maintaining Performance Via Silicon-Based On-
`Chip Optical Interconnects,” N. Nelson, G. Briggs, M. Haurylau, G. Chen, H. Chen, D.H.
`Albonesi, E.G. Friedman, and P.M. Fauchet, Workshop on Unique Chips and Systems,
`March 2005.
`“Dynamically Trading Frequency for Complexity in a GALS Microprocessor,” S. Drop-
`sho, G. Semeraro, D.H. Albonesi, G. Magklis, and M.L. Scott, 37th International Sym-
`posium on Microarchitecture, pp. 157-168, December 2004 (Best Paper Award Nomina-
`tion).
`“Dynamically Matching ILP Characteristics Via a Heterogeneous Clustered Microar-
`chitecture,” L. Chen, D.H. Albonesi, and S. Dropsho, IBM Watson Conference on the
`Interaction Between Architecture, Circuits, and Compilers, pp. 136-143, October 2004.
`“The Energy Impact of Aggressive Loop Fusion,” Y. Zhu, G. Magklis, M.L. Scott, C.
`Ding, and D.H. Albonesi, 13th International Conference on Parallel Architectures and
`Compilation Techniques, pp. 153-164, September 2004.
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 6
`
`

`

`“Mitigating Inductive Noise in SMT Processors,” W. El-Essawy and D.H. Albonesi,
`International Symposium on Low Power Electronics and Design, pp. 332-337, August
`2004.
`
`“Hiding Synchronization Delays in a GALS Processor Microarchitecture,” G. Semeraro,
`D.H. Albonesi, G. Magklis, M.L. Scott, S.G. Dropsho, and S. Dwarkadas, 10th Interna-
`tional Symposium on Asynchronous Circuits and Systems, pp. 159-169, April 2004.
`
`“Improving Application Performance by Dynamically Balancing Speed and Complexity
`in a GALS Microprocessor,” G. Semeraro, D.H. Albonesi, S. Dropsho, G. Magklis, S.
`Dwarkadas, and M.L. Scott, Workshop on Application Specific Processors, December
`2003.
`
`“Energy Efficient Co-Adaptive Instruction Fetch and Issue,” A. Buyuktosunoglu, T.
`Karkhanis, D.H. Albonesi, and P. Bose, 30th International Symposium on Computer
`Architecture, pp. 147-156, June 2003.
`
`“Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered
`Processors,” R. Balasubramonian, S. Dwarkadas, and D.H. Albonesi, 30th International
`Symposium on Computer Architecture, pp. 275-286, June 2003.
`
`“Profile-based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain
`Microprocessor,” G. Magklis, M.L. Scott, G. Semeraro, D.H. Albonesi, and S. Dropsho,
`30th International Symposium on Computer Architecture, pp. 14-25, June 2003.
`
`“Front-End Policies for Improved Issue Efficiency in SMT Processors,” A. El-Moursy
`and D.H. Albonesi, 9th International Symposium on High-Performance Computer Ar-
`chitecture, pp. 31-40, February 2003.
`
`“Dynamic Data Dependence Tracking and its Application to Branch Prediction,” L.
`Chen, S. Dropsho, and D.H. Albonesi, 9th International Symposium on High-Performance
`Computer Architecture, pp. 65-76, February 2003.
`
`“Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitec-
`ture,” G. Semeraro, D.H. Albonesi, S.G. Dropsho, G. Magklis, S. Dwarkadas, and M.L.
`Scott, 35th International Symposium on Microarchitecture, pp. 356-367, November 2002.
`
`“Managing Static Leakage Energy in Microprocessor Functional Units,” S. Dropsho, V.
`Kursun, D.H. Albonesi, S. Dwarkadas, and E.G. Friedman, 35th International Sympo-
`sium on Microarchitecture, pp. 321-332, November 2002.
`
`“Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power,” S.
`Dropsho, A. Buyuktosunoglu, R. Balasubramonian, D.H. Albonesi, S. Dwarkadas, G.
`Semeraro, G. Magklis, and M.L. Scott, 11th International Conference on Parallel Archi-
`tectures and Compilation Techniques, pp. 141-152, September 2002.
`
`“An Oldest-First Selection Logic Implementation for Non-Compacting Issue Queues,”
`A. Buyuktosunoglu, A. El-Moursy, and D.H. Albonesi, 15th International ASIC/SOC
`Conference, pp. 31-35, September 2002.
`
`“Tradeoffs in Power-Efficient Issue Queue Design,” A. Buyuktosunoglu, D.H. Albonesi,
`P. Bose, P. Cook, S. Schuster, International Symposium on Low Power Electronics and
`Design, pp. 184-189, August 2002.
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 7
`
`

`

`“A Microarchitectural-Level Step-Power Analysis Tool,” W. El-Essawy, D.H. Albonesi,
`and B. Sinharoy, International Symposium on Low Power Electronics and Design, pp.
`263-266, August 2002.
`
`“Energy Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage
`and Frequency Scaling,” G. Semeraro, G. Magklis, R. Balasubramonian, D.H. Albonesi,
`S. Dwarkadas, and M.L. Scott, 8th International Symposium on High-Performance Com-
`puter Architecture, pp. 29-40, February 2002.
`
`“Early Stage Definition of LPX: A Low Power Issue-Execute Processor,” P. Bose, D.
`Brooks, A. Buyuktosunoglu, P. Cook, K. Das, P. Emma, M. Gschwind, H. Jacobson, T.
`Karkhanis, P. Kudva, S. Schuster, J. Smith, V. Srinivasan, V. Zyuban, D. Albonesi, S.
`Dwarkadas, Workshop on Power-Aware Computer Systems, February 2002.
`
`“Low-Voltage 0.25um CMOS Improved Power Adaptive Issue Queue For Embedded
`Microprocessors,” B.W. Curran, M. Gifaldi, J. Martin, A. Buyuktosunoglu, M. Margala,
`and D.H. Albonesi, in 11th International Conference on Very Large Scale Integration of
`Systems-on/Chip: SOC Design Methodologies, pp. 289-300, December 2001.
`
`“Reducing the Complexity of the Register File in Dynamic Superscalar Processors,” R.
`Balasubramonian, S. Dwarkadas, and D.H. Albonesi, 34th International Symposium on
`Microarchitecture, pp. 237-248, December 2001.
`
`“A Dynamic Reconfigurable Clock Generator,” R.M. Secareanu, D. Albonesi, and E.G.
`Friedman, 14th International ASIC/SOC Conference, pp. 330-333, September 2001.
`
`“Dynamically Allocating Processor Resources Between Nearby and Distant ILP,” R.
`Balasubramonian, S. Dwarkadas, and D.H. Albonesi, 28th International Symposium on
`Computer Architecture, pp. 26-37, June 2001.
`
`“A Circuit Level Implementation of an Adaptive Issue Queue for Power-Aware Micro-
`processors,” A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and D.H.
`Albonesi, 11th Great Lakes Symposium on VLSI, pp. 73-78, March 2001.
`
`“Memory Hierarchy Reconfiguration for Energy and Performance in General Purpose
`Processor Architectures,” R. Balasubramonian, D.H. Albonesi, A. Buyuktosunoglu, and
`S. Dwarkadas, 33rd International Symposium on Microarchitecture, pp. 245-257, De-
`cember 2000.
`
`“An Adaptive Issue Queue for Reduced Power at High Performance,” A. Buyukto-
`sunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and D.H. Albonesi, Workshop on
`Power-Aware Computer Systems, November 2000.
`
`“Dynamic Memory Hierarchy Performance Optimization,” R. Balasubramonian, D.H.
`Albonesi, A. Buyuktosunoglu, and S. Dwarkadas, Workshop on Solving the Memory
`Wall Problem, June 2000.
`
`“An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of
`Microprocessor Memory Structures,” D.H. Albonesi, 10th International Conference on
`VLSI, pp. 192-203, December 1999.
`
`“Selective Cache Ways: On-Demand Cache Resource Allocation,” D.H. Albonesi, 32nd
`International Symposium on Microarchitecture, pp. 248-259, November 1999.
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 8
`
`

`

`“A Methodology for the Analysis of Dynamic Application Parallelism and Its Appli-
`cation to Reconfigurable Computing,” B. Xu and D.H. Albonesi, SPIE International
`Conference on Reconfigurable Technology: FPGAs for Computing and Applications, pp.
`78-86, September 1999.
`
`“Dynamic IPC/Clock Rate Optimization,” D.H. Albonesi, 25th International Sympo-
`sium on Computer Architecture, pp. 282-292, June 1998.
`
`“The Inherent Energy Efficiency of Complexity-Adaptive Processors,” D.H. Albonesi,
`Power-Driven Microarchitecture Workshop, pp. 107-112, June 1998.
`
`“Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-
`Based Systems,” D.H. Albonesi and I. Koren, 5th International Conference on Parallel
`Architectures and Compilation Techniques, pp. 126-135, November 1997.
`
`“An Automated and Flexible Framework for Integrated Microprocessor and System-
`Level Design Space Exploration,” D.H. Albonesi and I. Koren, Workshop on Perfor-
`mance Analysis and its Impact on Design, pp. 25-34, June 1997.
`
`“Architecture and Technology Tradeoffs in the Design of Next-Generation Multiprocessor
`Servers,” D.H. Albonesi and I. Koren, 7th IEEE Symposium on Parallel and Distributed
`Processing, pp. 174-181, October 1995.
`
`“An Analytical Model Of High Performance Superscalar-Based Multiprocessors,” D.H.
`Albonesi and I. Koren, 3rd International Conference on Parallel Architectures and Com-
`pilation Techniques, pp. 194-203, June 1995.
`
`“Tradeoffs in the Design of Single Chip Multiprocessors,” D.H. Albonesi and I. Koren,
`2nd International Conference on Parallel Architectures and Compilation Techniques, pp.
`25-34, August 1994.
`
`Poster Presentations
`“Fractured Arithmetic Accelerator for Training Deep Neural Networks,” T. Rzayev, S.
`Moradi, D.H. Albonesi, and R. Manohar, Workshop on Hardware and Algorithms for
`Learning On-a-chip, November 2016.
`
`“PowerPlay: Coordinated Power Management and Scheduling for Unpredictably Het-
`erogeneous CMPs,” J.A. Winter, D.H. Albonesi, and C.A. Shoemaker, International
`Conference on Architectural Support for Programming Languages and Operating Sys-
`tems, March 2009.
`
`“Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors,” S.
`Lopez, S. Dropsho, D.H. Albonesi, O. Garnica, and J. Lanchares, International Confer-
`ence on Parallel Architectures and Compilation Techniques, September 2007.
`
`“Optical On-Chip Networks for High-Performance, Energy-Efficient Multi-Core Archi-
`tectures,” D.H. Albonesi, J.F. Martinez, M.A. Watkins, N. Kirman, M. Kirman, K.
`Bergman, L. Carloni, and A. Shacham, Workshop on On- and Off-Chip Interconnection
`Networks for Multicore Systems, December 2006.
`
`“Leveraging Optical Technology in Future Bus-based Chip Multiprocessors,” N. Kir-
`man, M. Kirman, R.K. Dokania, J.F. Martinez, A.B. Apsel, M.A. Watkins, and D.H.
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 9
`
`

`

`Patents
`
`Albonesi, Workshop on On- and Off-Chip Interconnection Networks for Multicore Sys-
`tems, December 2006.
`
`“Performance Monitoring for New Phase Dynamic Optimization of Instruction Dispatch
`Cluster Configuration,” R. Balasubramonian, S. Dwarkadas, and D.H. Albonesi, U.S.
`Patent 8,103,856, issued 1/24/12.
`
`“Adaptive Issue Queue for Reduced Power at High Performance,” A. Buyuktosunoglu,
`S. Schuster, D. Brooks, P. Bose, P. Cook, and D.H. Albonesi, U.S. Patent 7,865,747,
`issued 1/4/11.
`
`“Dynamic Data Dependence Tracking and its Application to Branch Prediction,” L.
`Chen, D. Albonesi, and S. Dropsho, U.S. Patent 7,571,302, issued 8/4/09.
`
`“Multi-cluster Processor Operating Only Select Number of Clusters During Each Phase
`Based on Program Statistic Monitored at Predetermined Intervals,” R. Balasubramo-
`nian, S. Dwarkadas, and D.H. Albonesi, U.S. Patent 7,490,220, issued 2/10/09.
`
`“Multiple Clock Domain Microprocessor,” D.H. Albonesi, G. Semeraro, G. Magklis, M.L.
`Scott, R. Balasubramonian, and S. Dwarkadas, U.S. Patent 7,089,443, issued 8/4/06.
`
`“Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose
`Processor Architectures,” R. Balasubramonian, D.H. Albonesi, A. Buyuktosunoglu, and
`S. Dwarkadas, U.S. Patent 6,834,328, issued 12/21/04.
`
`“Dynamically Reconfigurable Memory Hierarchy,”R. Balasubramonian, D.H. Albonesi,
`A. Buyuktosunoglu, and S. Dwarkadas, U.S. Patent 6,684,298, issued 1/27/04.
`
`“Mechanism for Dynamically Altering the Complexity of a Microprocessor,” D.H. Al-
`bonesi, U.S. Patent 6,205,537, issued 3/20/01.
`
`“Electric Cable Connection Error-Detect Method and Apparatus,” D.H. Albonesi, U.S.
`Patent 5,170,113, issued 12/8/92.
`
`“Memory Board Selection Method and Apparatus,” D.H. Albonesi, U.S. Patent 5,119,486,
`issued 6/2/92.
`
`“System Bus for Multiprocessor Computer System,” D.H. Albonesi, B.K. Langendorf,
`J. Chang, J.G. Faase, and M.J. Homberg, U.S. Patent 5,113,514, issued 5/12/92.
`
`“Memory Error Correction System,” D.H. Albonesi, U.S. Patent 4,920,539, issued 4/24/90.
`
`Graduated PhD Students
`Paula Petrica, “Modular Architectures and Optimization Techniques for Power and Re-
`liability in Future Many Core Microprocessors,” School of Electrical and Computer En-
`gineering, Cornell University, January 2012. First employment: Intel Corporation.
`
`Mark Cianchetti, “Nanophotonic Interconnect Architectures for Many-core Micropro-
`cessors,” School of Electrical and Computer Engineering, Cornell University, January
`2012. First employment: Intel Corporation.
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 10
`
`

`

`Matt Watkins, “Reconfigurable Architectures for Chip Multiprocessors,” School of Elec-
`trical and Computer Engineering, Cornell University, August 2010. First employment:
`Harvey Mudd College.
`
`Jonathan Winter, “Adaptive Thread Management for Power, Performance, and Relia-
`bility in Future Microprocessors,” Department of Computer Science, Cornell University,
`February 2010. First employment: Google.
`
`Sonia Lopez Alarcon, “Adaptive Cache Memories for SMT Processors,” Department of
`Computer Architecture, Universidad Complutense de Madrid, March 2009 (co-advisor
`with Oscar Garnica and Juan Lanchares). First employment: Rochester Institute of
`Technology.
`
`Yongkang Zhu, “Hardware and Software Optimizations for Multiple Clock Domain
`Microprocessors,” Department of Electrical and Computer Engineering, University of
`Rochester, September 2005. First employment: Microsoft Corporation.
`
`Ali El-Moursy, “Highly Efficient Multithreaded Architecture,” Department of Electrical
`and Computer Engineering, University of Rochester, August 2005 (unofficial co-advisor:
`Sandhya Dwarkadas). First employment: Intel Corporation.
`
`Wael El-Essawy, “Architectural Level Analysis and Mitigation of Inductive Noise in
`Simultaneous Multi-Threaded Processors,” Department of Electrical and Computer En-
`gineering, University of Rochester, October 2004. First employment: IBM Austin Re-
`search Laboratory.
`
`Lei Chen, “Dynamic Data Dependence Tracking and its Applications,” Department of
`Electrical and Computer Engineering, University of Rochester, October 2004. First
`employment: IBM Austin Research Laboratory.
`
`Greg Semeraro, “Multiple Clock Domain Microarchitecture Design and Analysis,” De-
`partment of Electrical and Computer Engineering, University of Rochester, October
`2003. First employment: Rochester Institute of Technology.
`
`Rajeev Balasubramonian, “Dynamic Management of Microprocessor Resources in Future
`Microprocessors,” Department of Computer Science, University of Rochester, August
`2003 (unofficial co-advisor; advisor: Sandhya Dwarkadas). First employment: University
`of Utah.
`
`Alper Buyuktosunoglu, “Power-Efficient Issue Queue Design,” Department of Electrical
`and Computer Engineering, University of Rochester, June 2003. First employment: IBM
`T.J. Watson Research Center.
`
`Current PhD Students
`Neeraj Kulkarni, School of Electrical and Computer Engineering, Cornell University.
`
`Abhinandan Majumdar, School of Electrical and Computer Engineering, Cornell Uni-
`versity.
`
`Tayyar Rzayev (co-advised with Rajit Manohar), School of Electrical and Computer
`Engineering, Cornell University.
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 11
`
`

`

`Nitish Srivastava (co-advised with Rajit Manohar), School of Electrical and Computer
`Engineering, Cornell University.
`
`Postdoctoral Researchers
`Dr. Steven Dropsho, Department of Computer Science, University of Rochester, 9/2001-
`10/2003. First employment: EPFL.
`
`Graduated MS Students
`Haotian Pan, “HVAC Energy and Occupant Comfort Optimization Using Neural Network-
`Based Temperature Prediction,” School of Electrical and Computer Engineering, Cornell
`University, August 2015.
`
`Keith Kraft, “Trace Cache Hierarchies,” Department of Electrical and Computer En-
`gineering, University of Rochester, May 2003. First employment: Intel Corporation.
`
`Undergraduate Research Students
`Jason Setter (2013-2015), Vasu Mannar (2014), Wei Geng (2014), Scott McKenzie (2014),
`Adam Izraelevitz (2011-2013), Alvin Wijaya (2012), Ari Karo (2012), Jee Ho Ryoo (2010-
`11), Joseph Kerekes (2009-10), Greg Briggs (2005), Alvin Law (2002), Jethro Law (2000),
`John Strasser (1999).
`
`PhD Dissertation Committees
`Filipp Akopyan, Major Bhadauria, David Biermann, Tao Chen, Justin Dobbs, David
`Fang, Bye-sah Gantsog, Saugata Ghose, Benjamin Hill, Raymond Huang, Engin Ipek,
`Sandra Jackson, Meyrem Kirman, Chris LaFrieda, Jian Li, Derek Lockhart, Janani
`Mukundan, Paruj Ratanaworabhan, Basit Shiekh, Karan Singh, Peter Szwed, Jonathan
`Tse, Xiaodong Wang, Vince Weaver (Cornell); Victor Adler, Magdy El-Moursy, Galen
`Hunt, Ivan Kourtev, Volkan Kursun, Grigoris Magklis, Andrey Meshiba, Umit Ren-
`cuzogullari, Tolga Soyata, Robert Stets, Kevin Tang, Dimitrios Velenis, Yutao Zhong
`(University of Rochester); Anne Bracy (University of Pennsylvania); Jaume Abella (Uni-
`versitat Politecnica de Catalunya [UPC]).
`
`MS Thesis Committees
`Major Bhadauria, Ramazan Bitirgen, Julia Karl, Nevin Kirman, Catherine Trammell
`(Cornell); Michael Wieckowski (University of Rochester).
`
`Teaching and Curriculum Development
`The Computing Technology Inside Your Smartphone
`Online edX course. Developed and taught Spring’15. Taught Summer’16.
`
`The Computing Technology Inside Your Smartphone
`Freshman course in computer systems. Developed and taught Fall’10. Taught Fall’11,
`Fall’12, and Spring’17.
`
`Digital Logic and Computer Organization
`
`Petitioner STMicroelectronics, Inc.
`Ex. 1004, p. 12
`
`

`

`Undergraduate course in digital logic design and computer architecture. Taught Spring’06,
`Sprin