1
`
`PETITIONER’S ORAL ARGUMENT
`
`Inter Partes Review No. 2017‐01430
`Unified Patents Inc. v. Plectrum LLC
`
`U.S. Patent No. 5,978,951
`
`‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNIFIED 1023
`UNIFIED PATENTS INC. v. PLECTRUM LLC
`IPR2017-01430
`
`
`
`PETITIONER’S ORAL ARGUMENT
`
`Inter Partes Review No. 2017‐01430
`Unified Patents Inc. v. Plectrum LLC
`
`U.S. Patent No. 5,978,951
`
`‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNIFIED 1023
`UNIFIED PATENTS INC. v. PLECTRUM LLC
`IPR2017-01430
`
`
`
`2
`
`Obviousness of claims
`–Claims 1‐6, 12‐14, and 21‐24: row‐related limitations
`
`–Claims 8 and 11: substitution of Jain’s CRC hash function in
`Issues raised by the Board and/or Patent Owner
`Overview of the prior art
`Overview of the ʼ951 patent
`
`place of Cheriton’s XOR‐based hash function
`
`Proposed Agenda
`
`
`
`3
`
`Overview of the ’951 Patent2
`
`33$99:B2,2296
`
`
`
`4
`
`‘951 patent at 1:31‐38
`
`address search results, including the destination port(s) for received frames”
`Processing (RHP) element which parses frame headers for address information; and returning
`the hardware address table for layer 2 and layer 3 addresses received from a Received Header
`“The ACA [Address Cache ASIC] is responsible for: maintaining a hardware address table … searching
`
`Seshan Decl. (EX1007) at ¶¶ 26‐29; Petition (Paper 3) at 4‐8
`
`Addr. 10.4
`
`Addr. 10.8
`
`Addr. 10.4
`
`Addr. 10.22
`
`Port 3
`
`Port 2
`
`Port 1
`
`Port 0
`
`The ʼ951 Patent –“Bridge/Router”
`
`
`
`5
`
`E.g., ‘951 patent at 5:25‐57;Petition (Paper 3) at 11‐17
`
`Use port number to forward data unit
`
`port number) from the same row/entry
`DA, retrieve second address info (e.g., a
`If the found cached address equals the
`
`row/entry and compare to DA info
`Retrieve cached address info from
`[that may have routing info for the DA]
`use that hash to identify a row in cache
`Generate a hash address from DA and
`
`destination address (DA)) from data unit
`Parse received address information (e.g.,
`
`each row with multiple entries
`A method using a row‐based cache,
`
`forwarding said data unit.
`using said retrieved second address information for
`
`address information yields a first result; and
`retrieved first address information and said received
`entry of said identified row if said comparison of said
`retrieving second address information from said first
`
`said received address information;
`comparing said retrieved first address information with
`
`said identified row;
`retrieving first address information from a first entry of
`
`identify one of said cache rows;
`using said received, encoded address information to
`encoding said received address information;
`
`parsing said data unit for address information;
`
`receiving said data unit at said network element;
`
`comprising the steps of:
`rows, each having plural respective entries, the method
`network element having a cache comprised of plural
`2. A method of forwarding a data unit through a
`
`ʼ951 Patent –Independent Claim 2
`
`
`
`6
`
`E.g., ‘951 patent at 5:25‐57;Petition (Paper 3) at 11‐17; Seshan Decl. (EX1007) at ¶¶ 191‐213
`
`data unit
`cache for use in outputting the
`the output SA and DA found in
`Output packetizer to ‘packetize’
`search the cache
`Lookup unit that uses hash to
`and send to cache lookup unit
`input SA, DA, and hash address
`Input packetizer to ‘packetize’
`address from data unit header
`CRC generator to form a hash
`
`address information.
`for receiving said formatted retrieved source and destination
`an output register in communication with said output packetizer
`
`destination address information from said cache; and
`unit for receiving and formatting retrieved source and
`an output packetizer in communication with said cache lookup
`
`formatted CRC encoded addresses;
`with said input packetizer for searching said cache with said
`a cache lookup unit and an associated cache in communication
`
`addresses from said input register;
`addresses and for receiving said received source and destination
`and said input register for formatting said CRC encoded
`an input packetizer in communication with said CRC generator
`
`register to form respective CRC encoded addresses;
`said received source and destination addresses from said input
`with said input register for executing a CRC algorithm on each of
`a cyclic redundancy code (CRC) generatorin communication
`
`including received source and destination address;
`an input register for receiving data unit header information
`
`device, comprising:
`8. A cache management unit of a data unit forwarding network
`
`ʼ951 Patent –Independent Claim 8
`
`
`
`7
`
`¶¶ 26‐28, 40‐44
`‘951 patent at Figs. 7A‐7C, 4A‐4B, 5:45‐57;Petition (Paper 3) at 13‐15; Seshan Decl. (EX1007) at
`
`Addr. 10.8
`
`Addr. 10.4
`
`Addr. 10.22
`
`Port 3
`
`Port 2
`
`Port 1
`
`Port 0
`
`2
`
`10.8
`
`Data: 0101011…
`Header: DA: 10.8
`Data unit:
`
`encoding said received address information;…
`
`parsing said data unit for address information;
`
`receiving said data unit at said network element;
`Claim 2:…
`
`The ʼ951 Patent –High‐Level Operation
`
`
`
`8
`
`¶¶ 26‐28, 40‐44
`‘951 patent at Figs. 7A‐7C, 4A‐4B, 5:45‐57;Petition (Paper 3) at 13‐15; Seshan Decl. (EX1007) at
`
`Addr. 10.8
`
`Addr. 10.4
`
`Addr. 10.22
`
`…
`
`…
`
`…
`
`…
`…
`
`0
`
`2
`
`…
`3
`
`DA(S2)
`
`Port (S1)
`
`10.77
`10.55
`10.33
`Port (S0)
`DA (S1)
`Address Cache
`
`3
`
`2
`
`…
`0
`
`Port 3
`
`Port 2
`
`Port 1
`
`Port 0
`
`2.
`1.Hash/row index (2)
`Parsed “cache address”:
`
`Set index (S0)
`
`…
`
`10.22
`10.8
`10.4
`DA (S0)
`
`…
`
`2
`
`10.8
`
`Data: 0101011…
`Header: DA: 10.8
`Data unit:
`
`1
`
`2
`
`…
`3
`
`Row
`
`with said received address information;…
`comparing said retrieved first address information
`
`entry of said identified row;
`retrieving first address information from a first
`
`information to identify one of said cache rows;
`… using said received, encoded address
`Claim 2:…
`
`The ʼ951 Patent –High‐Level Operation
`
`
`
`9
`
`¶¶ 26‐28, 40‐44
`‘951 patent at Figs. 7A‐7C, 4A‐4B, 5:45‐57;Petition (Paper 3) at 13‐15; Seshan Decl. (EX1007) at
`
`Addr. 10.8
`
`Addr. 10.4
`
`Addr. 10.22
`
`…
`
`…
`
`…
`
`…
`…
`
`0
`
`2
`
`…
`3
`
`DA(S2)
`
`Port (S1)
`
`Port 3
`
`Port 2
`
`Port 1
`
`Port 0
`
`Port 2
`
`10.77
`10.55
`10.33
`Port (S0)
`DA (S1)
`Address Cache
`
`3
`
`2
`
`…
`
`…
`0
`
`2
`
`10.8
`
`Data: 0101011…
`Header: DA: 10.8
`Data unit:
`
`10.22
`10.8
`10.4
`DA (S0)
`
`…
`
`1
`
`2
`
`…
`3
`
`Row
`
`for forwarding said data unit.
`using said retrieved second address information
`
`and
`received address information yields a first result;
`of said retrieved first address information and said
`first entry of said identified row if said comparison
`retrieving second address information from said
`Claim 2:…
`
`The ʼ951 Patent –High‐Level Operation
`
`
`
`10
`
`‘951 patent at Figs. 3, 4A‐4B, 5:25‐57.Petition (Paper 3) at 13‐15; Seshan Decl. (EX1007) at ¶¶ 40‐44
`
`identifies a row of four sets, i.e. Sets 0‐3“
`serves as a row index into the cache, and
`interest is known as a “hash.” The hash
`“A CRC generated from the address of
`
`DA = 10.8
`
`Header: DA: 10.8; SA 19.6
`Data Frame:
`
`Data: 0101011…
`
`then used to identify a cache row.
`then used to identify a cache row.
`process is performed by a CRC engine 104 on the address to generate a CRC. This code is
`process is performed by a CRC engine 104 on the address to generate a CRC. This code is
`MAC DA, or network DA) is received by the ACA 26. A Cyclic Redundancy Code (CRC)
`MAC DA, or network DA) is received by the ACA 26. A Cyclic Redundancy Code (CRC)
`At a high level, a cache lookup occurs as follows. An address to be searched (MAC SA,
`At a high level, a cache lookup occurs as follows. An address to be searched (MAC SA,
`
`This code is then used to identify a cache row.”
`CRC engine 104 on the address to generate a CRC.
`Redundancy Code (CRC) process is performed by a
`network DA) is received by the ACA 26. A Cyclic
`address to be searched (MAC SA, MAC DA, or
`“At a high level, a cache lookup occurs as follows. An
`
`Hashed row address = <n‐1>
`
`cache rows; …
`information to identify one of said
`using said received, encoded address
`Claim 2:…
`
`The ʼ951 Patent –“Cache lookup”
`
`
`
`11
`
`‘951 patent at Figs. 3, 4A‐4B, 10‐14; Petition (Paper 3) at 13‐15; Seshan Decl. (EX1007) at ¶¶ 40‐44
`
`. . .
`. . .
`
`then used to identify a cache row.
`then used to identify a cache row.
`process is performed by a CRC engine 104 on the address to generate a CRC. This code is
`process is performed by a CRC engine 104 on the address to generate a CRC. This code is
`MAC DA, or network DA) is received by the ACA 26. A Cyclic Redundancy Code (CRC)
`MAC DA, or network DA) is received by the ACA 26. A Cyclic Redundancy Code (CRC)
`At a high level, a cache lookup occurs as follows. An address to be searched (MAC SA,
`At a high level, a cache lookup occurs as follows. An address to be searched (MAC SA,
`with said received address information…
`comparing said retrieved first address information
`
`Compare:
`
`Address = 10.8 ?
`
`of said identified row;
`retrieving first address information from a first entry
`Claim 2:…
`
`The ʼ951 Patent –“Cache lookup”
`
`
`
`12
`
`‘951 patent at Figs. 3, 4A‐4B, 10‐14; Petition (Paper 3) at 13‐15; Seshan Decl. (EX1007) at ¶¶ 40‐44
`
`. . .
`
`then used to identify a cache row.
`then used to identify a cache row.
`sends them to the appropriate NIC 100. “
`DA lookups, packages them in an output packet, and
`process is performed by a CRC engine 104 on the address to generate a CRC. This code is
`process is performed by a CRC engine 104 on the address to generate a CRC. This code is
`“The ACA collects the results from each of the SA and
`MAC DA, or network DA) is received by the ACA 26. A Cyclic Redundancy Code (CRC)
`MAC DA, or network DA) is received by the ACA 26. A Cyclic Redundancy Code (CRC)
`At a high level, a cache lookup occurs as follows. An address to be searched (MAC SA,
`At a high level, a cache lookup occurs as follows. An address to be searched (MAC SA,
`
`using said retrieved second address information for forwarding said data unit.
`
`received address information yields a first result; and
`row if said comparison of said retrieved first address information and said
`… retrieving second address information from said first entry of said identified
`Claim 2:
`
`The ʼ951 Patent –“Cache lookup”
`
`
`
`13
`
`‘951 patent at 5:14‐24, 7:7‐15, Figs. 4B, 6C, 10‐14; Seshan Decl. (EX1007) at ¶¶ 40‐44
`
`88 bits wide
`
`. . .
`
`1 row
`
`various fields in FIGS. 10, 11 and 110.”
`13 provides details of what is stored in
`then used to identify a cache row.
`then used to identify a cache row.
`beats are found in FIGS. 10, 11 and 110. FIG.
`process is performed by a CRC engine 104 on the address to generate a CRC. This code is
`process is performed by a CRC engine 104 on the address to generate a CRC. This code is
`set (FIG. 4B). The specific format of these
`MAC DA, or network DA) is received by the ACA 26. A Cyclic Redundancy Code (CRC)
`MAC DA, or network DA) is received by the ACA 26. A Cyclic Redundancy Code (CRC)
`cache, there are four beats per route cache
`At a high level, a cache lookup occurs as follows. An address to be searched (MAC SA,
`At a high level, a cache lookup occurs as follows. An address to be searched (MAC SA,
`bridge cache set (FIG. 4A). For a bridge‐route
`are two storage elements or "beats" per
`cache organized as bridge‐only cache, there
`26 supports both X8 and X16 devices. For a
`itself is implemented in SRAMS and the ACA
`cache entries, one per set. The cache 28
`88 bits wide. Each cache row contains four
`depth up to a maximum of 16K rows, and is
`cache 28 is 4‐way set associative, can vary in
`“In a preferred embodiment, the address
`
`~88 bits wide
`
`. . .
`
`One 64k‐row (216bits) by 16 bit wide SRAM
`
`1 row
`
`The ʼ951 Patent –Row‐based SRAMs
`
`
`
`14
`
`Overview of the Prior Art
`
`
`
`15
`
`Cheriton(EX1002) (annotated); Petition (Paper 3) at 21‐24
`
`–Output switch hardware (409)
`
`•Addressed via hash of addresses
`
`•Stores learned address/port
`
`information in SRAMs
`
`•Includes SA and DA of incoming
`
`–Cache (415)
`data unit
`
`–Virtual path index (630)
`–Input switch hardware (409)
`
`–Input ports (401‐404) and output
`Cheriton
`
`ports (405‐408)
`
`row.
`row.
`code is then used to identify a cache
`code is then used to identify a cache
`the address to generate a CRC. This
`the address to generate a CRC. This
`performed by a CRC engine 104 on
`performed by a CRC engine 104 on
`Redundancy Code (CRC) process is
`Redundancy Code (CRC) process is
`received by the ACA 26. A Cyclic
`received by the ACA 26. A Cyclic
`(MAC SA, MAC DA, or network DA) is
`(MAC SA, MAC DA, or network DA) is
`as follows. An address to be searched
`as follows. An address to be searched
`At a high level, a cache lookup occurs
`At a high level, a cache lookup occurs
`
`Applied Prior Art: Cheriton
`
`
`
`16
`
`Seshan Decl. (EX1007) at ¶¶ 86‐94, 117‐120
`Compare’951 patent at Fig. 6c to Cheriton(EX1002) at Fig. 6 (rotated 90‐degrees); see also, e.g.,
`
`then used to identify a cache row.
`then used to identify a cache row.
`process is performed by a CRC engine 104 on the address to generate a CRC. This code is
`process is performed by a CRC engine 104 on the address to generate a CRC. This code is
`MAC DA, or network DA) is received by the ACA 26. A Cyclic Redundancy Code (CRC)
`MAC DA, or network DA) is received by the ACA 26. A Cyclic Redundancy Code (CRC)
`At a high level, a cache lookup occurs as follows. An address to be searched (MAC SA,
`At a high level, a cache lookup occurs as follows. An address to be searched (MAC SA,
`
`Cheriton:
`
`’951 Patent:
`
`Cheritonaddresses SRAMs in the same way as the ’951
`
`
`
`17
`
`Cheriton(EX1002) at Fig. 6 (with 4‐way data comparisons annotated); 10:46‐59; see also, e.g.,
`
`Seshan Decl. (EX1007) at ¶¶ 90‐94
`
`Cheritonuses SRAM data in the same way as the ’951
`
`
`
`18
`
`E.g.,Cheriton(EX1002) at 9:48‐56, Fig. 7; Petition (Paper 3) at 39, 58‐59, 64
`
`functions” could also be used.
`index into its SRAMs, but notes that “other hash
`Cheritonuses an XOR function to generate a hash to
`
`E.g.,Cheriton(EX1002) at 9:34‐38, 10:46‐49; Petition (Paper 3) at 30‐31
`
`that those SRAMs are row‐based.
`associative cache, but does not explicitly acknowledge
`Cheritondescribes using SRAMs to form a 4‐way set
`
`’951 patent at Abstract
`E.g.,Cheriton(EX1002) at Abstract, 1:20‐24; Petition (Paper 3) at 21‐24, 5‐6;
`
`the same type of device described in the ‘951 patent.
`switch network traffic based on network addresses—
`Cheritonis directed at a network device used to route/
`
`Applied Prior Art: Cheriton
`
`
`
`19
`
`Jain(EX1003) at 6:1‐4; Petition (Paper 3) at 57
`Cheriton).
`XOR‐basedhashing function (such as used in
`hashing a network address as an alternative to an
`Jaindiscloses the use of a CRChashing function in
`
`received Frame”
`to compare with the Destination Address of each
`Jainmaintains a “set of addresses that the station uses
`
`Jain(EX1003) at 3:3‐5; Petition (Paper 3) at 57
`
`address.”
`device to “efficiently recognize a received [network]
`Jainis directed to an approach for enabling a network
`
`Jain(EX1003) at 2:3‐4; Petition (Paper 3) at 57
`
`Applied Prior Art: Jain
`
`
`
`20
`
`Hashing Comparison(EX1021) at 1571; Reply (Paper 14) at 10
`
`–Emphasizes that selection of CRC hash instead of XOR is a
`
`design choice
`
`–CRC known as “excellent hashing functions” in network
`–A “CRC provides an almost optimal hashing function”
`Hashing Comparison:
`
`address lookup applications
`
`Hashing Comparison(EX1021) at Title, Reply (Paper 14) at 10
`for Address Lookup in Computer Networks” (1992)
`Jain also authored “A Comparison of Hashing Schemes
`
`Contemporaneous Jain articles support obviousness
`
`
`
`21
`
`HN
`
`Issues Raised
`
`
`
`UmflmmmmSmm_
`
`
`
`22
`
`D.I. (Paper 8) at 19‐22; Order (Paper 15) at 1
`
`–Instituted after SASdecision
`Claims 1‐6, 12‐14, and 21‐24:
`–Obvious over Cheritonand Jain
`Claims 8 and 11:
`
`Board’s Decisions on Institution
`
`
`
`23
`
`Board Decision on Request for Reh’g (Paper 11) at 3, 4
`
`–And “disclosures in Cheriton that Petitioner relied upon fail to
`
`disclose or suggest the use of rows in caches.”
`
`likelihood of prevailing on the obviousness challenge”
`
`–However, “the Petition failed to demonstrate a reasonable
`
`–“use of rows in 4‐way associative caches may have been
`Claims 1‐6, 12‐14, and 21‐24
`
`known…”
`
`Patent Owner Resp. (Paper 12) at Table of Contents
`
`–Rationales for substituting Jain’sCRC‐based hash for Cheriton’s
`Claims 8 and 11
`
`XOR hash
`
`–Input and output “packetizers”
`
`Issues Raised By Patent Owner and/or Board
`
`
`
`24
`
`–did notidentify any secondary considerations of non‐
`–did notseek to depose Petitioner’s expert
`–did notprovide any rebuttal expert declaration
`Patent Owner
`
`obviousness
`
`Preponderance of Evidence shows Unpatentability
`
`
`
`25
`
`Obviousness of Claims
`Applied Prior Art and
`
`
`
`26
`
`Hashing Comparison(EX1021) at 1571; Petitioner Reply (Paper 14) at 3‐6
`
`–CRC hashes known as “excellent hashing functions,” and
`–A “CRC provides an almost optimal hashing function”
`Hashing Comparisonstates:
`
`specifically in network address lookup applications
`
`Cheriton(EX1021) at 9:48‐51; Petitioner Reply (Paper 14) at 10‐11
`
`–“it will be apparent to anyone skilled in the art that other
`–XOR function “is used for illustration only”
`used in its system as an alternative to XOR function
`Cheritonconfirms that other hash functions may be
`
`hash functions from the one shown can be used.”
`
`Claims 8 & 11 ‐Obvious to use CRC instead of XOR hash in Cheriton
`
`
`
`27
`
`Petitioner Reply (Paper 14) at 3‐6; Petition (Paper 3) at 19‐20
`
`data validation (Amendment (EX1017) at 2‐3 (02/09/99))
`•’951 file history acknowledged existing CRC circuit use for
`
`•Jain(EX1003) at 3:49‐4:7, 11:5‐6 (desirability of reducing
`
`circuitry, power)
`
`–Leverage/re‐use existing CRC computation resources
`
`–Improve performance by avoiding problems recognized in
`Motivations to use CRC hashes:
`
`•Cache misses when collisions force deletion of earlier‐
`Cheriton:
`
`Petitioner Reply at 4‐6)
`learned mappings (Cheriton(EX1002) 10:60‐11:5,
`
`Claims 8 & 11 ‐Obvious to use CRC instead of XOR hash in Cheriton
`
`
`
`28
`
`Petitioner Reply (Paper 14) at 6‐12; Petition (Paper 3) at 59‐60, 65
`
`2.Obvious as substitution of one well‐known element for
`–Finite number of hash functions (Hashing Comparison(EX1021))
`
`–Dr. Seshan testified that substitution would be routine
`–Hashing Comparison(EX1021) analyzed CRC, XOR as substitutes
`–Jainindicated interchangeability between CRC and XOR (6:1‐4)
`–Cheritonexplicitly confirmed substitutes would work (9:48‐15)
`another to obtain predictable results
`
`1.Obvious to try
`
`Claims 8 & 11 ‐Obvious to use CRC instead of XOR hash in Cheriton
`
`
`
`29
`
`Petitioner Reply (Paper 14) at 7‐8; Petition (Paper 3) at 59‐60, 65
`
`–Modular, building‐block nature of hash functions
`–CRC already in use in network devices (Id. at §IV)
`
`(EX1021))
`Cheriton—network address lookup (Hashing Comparison
`–CRCs known to work efficiently in the same application as
`The POSA would expect success using CRC hashes
`
`Claims 8 & 11 ‐Obvious to use CRC instead of XOR hash in Cheriton
`
`
`
`30
`
`E.g., Petitioner Reply (Paper 14) at 9, 11
`
`–In re Kahn, 441 F.3d 977, 990 (Fed. Cir. 2006) (“the law does not require
`
`that the references be combined [in a particular manner].”)
`
`–Allied Erecting & Dismantling Co. v. Genesis Attachments, LLC, 825 F.3d
`not a requirement for obviousness
`A roadmap on how to physically combine references is
`
`the primary reference.”)
`secondary reference may be bodily incorporated into the structure of
`1373, 1381 (Fed. Cir. 2016) (“test…is not whether the features of a
`
`Patent Owner’s ‘questions’ on Claims 8 and 11
`
`
`
`31
`
`E.g., Reply (Paper 14) at 11‐12; Hashing Comparison(EX1021) at §§IV, VII
`
`–“(d) why replacing the hash function logic with Jain’s CRC hashing would
`
`•CRCs and XORs were interchangeable
`have been ‘a routine substitution’”
`
`–“(c) why one of skill in the art would seek to change Cheriton’s hash
`
`•Better performance
`function logic”
`
`•Lower “thrashing” and/or resource re‐use
`
`–“(b) what effects such incorporation might have”
`
`•CRC known as a direct substitute for XOR with same interface (two
`Cheriton”
`
`–“(a) how Jain’s CRC hashing would be incorporated into the system of
`substitution:
`questions regarding “effects” of and motivations for
`Petitioner’s Reply addressed each of Patent Owner’s
`
`or more sets of bits as inputs, one binary output)
`
`Patent Owner’s ‘questions’ on Claims 8 and 11
`
`
`
`32
`
`E.g., ‘951 patent at 7:38‐58 (input packetizer), 9:16–42 (output packetizer))
`
`number to output network card
`“output packetizer”: Circuitry that sends SA, DA and port
`input frame, along with hash output for cache lookup
`1.
`“input packetizer”: Network card that sends SA, DA from
`Examples of packetizers cited by Board in ‘951 patent
`
`2.
`
`D.I. (Paper 8) at 20‐21 (citing ‘951 patent at e.g., 7:45‐50, 7:56‐58 (input), 9:16–18 (output))
`
`–Does not “require that ‘packets’ be in a specialized form.” (Id.)
`
`–The “assembly” and/or “reformatting” of “units of information
`Board’s understanding of “packetizer”:
`
`components.” (D.I. (Paper 8) at 21)
`or data” that are “transmitted between devices or
`
`Cheritondisclosed input and output “packetizers”
`
`
`
`33
`
`E.g., Petition at 64, 21‐24, Cheriton(EX1002) at Figs. 4, 7, 5:32‐34, 10:42‐45
`
`–Network hardware that transmits (to cache) SA and DA from
`
`–Includes hash function logic, “switch hardware 409”
`input frame, along with hash output for cache lookup
`
`•Cheriton’sdisclosure of “input packetizer”
`
`Cheritondisclosed input “packetizer”
`
`
`
`34
`
`E.g., Petition at 67‐68, 21‐24, Cheriton(EX1002) at Fig. 6, 10:57‐59, Fig. 4
`
`hardware 409”
`(onto which that record is assembled), and/or “switch
`
`–Includes “tri‐state buffer,” “virtual path record,” “bus 633”
`along with port number, to the output portion of the device
`
`–Circuitry that transmits SA and/or DA (found in lookup),
`
`•Cheriton’sdisclosure of “output packetizer”
`
`Cheritondisclosed output “packetizer”
`
`
`
`35
`
`1‐6, 12‐14, and 21‐24
`Row‐related Claims:
`
`
`
`36
`
`E.g., Petition (Paper 3) at 23, 30‐31, 39‐40; Suppl. Reply (Paper 18) at 1‐2
`
`without such disclosure in Cheriton
`based SRAMs (corroborated by Fujishima) in Cheritoneven
`
`–However, it would have been obviousto use known row‐
`
`–“[D]isclosures in Cheriton that Petitioner relied upon fail to
`Claims 1‐6, 12‐14, and 21‐24
`
`disclose or suggest the use of rows in caches.”
`
`Board Decision on Request for Reh’g (Paper 11) at 3, 4;
`
`Obvious to perform Cheriton’sactions using row‐based SRAMs
`
`
`
`37
`
`E.g., Petition (Paper 3) at 23, 30‐31, 39‐40; Suppl. Reply (Paper 18) at 1‐2
`
`was obvious)
`SRAMs(the structure that the record demonstrates
`disclosed actions on its disclosed data in row‐based
`It would have been obvious to perform Cheriton’s
`
`–E.g., using a hash index to “identify” address data in an
`claimed datain SRAMs
`Cheriton explicitly taught the claimed actions on the
`
`SRAM for claim element 2(f)
`
`Obvious to perform Cheriton’sactions using row‐based SRAMs
`
`
`
`38
`
`See, e.g., Petition (Paper 3) at 21‐24; D.I. (Paper 8) at 14‐15; Suppl. Reply (Paper 18) at 1‐2
`
`Row‐basedSRAM
`
`Row‐basedSRAM
`
`
`
`
`
`
`
`
`
`Information”
`“First address
`
`Port information
`
`
`
`?? ? ?? ?
`
`Row‐basedSRAM
`
`with a rowin SRAM
`Value associated
`
`Row‐basedSRAM
`
`<N/A>
`
`Row‐basedSRAM
`
`Structure
`
`address
`Destination
`“value”
`Address/index
`address
`Encoded/hashed
`addresses
`Network
`addresses
`Network
`Data
`in which Cheritonstores its data
`Main dispute is the structureon which Cheritonperforms its actionsand
`
`
`
`
`
`
`
`
`
`
`
`in SRAM
`Retrievingfrom entry
`identifya forwarding port
`Readingfrom SRAM to
`address in SRAM cache
`Comparingwith destination
`coded address
`Comparingto hash/
`entries in SRAM
`Used for identifying
`a CRC hash function
`Encodingusing, e.g.,
`In SRAM
`Arrangingin entries
`Action
`
`
`
`
`
`
`
`
`
`
`
`Cheritondiscloses the claimed actionson the claimed data
`
`
`
`39
`
`Resulting data
`
`Row <n>
`
`Row 2
`
`Row 1
`
`“row address signal”
`
`45, 13:14‐18 (storage), 12:49‐54 (locating), Fig. 9; Seshan Decl. (EX1007) at ¶¶ 62, 86‐88
`E.g., Petition (Paper 3) at 23; Suppl. Reply (Paper 18) at 1‐3 ;Fujishima(EX1019) at 5:38‐
`–Locate/identify their data by rows using row addresses
`–Store their data in rows
`–Are arranged in rows
`Known row‐based SRAMs:
`
`Row‐based SRAMs were known
`
`
`
`40
`
`“way” entries A1‐D1) (excerpted; emphases added); Petition at 23; Suppl. Reply at 2‐3
`Fujishima(EX1019) at 5:38‐45, 12:49‐54, 13:14‐18; Fig. 9 (row‐based SRAMs with 4
`
`address buffer 46 for selecting one row in the SRAM memory cell array”
`[which] is responsive to a cache row address signal applied from a cache
`–“SRAM memory cell array 12 is provided with a cache row decoder 43….
`to one row in the ways A, B, C and D in the SRAM memory cell array 12.”
`four rows in the block BK1 in the DRAM memory cell array 1 are transferred
`–“In FIG. 9, a state is shown in which data Al, B1, C1 and D1 corresponding to
`
`–“The second [SRAM] memory cell array is divided intoa plurality of regions
`SRAMs arranged and accessed as rows were known:
`
`each comprising the same number of a plurality of rows”
`
`Row‐based SRAMs were known
`
`
`
`41
`
`E.g., Suppl. Reply (Paper 18) at 3; Ross(EX2001) at 1:38‐67; Fig. 9; 7:34
`
`•Rossdoes not disclose an alternative to row‐based SRAMs
`
`•Tree‐based indexes in Patent Owner’s Rosspatent were
`
`situated in an “array” (row‐based) memory
`
`–No other type of SRAM in evidence
`
`–Undisputed expert testimony that POSA would expect SRAMs used
`Row‐based SRAMS were common, if not only, type of SRAM
`
`understanding of a person of ordinary skill in the art.”
`measured in rows, consistent with the Fujishima reference and the
`also describes such a cache as a 4‐way set associative cache with a depth
`August 9, 1990, at 12:49‐54 (EX1019) (“Fujishima”). The ’951 patent itself
`organize the sets as entries in a row. (See, e.g., U.S. 5,226,147, filed
`associative cache (equivalently a 4‐way set associative cache) would
`•“A person of ordinary skill in the art would understand that a 4‐set
`in associative caches to be row based
`
`Seshan Decl. (EX1007) at ¶¶ 62‐64; Petition (Paper 3) at 22‐23
`
`Row‐based SRAMs were known
`
`
`
`42
`
`Petition (Paper 3) at 8‐10 (citing Steely(EX1012) at Fig. 3 (excerpt)
`
`bb
`
`Row‐based SRAMs were known
`
`
`
`43
`
`18) at 3‐8
`(Paper 3) at 21‐24; Suppl. Reply (Paper
`E.g., Cheriton(EX1002) at Fig. 6; Petition
`
`314.” (Cheriton(EX1002) at 7:24‐27)
`source address field 312, the optional type field 313, and the input port field
`“The tag field 310 has four subfields: the destination address field 311, the
`
`virtual path index 630” (Cheriton(EX1002) at 9:38‐40)
`“The tag field 310 [from each set of SRAMs]will be compared against the
`
`cache 601 then comparator 611 will indicate a ‘hit’” (Cheriton 10:49‐54)
`611 through 614. Assuming a valid virtual path tag was found in SRAM
`from the four set associate cache 601 through 604 via the four comparators
`“The virtual path index is further compared in parallel against the outputs
`Action: Using/Comparing(address) data within SRAMs:
`
`601 through 604.” (Cheriton(EX1002) at 9:34‐38; emphasis added)
`turn looks up the four parallel sets of the virtual path cache SRAMs
`which in turn produces a virtual patch cache index 632 which in
`address pair of the incoming datagram, enters hash function 631
`“The virtual path index 630, which is the source‐destination
`Action: Locating data within SRAMs:
`added)
`comparators 611.” (Cheriton(EX1002) at 9:29‐33; emphasis
`memory 601 through 604,each equipped with a set of
`set associative cache built with four banks of high‐speed static
`“The virtual path cache illustrated in FIG. 6 is organized as a 4‐
`Action:Arrangingdata as entries in SRAMs:
`
`Cheritondisclosed the claimed actionson SRAMs
`
`
`
`44
`
`See, e.g., Cheriton(EX1002) at Fig. 6 (with row annotations added in red);
`
`Petition (Paper 3) at 21‐24; Suppl. Reply (Paper 18) at 3‐8
`
`Row <n>
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`Obvious to perform Cheriton’s actions on row‐based SRAMs
`
`
`
`45
`
`Petition (Paper 3) at 21‐24; Suppl. Reply (Paper 18) at 3‐8
`Cheriton(EX1002) at Fig. 6 (with row annotations added in red);
`
`Row <n>
`
`Action: Using/Comparing(address) data within row‐basedSRAMs:
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`Action: Locating data within row‐basedSRAMs:
`
`Action:Arrangingdata as entries in row‐basedSRAMs:
`
`Row‐based SRAM use obvious in view of Cheriton
`
`
`
`46
`
`30‐31; Suppl. Reply (Paper 18) at 3‐5
`See, e.g., Seshan Decl. (EX1007) at ¶¶ 62‐64, 86‐89; Petition (Paper 3) at 22‐23,
`
`–Dr. Seshan showed that SRAMs were known to be row‐based
`
`–Cheritonand Fujishimaused SRAMs in the same type of 4‐way set
`identical type of memory devices Cheritonuses
`
`3.Obvious as application of a well‐known technique to the
`
`associate caches
`
`–Single‐reference obviousness supported when the modification is
`
`“known to be one of the most common options”
`
`–Few if any other ways to arrange and use SRAM in evidence
`
`2.Obvious to modify
`
`1.Obvious to try
`
`Obvious to use Row‐based SRAMs in Cheriton
`
`
`
`47
`
`See, e.g., Suppl. Reply (Paper 18) at 4‐5
`
`–Generic, readily‐available building blocks
`–No other type of SRAM in evidence
`–History of successful use of such SRAMs
`SRAMs
`The POSA would except success using row‐based
`
`Obvious to use Row‐based SRAMs in Cheriton
`
`
`
`48
`
`grasp”)
`reason to pursue the known options within his or her technical
`(obvious to try because “a person of ordinary skill has good
`–See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007)
`
`–Cubist Pharms., Inc. v. Hospira, Inc., 805 F.3d 1112, 1129 (Fed. Cir.
`most common” options (e.g., row‐based SRAMs)
`Modification obvious when it was “known to be one of the
`
`2015)
`
`reference obviousness)
`SFC Co., 870 F.3d 1376, 1380‐82 (Fed. Cir. 2017) (affirming single‐
`832 F.3d 1355, 1361 (Fed. Cir. 2016); see alsoIdemitsu Kosan Co. v.
`1336, 1346‐47 (Fed. Cir. 2018); citing Arendi S.A.R.L. v. Apple Inc.,
`
`–Monsanto Tech. LLC v. E.I. DuPont de Nemours & Co., 878 F.3d
`would have been obvious to modify that reference
`Single reference can render a patent obvious when it
`
`Obvious to use Row‐based SRAMs in Cheriton
`
`
`
`49
`
`See, e.g., Suppl. Reply (Paper 18) at 5‐8; Petition (Paper 3) at 30‐33, 37‐40, 45
`
`–2(g) [2(i)]: “retrieving first [second] address information from a [said]
`
`first entry of said identified row”
`
`–1(h): “in the event of a match…with said row, comparing said received
`Using/Comparingdata within SRAM rows
`–1(g): “comparing said coded address to a value associated with a row”
`
`with a first entry in said row”
`destination address with a cached destination address associated
`
`–2(f): “using said received, encoded address information to identify
`Locatingdata within SRAM rows
`
`one of said cache rows”
`
`–21(c): “a cache having plural rows, each of said rows having plural
`
`entries”
`
`–2(b): “having a cache comprised of plural rows, each having plural
`Arrangingdata in SRAM rows (and within entries)
`Each “row” limitation would have been obvious
`
`respective entries”
`
`
`
`50
`
`text); see alsoSuppl. Reply (Paper 18) at 5‐6; Petition (Paper 3) at 32‐33, 45
`Cheriton (EX1002) at Fig. 6 (with row and entry annotations added in red and associated
`
`(Cheriton9:38‐40)
`virtual path index 630”
`compared against the
`each set of SRAMs will be
`“The tag field 310 from
`
`Row <n>
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`at 9:29‐33; emphasis added)
`a set of comparators 611.” (Cheriton(EX1002)
`[SRAM] 601 through 604,each equipped with
`with four banks of high‐speed static memory
`organized as a 4‐set associative cache built
`“The virtual path cache illustrated in FIG. 6 is
`
`patent at 5:14‐17; emphasis added)
`cache entries, one per Set.” (’951
`wide. Each cache row contains four
`maximum of 16K rows, and is 88 bits
`associative, can vary in depth up to a
`address cache 28 is 4‐way Set
`“In a preferred embodiment, the
`
`Row 2
`Row 1
`1stEntry 2ndEntry 3rdEntry 4thEntry
`
`Row 2
`Row 1
`
`Row 2
`Row 1
`
`Row 2
`Row 1
`
`row has four entries
`When four row‐based SRAMs are used in Cheriton, each
`
`Obvious to perform Cheriton’s actions on row‐based SRAMs
`
`
`
`51
`
`with id. at Fig. 3 (excerpted); Petition (Paper 3) at 32‐33; Suppl. Reply (Paper 18) at 5‐6
`Cheriton(EX1002) at Fig. 6 (with row/entry annotations added and associated text) overlaid
`
`Entry Entry
`First Second
`
`(Cheritonat 9:38‐40)
`virtual path index 630”
`compared against the
`each set of SRAMs will be
`“The tag field 310 from
`
`Row <n>
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`Row <n>
`
`Row 2
`Row 1
`
`row…
`entry of said identified
`information from a first
`…retrieving first address
`Claim 2:
`
`individual SRAM also has multiple entries (fields)
`When row‐based SRAMs are used in Cheriton, each
`
`Obvious to perform Cheriton’s actions on row‐based SRAMs
`
`
`
`52
`
`See also Petition (Paper 3) at 30‐31; Suppl. Reply (Paper 18) at 7‐8
`
`–Patentee indicated that “comparison” term in claim 1 looks up entries using
`’951 patent file history:
`
`5; emphasis added)
`address….used to index rowsof a
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