IPR2017-01430 Petition
`Patent 5,978,951
`
`DOCKET NO.: 2211726-00145
`Filed on behalf of Unified Patents Inc.
`By: David L. Cavanaugh, Reg. No. 36,476
`Daniel V. Williams, Reg. No. 45,221
`Wilmer Cutler Pickering Hale and Dorr LLP
`1875 Pennsylvania Ave., NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
`
`Roshan Mansinghani, Reg. No. 62,429
`Jonathan Stroud, Reg. No. 72,518
`Unified Patents Inc.
`1875 Connecticut Ave. NW, Floor 10
`Washington, DC, 20009
`Tel: (202) 805-8931
`Email: Roshan@unifiedpatents.com
`Email: jonathan@unifiedpatents.com
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________________________________
`UNIFIED PATENTS INC.
`Petitioner
`v.
`PLECTRUM LLC
`Patent Owner
`IPR2017- 01430
`Patent 5,978,951
`PETITION FOR INTER PARTES REVIEW OF
`US PATENT NO. 5,978,951
`CHALLENGING CLAIMS 1-6, 8, 11-14, AND 21-24
`UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104
`
`
`
`

`

`IPR2017-01430 Petition
`Patent 5,978,951
`
`TABLE OF CONTENTS
`
`I. 
`
`2. 
`
`Page
`MANDATORY NOTICES ............................................................................. 1 
`A. 
`Real Party-in-Interest ............................................................................ 1 
`B. 
`Related Matters ...................................................................................... 1 
`C. 
`Counsel .................................................................................................. 2 
`D. 
`Service Information, Email, Hand Delivery and Postal ........................ 2 
`CERTIFICATION OF GROUNDS FOR STANDING .................................. 2 
`II. 
`III.  OVERVIEW OF CHALLENGE AND RELIEF REQUESTED .................... 3 
`A. 
`Prior Art Patents and Printed Publications ............................................ 3 
`1. 
`US Patent 6,091,725 (filed on December 29, 1995,
`published on July 18, 2000) (“Cheriton” (EX1002)),
`which is prior art under 35 U.S.C. § 102(e) ................................ 3 
`European Patent Application No. EP0522743A1
`(“Jain” (EX1003)), which is prior art under 35 U.S.C.
`§ 102(b) ....................................................................................... 3 
`Kessler et al., “Inexpensive Implementations of Set-
`Associativity”, 17:3 ACM SIGARCH Computer
`Architecture News – Special Issue: Proceedings of the
`16th annual international symposium on Computer
`Architecture 131 (June 1989) (“Kessler” (EX1004)),
`which is prior art under 35 U.S.C. § 102(b) ............................... 3 
`Grounds for Challenge .......................................................................... 4 
`B. 
`IV.  TECHNOLOGY BACKGROUND ................................................................. 4 
`V.  OVERVIEW OF THE ’951 PATENT .......................................................... 11 
`A. 
`Summary of the Alleged Invention ..................................................... 11 
`B. 
`Level of Ordinary Skill in the Art ....................................................... 16 
`C. 
`Prosecution History ............................................................................. 16 
`VI.  CLAIM CONSTRUCTION .......................................................................... 18 
`A. 
`“code generator,” (claim 1), “coded address,” (claim 1), and
`“encoding” (claim 2) ........................................................................... 19 
`
`3. 
`
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`

`B. 
`
`IPR2017-01430 Petition
`Patent 5,978,951
`VII.  SPECIFIC GROUNDS FOR PETITION ...................................................... 20 
`A.  Ground I: Claims 1, 2, and 21 are rendered obvious by
`Cheriton as understood by a person of ordinary skill in the
`art ......................................................................................................... 21 
`1. 
`Overview of Cheriton ............................................................... 21 
`2. 
`Claim 1 is obvious in view of Cheriton and ordinary
`skill ............................................................................................ 24 
`Claim 2 is obvious in view of Cheriton .................................... 37 
`3. 
`Claim 21 is obvious in view of Cheriton .................................. 43 
`4. 
`Ground II: Claims 3, 5, and 6 are rendered obvious by
`Cheriton in view of Kessler ................................................................. 51 
`1. 
`Overview of Kessler.................................................................. 51 
`2. 
`Claim 3 is obvious in view of Cheriton and Kessler ................ 52 
`3. 
`Claim 5 is obvious in view of Cheriton and Kessler ................ 54 
`4. 
`Claim 6 is obvious in view of Cheriton and Kessler ................ 56 
`Ground III: Claims 4 and 22-24 are rendered obvious by
`Cheriton in view of Kessler in view of Jain ........................................ 57 
`1. 
`Overview of Jain ....................................................................... 57 
`2. 
`Claim 4 is obvious in view of Cheriton, Kessler, and
`Jain ............................................................................................ 58 
`Claim 22 is obvious in view of Cheriton and Jain .................... 59 
`3. 
`Claim 23 is obvious over Cheriton and Jain ............................. 60 
`4. 
`Claim 24 is obvious over Cheriton, Kessler, and Jain .............. 61 
`5. 
`D.  Ground IV: Claims 8 and 11-14 are rendered obvious by
`Cheriton in view of Jain ...................................................................... 62 
`1. 
`Claim 8 is obvious in view of Cheriton and Jain ...................... 62 
`2. 
`Claim 11 is obvious in view of Cheriton and Jain .................... 69 
`3. 
`Claim 12 is obvious in view of Cheriton and Jain .................... 69 
`4. 
`Claim 13 is obvious in view of Cheriton and Jain .................... 70 
`5. 
`Claim 14 is obvious in view of Cheriton and Jain .................... 71 
`VIII.  CONCLUSION .............................................................................................. 72 
`
`C. 
`
`
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`IPR2017-01430 Petition
`Patent 5,978,951
`
`I. MANDATORY NOTICES
`A. Real Party-in-Interest
`Pursuant to 37 C.F.R. § 42.8(b)(1), Unified Patents Inc. (“Unified” or
`
`“Petitioner”) certifies that Unified is the real party-in-interest, and further certifies
`
`that no other party exercised control or could exercise control over Unified’s
`
`participation in this proceeding, the filing of this petition, or the conduct of any
`
`ensuing trial. In this regard, Unified has submitted voluntary discovery. See EX1020
`
`(Petitioner’s Voluntary Interrogatory Responses).
`
`B. Related Matters
`US Pat. No. 5,978,951 (“’951 patent” (EX1001)) is owned by Plectrum LLC
`
`(“Plectrum” or “Patent Owner”).
`
`The ’951 patent is the subject of the following Eastern District of Texas
`
`district court proceedings:
`
`Plectrum LLC v. Nokia USA Inc. et al, 4-17-cv-00140; Oracle Corporation et
`
`al, 4-17-cv-00141; AT&T Inc. et al, 4-17-cv-00120; Broadcom Corporation et al, 4-
`
`17-cv-00121; Comcast Corporation et al, 4-17-cv-00123; NEC Corporation of
`
`America et al, 4-17-cv-00125; Verizon Communications, Inc. et al, 4-17-cv-00126;
`
`Facebook, Inc., 4-17-cv-00081; Fortinet, Inc., 4-17-cv-00082; Huawei Technologies
`
`USA, Inc., 4-17-cv-00083; Juniper Networks, Inc., 4-17-cv-00084; Arista Networks,
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`IPR2017-01430 Petition
`Patent 5,978,951
`Inc., 4-17-cv-00076; Brocade Communications Systems, Inc., 4-17-cv-00077; Cisco
`
`Systems, Inc., 4-17-cv-00078; and Extreme Networks, Inc., 4-17-cv-00079.
`
`C. Counsel
`David L. Cavanaugh (Reg. No. 36,476) will act as lead counsel; Roshan
`
`Mansinghani (Reg. No. 62,429) will act as primary back-up counsel; Jonathan
`
`Stroud (Reg. No. 72,518) and Daniel Williams (Reg. No. 45,221) will act as back-
`
`up counsel.
`
`D.
`Service Information, Email, Hand Delivery and Postal
`Unified consents to electronic service at david.cavanaugh@wilmerhale.com
`
`and roshan@unifiedpatents.com. Petitioner can be reached at Wilmer Cutler
`
`Pickering Hale and Dorr, LLP, 1875 Pennsylvania Ave., NW, Washington, DC
`
`20006, Tel: (202) 663-6000, Fax: (202) 663-6363, and Unified Patents Inc., 1875
`
`Connecticut Ave. NW, Floor 10, Washington, DC 20009, (650) 999-0899.
`
`II. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which review
`
`is sought is available for inter partes review and that Petitioner is not barred or
`
`estopped from requesting an inter partes review challenging the patent claims on the
`
`grounds identified in this Petition.
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`IPR2017-01430 Petition
`Patent 5,978,951
`III. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)–(2), Petitioner challenges
`
`claims 1-6, 8, 11-14, and 21-24 of the ’951 patent.
`
`A.
`Prior Art Patents and Printed Publications
`The following references are pertinent to the grounds of unpatentability
`
`explained below:
`
`1.
`
`2.
`
`3.
`
`US Patent 6,091,725 (filed on December 29, 1995, published on
`July 18, 2000) (“Cheriton” (EX1002)), which is prior art under
`35 U.S.C. § 102(e)
`
`European Patent Application No. EP0522743A1 (“Jain”
`(EX1003)), which is prior art under 35 U.S.C. § 102(b)
`
`Implementations of Set-
`Kessler et al., “Inexpensive
`Associativity”, 17:3 ACM SIGARCH Computer Architecture
`News – Special Issue: Proceedings of
`the 16th annual
`international symposium on Computer Architecture 131 (June
`1989) (“Kessler” (EX1004)), which is prior art under 35 U.S.C.
`§ 102(b)1
`
`
`
`
`
`
`1 EX1005 is a version of Kessler from the Library of Congress with a date stamp of
`
`1990. EX1006 is a Declaration from Scott Bennett establishing the public
`
`availability of Kessler before the ’951 patent filing date.
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`IPR2017-01430 Petition
`Patent 5,978,951
`
`B. Grounds for Challenge
`This Petition, supported by the declaration of Professor Srinivasan Seshan
`
`(“Seshan Declaration” or “Seshan” (EX1007)), requests cancellation of challenged
`
`claims 1-6, 8, 11-14, and 21-24 as unpatentable under 35 U.S.C. § 103. See 35
`
`U.S.C. § 314(a).
`
`IV. TECHNOLOGY BACKGROUND
`When the ’951 patent was filed, data communication networks were well
`
`known for years. (See, e.g., US5,566,170, filed Dec. 29, 1994, at 1:23-27 (EX1008))
`
`(“Bakke”). In such a network, one component is a switch which directs data units,
`
`such as data packets, from one network node to another. (See, e.g., Bakke at 1:31-
`
`33 (EX1008)). Such a device concentrates data packets from network devices
`
`received over a communication network, which then directs the packets over a
`
`network output to either the desired destination device or to another forwarding
`
`device (e.g., another switch or router). (See, e.g., Bakke at 2:11-20 (EX1008)).
`
`Various such devices existed, with different internal designs. However, every
`
`design generally incorporated the same functional components. (See Newman et al.,
`
`“IP Switching and Gigabit Routers”, IEEE Comm. Magazine 64 (Jan. 1997)
`
`(EX1009) (“IP Switching”)). Line cards were used to connect the physical network
`
`data link into a switch fabric (e.g., a crossbar switch). (IP Switching at 64
`
`(EX1009)). The switch fabric interconnected the various components of the device.
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`IPR2017-01430 Petition
`Patent 5,978,951
`(Id.) A forwarding engine would inspect packet headers, determine which outgoing
`
`line card should receive the packet, and rewrite the header as needed. (Id.) A
`
`network processor handles routing, including generating routing tables (also called
`
`forwarding information bases) for the forwarding engine, and handles general
`
`network management. (Id.) These known functional blocks could be in various
`
`physical arrangements. For example, it was known that the forwarding engine could
`
`be combined with the network processor. (IP Switching at 64 (EX1009)). The figure
`
`below illustrates one potential system along these lines:
`
`
`
`As network rates increased, the packet forwarding rate needed likewise
`
`increased. (IP Switching at 64 (EX1009)). IP Switching summarizes two known
`
`approaches for a forwarding engine. (Id. at 64-65). One known approach employed
`
`an application specific integrated circuit (ASIC) designed for forwarding, while the
`
`other known approach employed a general-purpose processor combined with
`
`destination address caching in an on-chip cache. (Id. at 64-65). In either approach,
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`IPR2017-01430 Petition
`Patent 5,978,951
`the core functionality is looking up the correct next destination to route or switch to,
`
`including the correct outbound interface (i.e., the right port in the right line card)
`
`based on the destination address of a packet. (Id. at 65). The figure below shows
`
`the path a packet could take in such a transaction.
`
`
`
`(Seshan ¶28 (EX1007)). First, the packet is sent from the network device and
`
`received at an input on a line card in the switching device. (Seshan ¶29 (EX1007)).
`
`The line card passes the packet to the switch fabric. (Seshan ¶29 (EX1007)). The
`
`switch fabric passes the packet to the forwarding engine. (Seshan ¶29 (EX1007)).
`
`The forwarding engine determines the appropriate line card and output to send the
`
`packet to and transmits the output destination to the switch fabric. (Seshan ¶29
`
`(EX1007)). The switch fabric then passes the packet to the appropriate line card,
`
`which transmits it to the appropriate recipient network device. (Seshan ¶29
`
`(EX1007)).
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`IPR2017-01430 Petition
`Patent 5,978,951
`It was well known to perform the outbound interface lookup described in IP
`
`Switching using a cache. A cache is a high-speed memory used to provide quick
`
`access to frequently used data. (Seshan ¶30 (EX1007)). A 1996 patent describes
`
`such a system. (US 5,914,938, filed November 19, 1996, at Abstract (EX1010))
`
`(“Brady”). In Brady, a “search key” comprising a destination address is used to
`
`generate an identifier using “hashing” (a mathematical technique of transforming
`
`data into a shorter representation). (Id. at 3:3-5 5:35-37; see also US 5,917,821, filed
`
`Dec. 21, 1994, at 3:14-19, FIG. 5 (EX1011)). The identifier is used to index into a
`
`storage containing one or more stored entries. (Brady at 2:64-3:1 (EX1010)). Then,
`
`each stored entry is compared to the original search key in order to determine if the
`
`entry matches the search key (i.e., is the correct entry). (Id. at 2:66-3:1).
`
`Thus, network switching devices that could receive packets, process packet
`
`headers, lookup appropriate output ports in a cache using the destination address,
`
`and forward the received packet appropriately were well known at the time of the
`
`invention of the ’951 patent. (Seshan ¶31 (EX1007)).
`
`Specific cache hardware was also well known at the time of the invention of
`
`the ’951 patent. A cache is a “relatively small, random access memory (RAM) used
`
`to store a copy of memory data in anticipation of future use.” (US 5,509,135, filed
`
`Sept. 25, 1992, at 1:20-22 (EX1012)) (“Steely”). Various types of caches, such as
`
`direct-mapped and set-associative caches, were well known. (Id. at 1:65-25). In a
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`IPR2017-01430 Petition
`Patent 5,978,951
`set-associative cache, multiple RAMs are concurrently addressed to provide multiple
`
`entries for a single cache index. (Id. at 2:16-19). Conceptually, this may be
`
`illustrated as follows:
`
`Cache Index RAM 1 RAM 2 RAM 3 RAM 4
`Index 1
`···
`···
`···
`···
`Index 2
`···
`···
`···
`···
`Index 3
`···
`···
`···
`···
`Index 4
`···
`···
`···
`···
`
`
`
`For example, FIG. 3 of Steely, reproduced below, shows four data RAMs 31-34.
`
`(Steely at FIG. 3, 4:38-40 (EX1012)).
`
`The number of RAMs is the number of “ways” in the cache; for example, a
`
`cache using four RAMs is a “four-way set-associative cache.” (Id. at 2:19-25).
`
`
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`IPR2017-01430 Petition
`Patent 5,978,951
`Because the index refers to multiple RAMs, a “tag” is used to “uniquely identify
`
`blocks having . . . the same cache index.” (Id. at 1:48-64). A portion of FIG. 3 of
`
`Steely has been annotated and reproduced below to illustrate one such set of blocks
`
`with the same cache index. The blocks have different data even though they share a
`
`cache index because their respective addresses hashed to the same value (Seshan ¶33
`
`(EX1007)).
`
`
`
`
`
`
`
`
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`IPR2017-01430 Petition
`Patent 5,978,951
`The use of tags to distinguish the blocks can be illustrated as follows:
`
`RAM 1
`
`RAM 2
`
`RAM 3
`
`Cache
`Index
`Index 1 Tag11 Data11 Tag21 Data21 Tag31 Data31 Tag41 Data41
`Index 2 Tag12 Data12 Tag22 Data22 Tag32 Data32 Tag42 Data42
`Index 3 Tag13 Data13 Tag23 Data23 Tag33 Data33 Tag43 Data43
`Index 4 Tag14 Data14 Tag24 Data24 Tag34 Data34 Tag44 Data44
`
`RAM 4
`
`In operation, a set-associative cache works as follows. A cache access causes
`
`each of the RAMs in the set to be examined at the corresponding cache index
`
`location. The tag in the cache access request is compared to the tag in the stored
`
`cache blocks in order to distinguish between cache blocks with the same cache index
`
`but different addresses. (Steely at 2:26-34 (EX1012)).
`
`It was also known to use a type of memory called “content-addressable
`
`memory” in which the memory is indexed using identifiers derived from the desired
`
`information itself, rather than addresses of locations where the data is stored. (US
`
`4,377,855, filed Nov. 6, 1980, at 1:17-21 (EX1013)) (“Lavi”). In other words,
`
`instead of requesting that the cache return the value associated with a particular
`
`memory location, in a content-addressable memory you request that the cache return
`
`the value associated with a search key (e.g., data associated with a destination
`
`address in a network.) (Seshan ¶34 (EX1007)). Brady, described above, is thus a
`
`logical description of a set-associative content-addressable network address cache.
`
`(Seshan ¶34 (EX1007)).
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`IPR2017-01430 Petition
`Patent 5,978,951
`It was thus well-known in the art both to lookup addresses from packets in a
`
`cache to determine an output port, and to use a content-addressable cache memory
`
`(e.g., a 4-way set associative cache using content-addressable memory) as the lookup
`
`mechanism. (Seshan ¶35 (EX1007)).
`
`V. OVERVIEW OF THE ’951 PATENT
`A.
`Summary of the Alleged Invention
`The ’951 patent is generally directed to providing a hardware network address
`
`cache. (’951 patent, 1:23-31 (EX1001)). The address cache is responsible for
`
`maintaining address and age tables, searching the address table for addresses
`
`received in network frames, and returning address search results (such as the
`
`destination port(s) for the received frame). (’951 patent, 1:30-39 (EX1001)). Using
`
`this system, a frame is received, the addresses in the frame are looked up in the
`
`cache, and data associated with cached addresses (if any) is returned for use in
`
`processing the frame. (’951 patent, 1:41-52 (EX1001)).
`
`The ’951 patent admits that it was known to use software to parse frames to
`
`determine addresses, to lookup data for those addresses, and to process frames
`
`according to the associated data. (’951 patent, 1:15-17 (EX1001)). The alleged
`
`invention of the ’951 patent is a hardware approach to performing these functions
`
`that supposedly provides better performance by using a coded address in cache
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`IPR2017-01430 Petition
`Patent 5,978,951
`lookup. (’951 patent, 1:23-27; 2:20-22; 2:43-46 (EX1001)). This approach is
`
`described below.
`
`A given network device according to the ’951 patent incorporates one or more
`
`network interfaces connected to a motherboard via a backplane. (’951 patent, 3:26-
`
`30 (EX1001)). FIG. 1 of the ’951 patent illustrates this general structure.
`
`The motherboard incorporates an address cache ASIC with an associated
`
`cache, a frame processor, an application processor, and a master buffer. (’951 patent,
`
`3:25-30; 3:57-60 (EX1001)). FIG. 2 of the ’951 patent illustrates the motherboard
`
`and network interface modules in more detail. Color coding has been added to the
`
`figure to illustrate key components. (Seshan ¶39 (EX1007)).
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`IPR2017-01430 Petition
`Patent 5,978,951
`
`
`
`
`
`Each network interface module has one or more input ports 18 for receiving
`
`data, and one or more output ports 20 for sending data. (’951 patent, 3:31-35
`
`(EX1001)). When a frame is received via the input port(s) 18, the frame is passed
`
`to the receive header processor 46, which derives information from the header and
`
`passes that information to the address cache ASIC (ACA) 26. (’951 patent, 7:53-59
`
`(EX1001)).
`
`The ACA 26 has an associated cache 28. (’951 patent, 3:57-58 (EX1001)).
`
`Lookup of the addresses cached in associated cache 28 is the primary function of the
`
`ACA 26. (’951 patent, 4:20-21 (EX1001)). When the receive header processor 46
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`IPR2017-01430 Petition
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`passes source and destination addresses to the ACA 26, the ACA 26 uses those
`
`addresses to perform lookups. (’951 patent, 3:61-64 (EX1001)). In particular, after
`
`receiving one or more addresses, the ACA 26 searches the cache 28 for each received
`
`address and provides a response to the network interface module it received the
`
`packet from, which may include whether the address(es) were found in the cache 28,
`
`and any data associated with the cached address. (’951 patent, 4:20-33 (EX1001)).
`
`The ACA 26 and cache 28, as well as the lookup process, are described in more
`
`detail below. After lookup, either the frame is transmitted out of all output ports if
`
`the lookup failed, or the frame is forwarded to the appropriate output port(s) if the
`
`address is known. (’951 patent, 4:60-5:1 (EX1001)).
`
`In one embodiment, the cache 28 is a 4-way set associative cache. (’951
`
`patent, 5:14-15 (EX1001)). Each row of the cache is thus associated with one entry
`
`from each of the 4 sets. (’951 patent, 5:16-17 (EX1001)). FIG. 4A illustrates this
`
`arrangement of the cache 28.
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`IPR2017-01430 Petition
`Patent 5,978,951
`
`
`
`To locate data in the cache, a four step process is performed. First, the
`
`received address is coded to generate a coded address to use as a row identifier. In
`
`one embodiment, this coding is done by performing a Cyclic Redundancy Code
`
`process. (’951 patent, 5:25-30 (EX1001)). Second, the coded address is used to
`
`identify a cache row. (’951 patent, 5:29-30 (EX1001)). Third, a set within the row
`
`is chosen for examination, and the stored address is compared to the received address
`
`(i.e., the address prior to coding). (’951 patent, 5:30-37 (EX1001)). Optionally, the
`
`cache can check which sets contain valid data and which sets have been used more
`
`or less recently in order to determine which sets to use for comparison. (’951 patent,
`
`5:30-34 (EX1001)). Finally, if a set has a matching address, the associated data is
`
`returned. (’951 patent, 5:37-39 (EX1001)). Using the data, the frame is forwarded
`
`appropriately. (’951 patent, 4:60-5:1 (EX1001)).
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`IPR2017-01430 Petition
`Patent 5,978,951
`
`B.
`Level of Ordinary Skill in the Art
`A person of ordinary skill in the art for the ’951 patent would have been an
`
`electrical engineer or computer engineer having a bachelor’s degree and two years
`
`of experience in designing network switching/routing hardware, or equivalent post-
`
`graduate education, such as a master’s degree focused in networking systems.
`
`(Seshan ¶45 (EX1007)).
`
`C.
`Prosecution History
`The ’951 patent issued from US Patent Application Number 08/927,336,
`
`which was filed on September 11, 1997 (File History, Application (12/11/97)
`
`(EX1014)). The original application included one claim. A Preliminary
`
`Amendment was filed on March 10, 1998 that added claims 2-26. (File History,
`
`Preliminary Amendment (03/10/98) (EX1015)). A non-final Office Action was
`
`mailed on November 9, 1998 that rejected claims 1-7 and allowed claims 8-26. (File
`
`History, Office Action (11/09/98) (EX1016)). The Examiner did not indicate why
`
`he believed claims 8-26 were allowable.
`
`The applicant filed an Amendment on February 9, 1999 that amended claim
`
`1 to change “CRC code” to “coded address.” (File History, Amendment at 2-3
`
`(02/09/99) (EX1017)). In support of the amendment, the applicant asserted:
`
`Claim 1 has been amended in order to delete references to ‘CRC
`code’ in order to remove any unintended suggestion that the
`encoding step was being utilized to ensure data validity after
`
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`IPR2017-01430 Petition
`Patent 5,978,951
`transmission, as for which cyclic redundancy checks are often
`used. Rather, in the present case, at least a portion of the
`received data unit is coded, such as with a cyclic redundancy
`code, to generate a reduced representation of that address.
`(Id. at 5 (EX1017)).
`
`Attempting to distinguish claim 1 from the prior art, the applicant argued the
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`following:
`
`Present claims 1 and 2 recite the coding of a portion of a
`received, destination address. This coded address is then used
`to index rows of a cache. Once a desired row has been identified
`based upon this indexing, one of plural entries is identified and
`a portion of the originally received destination address is
`compared against a cached address value associated with the
`identified entry. If a favorable comparison occurs, the entry
`contents are retrieved as an indication of how the received data
`is to be forwarded.
`(Id. (EX1017)).
`
`A Notice of Allowability was then mailed on March 15, 1999 allowing all
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`claims 1-26. (File History, NOA (03/15/99) (EX1018). The examiner did not
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`provide reasons for allowance. As described in detail below, the limitations argued
`
`as being absent from the prior art are found in the currently cited references.
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`IPR2017-01430 Petition
`Patent 5,978,951
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`VI. CLAIM CONSTRUCTION
`Claim terms of an unexpired patent in inter partes review are given the
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`“broadest reasonable construction in light of the specification.” 37 C.F.R.
`
`§ 42.100(b); In re Cuozzo Speed Techs., LLC 778 F.3d 1271, 1279–81 (Fed. Cir.
`
`2015). As the ’951 patent will expire on September 11, 2017, a district court-type
`
`(i.e., Phillips) claim construction may be applied for, upon request. 37 C.F.R. §
`
`42.100. In general, this standard gives claim terms their ordinary and customary
`
`meaning, as understood by one of ordinary skill in the art at the time of the invention.
`
`Phillips v. AWH Corp., 415 F.3d 1303, 1321 (Fed. Cir. 2005); Interthinx v. Corelogic
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`Sols., CBM2012-00007, Paper 16 at 15 (P.T.A.B. Jan. 31, 2013).
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`The Federal Circuit has explained that “the ‘ordinary meaning’ of a claim term
`
`is its meaning to the ordinary artisan after reading the entire patent.” Phillips, 415
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`F.3d at 1321. Therefore, the specification provides the primary basis for construing
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`the claims. Id. at 1315. Dictionaries, encyclopedias, and treatises can also inform
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`the ordinary meaning of a claim term, id. at 1322–23, so long as this extrinsic
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`evidence “does not contradict any definition found in or ascertained by a reading of
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`the patent documents,” Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1584
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`n.6 (Fed. Cir. 1996). The only exceptions to giving the words in a claim their
`
`ordinary meaning are 1) when the applicant acts as his own lexicographer; and 2)
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`when the applicant disavows or disclaims the full scope of a claim term in the
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`IPR2017-01430 Petition
`Patent 5,978,951
`specification. Poly-Am., L.P. v. API Indus., Inc., 839 F.3d 1131, 1136 (Fed. Cir.
`
`2016).
`
`The proposed constructions below are the ordinary meaning of the claim term
`
`as they would have been understood by one of ordinary skill in the art at the time of
`
`the invention and thus comply with a district court-type claim construction, as
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`referenced in 37 C.F.R. § 42.100. Any claim terms not included should be
`
`interpreted in the same way.
`
`A.
`
`“code generator,” (claim 1), “coded address,” (claim 1), and
`“encoding” (claim 2)
`The term “code generator” should be interpreted to mean “an algorithm or
`
`hardware block, such as a hash algorithm, which converts one or more input(s) into
`
`a different representation” and “coded address” should be interpreted to mean “a
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`representation created by a code generator based on an address as input.” (Seshan
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`¶58 (EX1007)). Similarly, the term “encoding” should be interpreted to mean
`
`“converting one or more input(s) into a different representation.” (Seshan ¶58
`
`(EX1007)).
`
`The ’951 patent does not use the term “code generator” or “coded address” in
`
`the specification. However, during prosecution, the patentee argued that “at least a
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`portion of the received data unit is coded, such as with a cyclic redundancy code, to
`
`generate a reduced representation of that address.” (Amendment dated 02/09/1999,
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`IPR2017-01430 Petition
`Patent 5,978,951
`at 5 (EX1017)) (emphases added). The portion of the specification identified as
`
`supporting this simply describes the use of a CRC generator; the patentee later
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`describes the claims as relating to a “particular hash algorithm.” (Id. at 6.)
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`Accordingly, a person of ordinary skill in the art, reading the patent in context of the
`
`specification and file history, would have understood the claim term “code
`
`generator” to refer to an algorithm or hardware block, such as a hash algorithm, that
`
`converts one or more input(s) into a different representation. (Seshan ¶59
`
`(EX1007)).
`
`During prosecution, the patentee also stated that claim 1 recites “the coding
`
`of a portion of a received destination address.” (Amendment dated 02/09/1999 at 5
`
`(EX1017)). This is then referred to as a “coded address.” (Id.) A person of ordinary
`
`skill in the art would have thus understood the coded address to be the output of a
`
`code generator when an address is an input for the code generator. (Seshan ¶60
`
`(EX1007)). Accordingly, a person of ordinary skill in the art would have understood
`
`a “coded address” to refer to a representation created by a code generator based on
`
`an input address. (Seshan ¶60 (EX1007)).
`
`VII. SPECIFIC GROUNDS FOR PETITION
`Pursuant to Rule 42.104(b)(4)–(5), the following sections (as confirmed in the
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`Seshan Declaration ¶¶61–225 (EX1007)) detail the grounds of unpatentability, the
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`Patent 5,978,951
`limitations of the challenged claims of the ’951 patent, and how these claims were
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`therefore obvious in view of the prior art.
`
`A. Ground I: Claims 1, 2, and 21 are rendered obvious by Cheriton
`as understood by a person of ordinary skill in the art
`Cheriton is not of record in the ’951 patent.
`
`1. Overview of Cheriton
`Cheriton was filed on December 29, 1995. Cheriton is directed to a network
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`device used to switch network traffic based on network addresses. (Cheriton,
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`Abstract, 1:20-24 (EX1002)). In particular, Cheriton describes a technique for
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`caching network addresses, and hardware to support that technique. (Cheriton, 5:32-
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`38 (EX1002)). As shown in Figure 4 of Cheriton, reproduced below with color
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`added for ease of reference, this hardware includes input and output ports, cache
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`hardware, and switch hardware. Cheriton’s switch hardware includes functions both
`
`for frame header handling and for frame processing and accordingly has been
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`colored both green and yellow.
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`IPR2017-01430 Petition
`Patent 5,978,951
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`
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`Cheriton’s input ports (401-404) are used to receive data packets. (Cheriton,
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`8:32-34, 10:41-42 (EX1002)). After the header has arrived, Cheriton uses the switch
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`hardware to decode the source and destination addresses and generate a virtual path
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`index for use in indexing the cache. (Cheriton, 5:32-34, 10:42-45 (EX1002)). In
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`particular, Cheriton’s cache includes a hash function which hashes the source and
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`IPR2017-01430 Petition
`Patent 5,978,951
`destination address to provide a lookup index for the cache. (Cheriton, 9:34-38,
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`10:42-45 (EX1002)). Cheriton’s cache is “organized as a 4-set associative cache,”
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`identical to the structure of the cache in the ’951 patent. (Cheriton, 9:29-30
`
`(EX1002)). A person of ordinary skill in the art would understand that a 4-set
`
`associative cache (equivalently a 4-way set associative cache) would organize the
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`sets as entries in a row. (See, e.g., U.S. 5,226,147, filed August 9, 1990, at 12:49-54
`
`(EX1019) (“Fujishima”); Seshan ¶62 (EX1007)). The ’951 patent itself also
`
`describes such a cache as a 4-way set associative cache with a depth