DOCKET NO.: 2211726-00145
`Filed on behalf of Unified Patents Inc.
`By: David L. Cavanaugh, Reg. No. 36,476
`Daniel V. Williams, Reg. No. 45,221
`Wilmer Cutler Pickering Hale and Dorr LLP
`1875 Pennsylvania Ave., NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
`Email: Daniel.Williams@wilmerhale.com
`
`
`
`
`Roshan Mansignhani, Reg. No. 62,429
`Jonathan Stroud, Reg. No. 72,518
`Unified Patents Inc.
`1875 Connecticut Ave. NW, Floor 10
`Washington, DC, 20009
`Tel: (202) 805-8931
`Email: Jonathan@unifiedpatents.com
`Email: Roshan@unifiedpatents.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________________________________
`UNIFIED PATENTS INC.
`Petitioner
`v.
`PLECTRUM LLC
`Patent Owner
`IPR2017-01430
`Patent 5,978,951
`DECLARATION OF DR. SRINIVASAN SESHAN
`US PATENT 5,978,951 – CLAIMS 1-6, 8, 11-14, AND 21-24
`
`
`UNIFIED 1007
`
`

`

`TABLE OF CONTENTS
`
`IPR2017-01430
`US Patent 5,978,951
`
`V. 
`
`Page
`I. 
`INTRODUCTION ........................................................................................... 1 
`QUALIFICATIONS ........................................................................................ 3 
`II. 
`III.  TECHNOLOGY BACKGROUND ................................................................. 8 
`IV.  OVERVIEW OF THE ’951 PATENT .......................................................... 14 
`A. 
`Summary of the Alleged Invention ..................................................... 14 
`B. 
`Level of Ordinary Skill in the Art ....................................................... 20 
`C. 
`Prosecution History ............................................................................. 20 
`D. 
`Level of Ordinary Skill in the Art ....................................................... 23 
`E. 
`Understanding of the Law ................................................................... 23 
`CLAIM CONSTRUCTION .......................................................................... 26 
`A. 
`“code generator,” (claim 1), “coded address,” (claim 1), and
`“encoding” (claim 2) ........................................................................... 26 
`VI.  SUMMARY OF OPINIONS ......................................................................... 28 
`A.  Ground I: Claims 1, 2, and 21 are rendered obvious by Cheriton in
`view of ordinary skill in the art ........................................................... 28 
`1. 
`Overview of Cheriton ............................................................... 28 
`2. 
`Claim 1 is obvious in view of Cheriton and ordinary skill ...... 31 
`3. 
`Claim 2 is obvious in view of Cheriton .................................... 44 
`4. 
`Claim 21 is obvious in view of Cheriton .................................. 52 
`Ground II: Claims 3, 5, and 6 are rendered obvious by Cheriton in
`view of Kessler .................................................................................... 61 
`1. 
`Overview of Kessler ................................................................. 61 
`2. 
`Claim 3 is obvious in view of Cheriton and Kessler ................ 62 
`3. 
`Claim 5 is obvious in view of Cheriton and Kessler ................ 64 
`4. 
`Claim 6 is obvious in view of Cheriton and Kessler ................ 66 
`Ground III: Claims 4, 22, 23, and 24 are rendered obvious by Cheriton
`in view of Kessler in view of Jain ....................................................... 67 
`
`B. 
`
`C. 
`
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`

`IPR2017-01430
`US Patent 5,978,951
`1. 
`Overview of Jain ....................................................................... 67 
`Claim 4 is obvious in view of Cheriton, Kessler, and Jain ...... 68 
`2. 
`Claim 22 is obvious in view of Cheriton and Jain ................... 69 
`3. 
`Claim 23 is obvious over Cheriton and Jain ............................ 70 
`4. 
`Claim 24 is obvious over Cheriton, Kessler, and Jain ............. 71 
`5. 
`D.  Ground IV: Claims 8 and 11-14 are rendered obvious by Cheriton in
`view of Jain ......................................................................................... 72 
`1. 
`Claim 8 is obvious in view of Cheriton and Jain ..................... 72 
`2. 
`Claim 11 is obvious in view of Cheriton and Jain ................... 80 
`3. 
`Claim 12 is obvious in view of Cheriton and Jain ................... 81 
`4. 
`Claim 13 is obvious in view of Cheriton and Jain ................... 82 
`5. 
`Claim 14 is obvious in view of Cheriton and Jain ................... 82 
`VII.  AVAILABILITY FOR CROSS-EXAMINATION ...................................... 83 
`VIII.  RIGHT TO SUPPLEMENT .......................................................................... 84 
`IX. 
`JURAT ........................................................................................................... 84 
`
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`IPR2017-01430
`US Patent 5,978,951
`
`I, Srinivasan Seshan, declare as follows:
`I.
`INTRODUCTION
`1.
`I have been retained by Unified Patents Inc. (“Unified” or
`
`“Petitioner”) as an independent expert consultant in this proceeding before the
`
`United States Patent and Trademark Office.
`
`2.
`
`I understand that this proceeding involves US Patent No. 5,978,951 to
`
`Christopher P. Lawler et al. (the “’951 patent”), (attached as EX1001 to Unified’s
`
`petition). I have reviewed the specification, file history and claims of the ’951
`
`patent.
`
`3.
`
`I understand that the application for the ’951 patent was filed on
`
`September 11, 1997. I also understand that the ’951 patent is currently assigned to
`
`Plectrum LLC.
`
`4.
`
`I have been asked to consider whether certain references disclose or
`
`suggest the features recited in the claims of the ’951 patent.
`
`5.
`
`I have also been asked to consider the state of the art and the prior art
`
`available as of September 11, 1997. In particular, I have been asked to consider
`
`the network related aspects in the ’951 patent and compare those to the prior art
`
`available as of September 11, 1997. My opinions are provided below.
`
`6.
`
`I have reviewed and understand US Patent 6,091,725 (“Cheriton”)
`
`(EX1002).
`
`1
`
`

`

`IPR2017-01430
`US Patent 5,978,951
`I have reviewed and understand European Patent Application No.
`
`7.
`
`EP0522743A1 (“Jain”) (EX1003).
`
`8.
`
`I have reviewed and understand Kessler et al., “Inexpensive
`
`Implementations of Set-Associativity”, 17:3 ACM SIGARCH Computer
`
`Architecture News – Special Issue: Proceedings of the 16th annual international
`
`symposium on Computer Architecture 131 (“Kessler”) (EX1004).
`
`9.
`
`I have reviewed every document cited in this declaration.
`
`10.
`
`I have been retained by Petitioner Unified Patents Inc. as an expert in
`
`networks, and more particularly, network switching and routing devices.
`
`11.
`
`I am being compensated at my normal consulting rate for my work.
`
`My compensation is not dependent on and in no way affects the substance of my
`
`statements in this declaration.
`
`12. To the best of my knowledge, I have no financial interest in Petitioner.
`
`Petitioner’s counsel has informed me that Plectrum LLC (“Plectrum”) purports to
`
`own the ’951 patent. To the best of my knowledge, I have no financial interest in
`
`Plectrum, and I have had no contact with Plectrum. To the best of my knowledge,
`
`I similarly have no financial interest in the ’951 patent. To the extent any mutual
`
`funds or other investments I own have a financial interest in the Petitioner, Unified
`
`Patents Inc., or the ’951 patent, I do not knowingly have any financial interest that
`
`would affect or bias my judgment.
`
`2
`
`

`

`IPR2017-01430
`US Patent 5,978,951
`
`II. QUALIFICATIONS
`13.
`I am a Professor in the Computer Science Department at Carnegie
`
`Mellon University (“Carnegie Mellon”) in Pittsburgh, Pennsylvania. I received my
`
`Ph.D. in Computer Science from the University of California – Berkeley in 1995.
`
`My thesis research explored techniques for improving the performance of handoff
`
`in cellular and IP networks.
`
`14.
`
`I joined the Computer Science Department at Carnegie Mellon in
`
`September of 2000. During my time at Carnegie Mellon, I founded the
`
`“Distributed systems, Network protocols, and Applications (DNA)” research
`
`group. From September 2011 to July 2015, I also served as the Associate
`
`Department Head and Ph.D. Program Director for the Computer Science
`
`Department at Carnegie Mellon.
`
`15. From December 1995 to August 2000, I was a Research Staff Member
`
`at IBM T.J. Watson Research.
`
`16.
`
`I am an author of a number of pieces of software, including the
`
`DAEDALUS protocol stack implementing TCP/IP for wireless/mobile hosts, the
`
`SLYFI wireless link layer (similar to 802.11), as well as several other network
`
`routing-related pieces of software.
`
`3
`
`

`

`IPR2017-01430
`US Patent 5,978,951
`I am a Member of the Association for Computing Machinery, the
`
`17.
`
`world’s largest technical society dedicated to computing as a science and
`
`profession.
`
`18.
`
`In addition to my academic qualifications, I have been a practicing
`
`computer scientist for approximately 20 years. Throughout this time period, a
`
`substantial portion of my work in academia and industry has been focused on
`
`problems associated with networking theory and practice as they relate to mobile
`
`communications, wireless networking, and routing in networks. I consider myself
`
`to be thoroughly familiar with technologies in those areas and have published
`
`papers in a wide variety of topics. More specifically, I am familiar with wired and
`
`wireless network architectures, mobility support, including session continuity, and
`
`related programming techniques in those areas.
`
`19.
`
`I have been awarded three U.S. patents:
`
`
`
`D. Schales, S. Seshan and M. Zohar, “Network Data Packet
`
`Classification and Demultiplexing,” U.S. Patent No. 7,200,684 (issued April 13,
`
`2000).
`
`
`
`S. Gollakota, F. Adib, D. Katabi, and S. Seshan. “Cross Technology
`
`Interference Cancellation,” U.S. Patent No. 8,983,011 (issued March 17, 2015).
`
`4
`
`

`

`IPR2017-01430
`US Patent 5,978,951
`A. Anand, A. Akella and S. Seshan. “Network Routing System
`
`
`
`Providing Increased Network Bandwidth,” U.S. Patent No. 9,438,504 (issued
`
`September 6, 2016).
`
`20.
`
`I have supervised numerous Ph.D. and Masters candidates, many of
`
`whom have worked on theses and projects relating to wireless communications and
`
`networking, including:
`
`
`
`Srinivasa Aditya Akella (Thesis: End-Point Based Routing Strategies
`
`for Improving Internet Performance)
`
`
`
`Dongsu Han (Thesis: Supporting Long Term Evolution in an Internet
`
`Architecture)
`
`
`
`Jeffrey Pang (Thesis: Quantifying and Mitigating Privacy Threats in
`
`Wireless Protocols and Services)
`
`21.
`
`I have been the principal or co-investigator on over $16,000,000 in
`
`research grants relating to my work and research, including from companies such
`
`as Intel, IBM, Google, Microsoft, and AT&T, as well as from the National Science
`
`Foundation and the Defense Advanced Research Projects Agency (DARPA).
`
`22.
`
`I am an author on more than 120 journal or workshop papers.
`
`Representative papers include:
`
`
`
`H. Liu, M. K. Mukerjee, C. Li, N. Feltman, G. Papen, S. Savage, S.
`
`Seshan, G. M. Voelker, D. G. Andersen, M. Kaminsky, G. Porter,
`
`5
`
`

`

`IPR2017-01430
`US Patent 5,978,951
`and A. Snoeren. Scheduling Techniques for Hybrid Circuit/Packet
`
`Networks. Proceedings of ACM CoNext 2015, December 2015,
`
`Heidelberg, Germany
`
`
`
`D. Han, A. Anand, F. Dogar, B. Li, H. Lim, M. Machado, A.
`
`Mukundan, W. Wu, A. Akella, D. Andersen, J. Byers, S. Seshan, and
`
`P. Steenkiste. XIA: Efficient Support for Evolvable Internetworking.
`
`Proceedings of the USENIX Symposium on Networked Systems
`
`Design and Implementation (NSDI '12), San Jose, CA, April 2012.
`
`
`
`A. Anand, A. Gupta, A. Akella, S. Seshan, and S. Shenker. Packet
`
`Caches on Routers: The Implications of Universal Redundant Traffic
`
`Elimination. Proceedings of the SIGCOMM Symposium on
`
`Communications Architectures and Protocols, Seattle, WA, Aug
`
`2008.
`
`
`
`M. Agrawal, S. Bailey, A. Greenberg, J. Pastor, P. Sebos, S. Seshan,
`
`J. Van der Merwe, J. Yates. “RouterFarm: Towards a Dynamic,
`
`Manageable Network Edge,” Proceedings of ACM Sigcomm
`
`Workshop on Internet Network Management, Pisa Italy, September
`
`2006.
`
`
`
`A.Akella, J. Pang, A. Shaikh, B. Maggs and S. Seshan. “A
`
`Comparison of Overlay Routing and Multihoming Route Control,”
`
`6
`
`

`

`IPR2017-01430
`US Patent 5,978,951
`Proceedings of the ACM SIGCOMM Conference, Portland, OR,
`
`August 2004.
`
`
`
`H. Balakrishnan, H. Rahul and S. Seshan. “An Integrated Congestion
`
`Management Architecture for Internet Hosts,” Proceedings of the
`
`ACM SIGCOMM Conference, Cambridge, MA, September 1999.
`
`
`
`H. Balakrishnan, V. Padmanabhan, S. Seshan, M. Stemm and R. Katz.
`
`“TCP Behavior of a Busy Internet Server: Analysis and
`
`Improvements,” Proceedings of the IEEE INFOCOM Conference,
`
`San Francisco, CA, March 1998.
`
`23.
`
`I was awarded Best Paper at ACM CoNext 2013, ACM MobiSys (the
`
`International Conference on Mobile Systems, Applications, and Services) 2008,
`
`and BaseNets. I was also awarded Best Student Paper at ACM MOBICOM 2000
`
`and ACM MOBICOM 1995. ACM CoNext, ACM MobiSys and ACM
`
`MOBICOM are the among ACM’s top venues for research regarding general
`
`networking, wireless networking and mobile computing.
`
`24.
`
`I was an Associate Editor of the ACM/IEEE Transactions on
`
`Networking technical journal from 2003-2005. I have also been selected as chair
`
`of the 2014 Technical Steering Committee for ACM Sigcomm, have co-chaired the
`
`ACM Sigcomm Program Committee, and have served as a member of the Program
`
`7
`
`

`

`IPR2017-01430
`US Patent 5,978,951
`Committee for ACM MobiSys, ACM Sigcomm, and ACM Mobicom on a number
`
`of occasions. I have been asked to serve on NSF review panels ten times.
`
`25. Additional detailed information regarding my background,
`
`experience, and professional qualifications may be found in the attached
`
`Curriculum Vitae.
`
`III. TECHNOLOGY BACKGROUND
`26. When the ’951 patent was filed, data communication networks were
`
`well known for years. (See, e.g., US5,566,170, filed Dec. 29, 1994, at 1:23-27
`
`(EX1008)) (“Bakke”). In such a network, one component is a switch which directs
`
`data units, such as data packets, from one network node to another. (See, e.g.,
`
`Bakke at 1:31-33 (EX1008)). Such a device concentrates data packets from
`
`network devices received over a communication network, which then directs the
`
`packets over a network output to either the desired destination device or to another
`
`forwarding device (e.g., another switch or router). (See, e.g., Bakke at 2:11-20
`
`(EX1008)).
`
`27. Various such devices existed, with different internal designs.
`
`However, every design generally incorporated the same functional components.
`
`(See Newman et al., “IP Switching and Gigabit Routers”, IEEE Comm. Magazine
`
`64 (Jan. 1997) (EX1009) (“IP Switching”)). Line cards were used to connect the
`
`physical network data link into a switch fabric (e.g., a crossbar switch). (IP
`
`8
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`

`

`IPR2017-01430
`US Patent 5,978,951
`Switching at 64 (EX1009)). The switch fabric interconnected the various
`
`components of the device. (Id.) A forwarding engine would inspect packet
`
`headers, determine which outgoing line card should receive the packet, and rewrite
`
`the header as needed. (Id.) A network processor handles routing, including
`
`generating routing tables (also called forwarding information bases) for the
`
`forwarding engine, and handles general network management. (Id.) These known
`
`functional blocks could be in various physical arrangements. For example, it was
`
`known that the forwarding engine could be combined with the network processor.
`
`(IP Switching at 64 (EX1009)). The figure below illustrates one potential system
`
`along these lines:
`
`28. As network rates increased, the packet forwarding rate needed
`
`likewise increased. (IP Switching at 64 (EX1009)). IP Switching summarizes two
`
`known approaches for a forwarding engine. (Id. at 64-65). One known approach
`
`
`
`9
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`

`

`IPR2017-01430
`US Patent 5,978,951
`employed an application specific integrated circuit (ASIC) designed for
`
`forwarding, while the other known approach employed a general purpose processor
`
`combined with destination address caching in an on-chip cache. (Id. at 64-65). In
`
`either approach, the core functionality is looking up the correct next destination to
`
`route or switch to, including the correct outbound interface (i.e., the right port in
`
`the right line card) based on the destination address of a packet. (Id. at 65.). The
`
`figure below shows the path a packet could take in such a transaction.
`
`
`
`29. First, the packet is sent from the network device and received at an
`
`input on a line card in the switching device. The line card passes the packet to the
`
`switch fabric. The switch fabric passes the packet to the forwarding engine. The
`
`forwarding engine determines the appropriate line card and output to send the
`
`packet to and transmits the output destination to the switch fabric. The switch
`
`10
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`

`IPR2017-01430
`US Patent 5,978,951
`fabric then passes the packet to the appropriate line card, which transmits it to the
`
`appropriate recipient network device.
`
`30. A cache is a high-speed memory used to provide quick access to
`
`frequently used data. It was well known to perform the outbound interface lookup
`
`described in IP Switching by hashing the destination address and using the hashed
`
`value as the lookup key for a cache. For example, the Brady patent describes a
`
`system in which a search key is used as the lookup. (US 5,914,938, filed
`
`November 19, 1996, at Abstract (EX1010)) (“Brady”). First, the search key is
`
`hashed to generate an identifier. (Id. at 2:62-64). The identifier is used to index
`
`into a storage containing one or more stored entries. (Id. at 2:64-3:1). Then, each
`
`stored entry is compared to the original search key in order to determine if the
`
`entry matches the search key (i.e., is the correct entry). (Id. at 2:66-3:1). This
`
`general process of using a hash function to search a cache or memory could be
`
`applied using many different search keys. One option would be a destination
`
`address. (See, e.g., Brady at 3:3-5 (EX1010)); (see also US 5,917,821, filed Dec.
`
`21, 1994, at 3:14-19, FIG. 5 (EX1011)).
`
`31. Thus, network switching devices that could receive packets, process
`
`packet headers, lookup appropriate output ports in a cache using the destination
`
`address, and forward the received packet appropriately were well known at the
`
`time of the invention of the ’951 patent.
`
`11
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`

`IPR2017-01430
`US Patent 5,978,951
`32. Specific cache hardware was also well known at the time of the
`
`invention of the ’951 patent. A cache is a “relatively small, random access
`
`memory (RAM) used to store a copy of memory data in anticipation of future use.”
`
`(US 5,509,135, filed Sept. 25, 1992, at 1:20-22 (EX1012)) (“Steely”). Various
`
`types of caches, such as direct-mapped and set-associative caches, were well
`
`known. (Id. at 1:65-25). In a set-associative cache, multiple RAMs are
`
`concurrently addressed to provide multiple entries for a single cache index. (Id. at
`
`2:16-19). For example, FIG. 3 of Steely, reproduced below, shows four data
`
`RAMs 31-34. (Steely at FIG. 3, 4:38-40 (EX1012)).
`
`33. The number of RAMs is the number of “ways” in the cache; for
`
`example, a cache using four RAMs is a “four-way set-associative cache.” (Id. at
`
`
`
`12
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`

`IPR2017-01430
`US Patent 5,978,951
`2:19-25). A conventional cache address used a “tag” and a “cache index”; the
`
`index corresponds to the cache memory address storing the cached data, and the
`
`tag is used to “uniquely identify blocks having different memory addresses but the
`
`same cache index.” (Id. at 1:48-64). A portion of FIG. 3 of Steely has been
`
`annotated and reproduced below to illustrate one such set of blocks with the same
`
`cache index. While sharing a cache index, the blocks may refer to different
`
`memory addresses (e.g., if the memory addresses hash to the same value and thus
`
`the same cache index.)
`
`
`
`34.
`
`In operation, a set-associative cache works as follows. A cache access
`
`causes each of the RAMs in the set to be examined at the corresponding cache
`
`index location. The tag in the cache access request is compared to the tag in the
`
`stored cache blocks in order to distinguish between cache blocks with the same
`
`cache index but different addresses. (Steely at 2:26-34 (EX1012)). It was also
`
`known to use a type of memory called “content-addressable memory” in which the
`
`13
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`

`

`IPR2017-01430
`US Patent 5,978,951
`access identifier is the desired information, rather than the data stored at a memory
`
`address. (US 4,377,855, filed Nov. 6, 1980, at 1:17-21 (EX1013)) (“Lavi”). In a
`
`cache with a content-addressable memory, rather than providing a memory
`
`address, the desired search key is provided to the memory. In other words, instead
`
`of requesting that the cache return the value associated with memory location
`
`0x00FF, in a content-addressable memory you request that the cache return the
`
`value associated with a search key (e.g., data associated with a destination address
`
`in a network.) The Brady patent, described above, is thus a logical description of a
`
`set-associative content-addressable network address cache.
`
`35.
`
`It was thus well-known in the art both to lookup addresses from
`
`packets in a cache to determine an output port, and to use a content-addressable
`
`cache memory (e.g., a 4-way set associative cache using content-addressable
`
`memory) as the lookup mechanism.
`
`IV. OVERVIEW OF THE ’951 PATENT
`A.
`Summary of the Alleged Invention
`36. The ’951 patent is generally directed to providing a hardware network
`
`address cache. (’951 patent at 1:23-31 (EX1001)). The address cache is
`
`responsible for maintaining address and age tables, searching the address table for
`
`addresses received in network frames, and returning address search results (such as
`
`the destination port(s) for the received frame). (’951 patent at 1:30-39 (EX1001)).
`
`14
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`

`IPR2017-01430
`US Patent 5,978,951
`Using this system, a frame is received, the addresses in the frame are looked up in
`
`the cache, and data associated with cached addresses (if any) is returned for use in
`
`processing the frame. (’951 patent at 1:41-52 (EX1001)).
`
`37. The ’951 patent admits that it was known to use software to parse
`
`frames to determine addresses, to lookup data for those addresses, and to process
`
`frames according to the associated data. (’951 patent at 1:15-17 (EX1001)). The
`
`alleged invention of the ’951 patent is a particular hardware approach to
`
`performing these functions to supposedly provide better performance by using a
`
`coded address in cache lookup. (’951 patent at 1:23-27; 2:20-22; 2:43-46
`
`(EX1001)). This approach is described below.
`
`38. A given network device according to the ’951 patent incorporates one
`
`or more network interfaces connected to a motherboard via a backplane. (’951
`
`patent at 3:26-30 (EX1001)). FIG. 1 of the ’951 patent illustrates this general
`
`structure.
`
`15
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`IPR2017-01430
`US Patent 5,978,951
`
`
`
`39. The motherboard incorporates an address cache ASIC with an
`
`associated cache, a frame processor, an application processor, and a master buffer.
`
`(’951 patent at 3:25-30; 3:57-60 (EX1001)). FIG. 2 of the ’951 patent illustrates
`
`the motherboard and network interface modules in more detail. Color coding has
`
`been added to the figure to illustrate key components.
`
`16
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`IPR2017-01430
`US Patent 5,978,951
`
`
`
`40. Each network interface module has one or more input ports 18 for
`
`receiving data, and one or more output ports 20 for sending data. (’951 patent at
`
`3:31-35 (EX1001)). When a frame is received via the input port(s) 18, the frame is
`
`passed to the receive header processor 46, which derives information from the
`
`header and passes that information to the address cache ASIC (ACA) 26. (’951
`
`patent at 7:53-59 (EX1001)).
`
`41. The ACA 26 has an associated cache 28. (’951 patent at 3:57-58
`
`(EX1001)). Lookup of the addresses cached in associated cache 28 is the primary
`
`function of the ACA 26. (’951 patent at 4:20-21 (EX1001)). When the receive
`
`header processor 46 passes source and destination addresses to the ACA 26, the
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`ACA 26 uses those addresses to perform lookups. (’951 patent at 3:61-64
`
`(EX1001)). In particular, after receiving one or more addresses, the ACA 26
`
`searches the cache 28 for each received address and provides a response to the
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`network interface module it received the packet from, which may include whether
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`the address(es) were found in the cache 28, and any data associated with the
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`cached address. (’951 patent at 4:20-33 (EX1001)). The ACA 26 and cache 28, as
`
`well as the lookup process, are described in more detail below. After lookup,
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`either the frame is transmitted out of all output ports if the lookup failed, or the
`
`frame is forwarded to the appropriate output port(s) if the address is known. (’951
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`patent at 4:60-5:1 (EX1001)).
`
`42.
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`In one embodiment, the cache 28 is a 4-way set associative cache.
`
`(’951 patent at 5:14-15 (EX1001)). Each row of the cache is thus associated with
`
`one entry from each of the 4 sets. (’951 patent at 5:16-17 (EX1001)). FIG. 4A
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`illustrates this arrangement of the cache 28.
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`
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`43.
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`In order to locate data in the cache, a four step process is performed.
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`First, the received address is coded to generate a coded address to use as a row
`
`identifier. In one embodiment, this coding is done by performing a Cyclic
`
`Redundancy Code process. (’951 patent at 5:25-30 (EX1001)). Second, the coded
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`address is used to identify a cache row. (’951 patent at 5:29-30 (EX1001)). Third,
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`a set within the row is chosen for examination, and the stored address is compared
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`to the received address (i.e., the address prior to coding). (’951 patent at 5:30-37
`
`(EX1001)). Optionally, the cache can check which sets contain valid data and
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`which sets have been used more or less recently in order to determine which sets to
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`use for comparison. (’951 patent at 5:30-34 (EX1001)). Finally, if a set has a
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`matching address, the associated data is returned. (’951 patent at 5:37-39
`
`(EX1001)). If the set does not have a matching address, the next set is compared,
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`until all valid sets have been compared; if all sets are compared without a match,
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`then an indication that no match was found is returned. (’951 patent at 5:39-44
`
`(EX1001)).
`
`44. Using the data or indication from the cache, the frame is forwarded
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`appropriately. (’951 patent at 4:60-5:1 (EX1001)).
`
`B.
`Level of Ordinary Skill in the Art
`45. A person of ordinary skill in the art for the ’951 patent would have
`
`been an electrical engineer or computer engineer having a bachelor’s degree and
`
`two years of experience in designing network switching/routing hardware, or
`
`equivalent post-graduate education, such as a master’s degree focused in
`
`networking systems.
`
`C.
`Prosecution History
`46. The ’951 patent issued from US Patent Application Number
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`08/927,336, which was filed on September 11, 1997 (File History, Application
`
`(12/11/97) (EX1014)). The original application included one claim. A
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`Preliminary Amendment was filed on March 10, 1998 that added claims 2-26.
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`(File History, Preliminary Amendment (03/10/98) (EX1015)). A non-final Office
`
`Action was mailed on November 9, 1998 that rejected claims 1-7 and allowed
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`claims 8-26. (File History, Office Action (11/09/98) (EX1016)). The Examiner
`
`did not indicate why he believed claims 8-26 were allowable.
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`47. Applicant filed an Amendment on February 9, 1999 that amended
`
`claim 1 to change “CRC code” to “coded address.” (File History, Amendment at
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`2-3 (02/09/99) (EX1017)). In support of the amendment, Patent Owner asserted
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`the following:
`
`Claim 1 has been amended in order to delete references to ‘CRC
`
`code’ in order to remove any unintended suggestion that the
`
`encoding step was being utilized to ensure data validity after
`
`transmission, as for which cyclic redundancy checks are often
`
`used. Rather, in the present case, at least a portion of the
`
`received data unit is coded, such as with a cyclic redundancy
`
`code, to generate a reduced representation of that address.
`
`(Id. at 5 (EX1017)).
`
`48. Attempting to distinguish claim 1 from the prior art, Applicant argued
`
`the following:
`
`Present claims 1 and 2 recite the coding of a portion of a
`
`received, destination address. This coded address is then used
`
`to index rows of a cache. Once a desired row has been identified
`
`based upon this indexing, one of plural entries is identified and
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`a portion of the originally received destination address is
`
`compared against a cached address value associated with the
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`US Patent 5,978,951
`identified entry. If a favorable comparison occurs, the entry
`
`contents are retrieved as an indication of how the received data
`
`is to be forwarded.
`
`(Id. (EX1017)).
`
`Rosteker, in contrast, fails to teach or suggest the arrangement
`
`of cached data in rows comprising plural entries. Rather,
`
`Rosteker teaches the identification of individual rows based
`
`upon a hash of the received address, then the comparison of the
`
`contents of that row to the address of the incoming message
`
`(col. 20, lines 20-37). The CRC check recited in Rosteker
`
`appears to relate to a continuity check for received data packets
`
`(col. 34, lines 28-39; col. 35, lines 8-11), not to a particular hash
`
`algorithm enabling efficient comparisons against cache row
`
`labels, as claimed.
`
` (Id. at 6 (EX1015)).
`
`49. A Notice of Allowability was then mailed on March 15, 1999
`
`allowing all claims 1-26. (File History, NOA (03/15/99) (EX1018). The Examiner
`
`did not provide a reasons for allowance. As described in detail below, the
`
`limitations argued as being absent from the prior art are found in the currently cited
`
`references.
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`D. Level of Ordinary Skill in the Art
`50. A person of ordinary skill in the art for the ’951 patent would have
`
`been an electrical engineer or computer engineer having a bachelor’s degree and
`
`two years of experience in designing network switching/routing hardware, or
`
`equivalent post-graduate education, such as a master’s degree focused in
`
`networking systems.
`
`E. Understanding of the Law
`51.
`I am not an attorney. For the purposes of this declaration, Petitioner’s
`
`counsel has informed me about certain aspects of the law that are relevant to my
`
`opinions.
`
`52. Petitioner’s counsel have informed me that a patent claim may be
`
`“anticipated” if each element of that claim is present either explicitly or inherently
`
`in a single prior art reference. Petitioner’s counsel have informed me that to be
`
`inherently present, the prior art reference must necessarily disclose the limitation,
`
`and the fact that the reference might possibly practice or contain a claimed
`
`limitation is insufficient to establish that the reference inherently teaches the
`
`limitation.
`
`53. Petitioner’s counsel have informed me that a patent claim can be
`
`considered to have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed. This means that, even if all of the requirements of a
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`claim are not found in a single prior art reference, the claim is not patentable if the
`
`differences between the subject matter in the prior art and the subject matter in the
`
`claim would have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed.
`
`54. Petitioner’s counsel have informed me that a determination of whether
`
`a claim would have been obvious should be based upon several factors, including,
`
`among others:
`
` the level of ordinary skill in the art at the time the application was filed;
`
` the scope and content of the prior art;
`
` what differences, if any, existed between the claimed invention and the
`
`prior art.
`
`55. Petitioner’s counsel have informed me that a single reference can
`
`render a patent claim obvious if any differences between that reference and