throbber
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`Greaves, Paul
`In re Patent of:
`5,978,876 Attorney Docket No.: 12189-0052IP1
`U.S. Patent No.:
`November 2, 1999
`
`Issue Date:
`Appl. Serial No.: 08/834,242
`
`Filing Date:
`April 14, 1997
`
`Title:
`SYSTEM AND METHOD FOR CONTROLLING
`COMMUNICATIONS BETWEEN SUBSYSTEMS
`
`
`
`
`
`
`I.
`
`DECLARATION OF M. RAY MERCER
`
`Personal Work Experience and Awards
`1. My name is Melvin Ray Mercer, Professor Emeritus of Electrical and
`
`Computer Engineering at Texas A&M University. I am currently President of M.
`
`Ray Mercer and Associates, Inc., an independent consulting firm. In addition to the
`
`below summary, a copy of my current curriculum vitae more fully setting forth my
`
`experiences and qualifications is submitted herewith as Appendix A.
`
`2.
`
`I have more than 46 years of dual industrial and academic experience
`
`in Electrical Engineering and Computer Engineering. I received a B.S. in Electrical
`
`Engineering from Texas Tech University in 1968, a Master of Science in Electrical
`
`Engineering from Stanford University in 1971, and a Doctor of Philosophy in
`
`Electrical Engineering from The University of Texas at Austin in 1980. Further, I
`
`have authored dozens of published technical papers and delivered many lectures
`
`addressing various aspects of Electrical and Computer Engineering.
`
`
`
`1
`
`TI 1003
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`

`

`3.
`
`From 1968 to 1973, I was a Research/Development Engineer at
`
`General Telephone and Electronics Sylvania in Mountain View, California, during
`
`which time I also completed my M.S. in Electrical Engineering from Stanford
`
`University in 1971. During this period, I programmed minicomputer systems
`
`(predecessors to personal computers, smartphones, and modem servers) in machine
`
`language, assembly language, and various higher-level languages. I wrote simple
`
`Operating Systems, and most of the applications involved real-time processing as a
`
`significant aspect of the systems design. Much of this work was related to
`
`computer control of data collection and analysis systems used by organizations in
`
`the United States government.
`
`4.
`
`From 1973 to 1977, I was a Member of Technical Staff at Hewlett-
`
`Packard's Santa Clara Division and subsequently at Hewlett-Packard Laboratories
`
`in Palo Alto, California. During this time, I continued to develop application
`
`programs. I also designed interface hardware to interact with the software of the
`
`computers and accomplish various tasks. One major project for which I had overall
`
`responsibility was the real-time control of environmental test systems for satellites
`
`and satellite components. At HP Laboratories, among other projects, I developed
`
`hardware and software to provide real-time control of manufacturing systems for
`
`exotic solid state devices.
`
`
`
`2
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`

`

`5.
`
`From 1977 to 1980, I was a Lecturer in the Division of Mathematics,
`
`Statistics, and Computer Science at the University of Texas at San Antonio. As the
`
`director of a laboratory for teaching students to program and build hardware
`
`interfaces and control systems using small computers, I purchased, built, and
`
`operated some of the earliest personal computers. Additionally, I taught courses in
`
`the design of digital systems, while also completing my Ph.D. in Electrical
`
`Engineering from the University of Texas at Austin in 1980.
`
`6.
`
`From 1980 to 1983, I was a Member of Technical Staff at Bell
`
`Laboratories in Murray Hill, New Jersey. My work involved the programming of
`
`computers and the hardware design of components for communication systems. I
`
`was part of a three-person team that designed, tested, and directed the manufacture
`
`of an integrated circuit that was a key component in a digital telephone modem.
`
`7.
`
`In 1983, I was appointed Assistant Professor of Electrical and
`
`Computer Engineering at the University of Texas at Austin. In 1987, I was
`
`promoted to Associate Professor and Professor in 1991. During this period, I
`
`taught Computer Engineering courses at the undergraduate and graduate level,
`
`directed the research of graduate students, and consulted with numerous
`
`organizations.
`
`8.
`
`In 1995, I was appointed Professor of Electrical and Computer
`
`Engineering, Leader of the Computer Engineering Group, and Holder of the
`
`
`
`3
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`

`

`Computer Engineering Chair in Electrical Engineering at Texas A&M University
`
`in College Station, Texas. My teaching, my research, my technical publications,
`
`and my supervision of graduate students during this period included the areas of
`
`the modeling, design, and fabrication of digital hardware and software systems.
`
`My administrative duties included the development and enhancement of the
`
`Computer Engineering Group. As with previous work (at The University of Texas
`
`at Austin), during this period, I taught courses at the undergraduate and graduate
`
`level, I directed the research of graduate students, and I consulted with numerous
`
`organizations on a variety of topics. I was also responsible for monitoring
`
`controlled experiments to optimize and quantify the use of tester time to detect
`
`defects in electrical products, and I was part of a team that used analytical
`
`techniques to predict the expected growth of quiescent currents in MOS transistors
`
`as a function of the reduction in integrated circuit feature sizes.
`
`9.
`
`In September 2005, I retired from my teaching position, and the
`
`Regents of the Texas A&M University System appointed me as “Professor
`
`Emeritus of Electrical and Computer Engineering at Texas A&M University.”
`
`10.
`
`In 1984, I formed M. Ray Mercer and Associates, an independent
`
`consulting firm that I have owned and directed to this day. Since 1984, I have been
`
`providing private consultation and advice in Electrical and Computer Engineering
`
`
`
`4
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`to numerous entities, including IBM Corp., Rockwell International, Motorola
`
`Semiconductor, AT&T, Inc., and SigmaTel.
`
`11.
`
`I first served as an expert witness at the request of the Office of the
`
`State Attorney General of Texas in 1984. Since that time, I have been hired by
`
`numerous law firms to provide them and their clients with expert consultation and
`
`expert testimony, often in the areas of patent infringement litigation related to
`
`Electrical and Computer Engineering. I have testified about systems that
`
`download entertainment media from the internet for presentation on home-based
`
`entertainment systems. I have testified regarding stand alone and on line gaming
`
`systems. I have testified regarding home entertainment systems which use wireless
`
`communications. I have testified regarding media advertising for automotive
`
`products. I have testified with respect to on-line educational institutions and
`
`technical aspects of their media distribution systems. I have testified with respect
`
`to media and entertainment systems for mobile vehicles. I have testified in a case
`
`involving the simultaneous acquisition of media from an external source to a
`
`storage device and presentation of different media stored on that same storage
`
`device via an entertainment device. I have testified in a case involving delta-sigma
`
`modulation for high performance analog-to-digital and digital-to-analog converters
`
`– such as those commonly utilized in personal computers.
`
`
`
`5
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`

`

`12. Throughout my career, I have been actively involved in numerous
`
`professional organizations including the Institute of Electrical and Electronics
`
`Engineers ("IEEE"), and I was recognized as an IEEE Fellow in 1994. I was the
`
`Program Chairman for the 1989 International Test Conference, which is an IEEE
`
`sponsored annual conference with (at that time) more than one thousand attendees
`
`and over one hundred presented papers. I won the Best Paper Award at the 1982
`
`International Test Conference.
`
`13.
`
`I also won a Best Paper Award at the 1991 Design Automation
`
`Conference, an annual conference with (at that time) more than ten thousand
`
`attendees and five hundred submitted papers, many of which related to the design
`
`of integrated circuit-based systems.
`
`14.
`
`I also won a Best Paper Award at the 1999 VLSI Test Symposium.
`
`This paper was focused on manufacturing techniques to optimize the quality of
`
`manufactured digital systems. I am the inventor of two United States patents that
`
`relate to the design of integrated circuits and digital systems. I was selected as a
`
`National Science Foundation Presidential Young Investigator in 1986. This award
`
`included $500,000 for support of my research.
`
`15. Based on my above-described 46 years of dual industrial and
`
`academic experience in Electrical Engineering and Computer Engineering, and the
`
`acceptance of my publications and professional recognition by societies in my
`
`
`
`6
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`field, I believe that I am an expert in the field of communications between
`
`subsystems and subsystem communication control systems including prioritizing
`
`and controlling data transfers across a bus.
`
`
`
`II. Materials Considered
`
`16.
`
`In writing this Declaration, I have considered the following: my own
`
`knowledge and experience, including my work experience in the fields of digital
`
`communications and control; my industry experience with those subjects; and my
`
`experience in working with others involved in those fields. I have also analyzed
`
`the following publications and materials, in addition to other materials I cite in my
`
`declaration:
`
`
`
`
`
`
`
`
`
`
`
`U.S. Patent No. 5,978,876 and its accompanying Prosecution History
`
`(“the ’876 Patent” and “the ’876 PH”)
`
`U.S. Patent No. 5,905,879 (“Lambrecht”)
`
`U.S. Patent No. 5,707,286 (“Carlson”)
`
`U.S. Patent No. 5,987,590 (“Wing So”)
`
`U.S. Patent No. 5,333,299 (“Koval et al.”)
`
`17. Although for the sake of brevity this Declaration refers to selected
`
`portions of the cited references, it should be understood that one of ordinary skill in
`
`the art would view the references cited herein in their entirety and in combination
`
`
`
`7
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`

`with other references cited herein or cited within the references themselves. The
`
`references used in this Declaration, therefore, should be viewed as being
`
`incorporated herein in their entirety.
`
`18.
`
`I am not currently and have not at any time in the past been an
`
`employee of Texas Instruments, Inc. I have been engaged in the present matter to
`
`provide my independent analysis of the issues raised in the petition for inter partes
`
`review of the ’876 patent. I received no compensation for this declaration beyond
`
`my normal hourly compensation based on my time actually spent studying the
`
`matter, and my compensation does not depend on the outcome of this inter partes
`
`review of the ’876 patent.
`
`
`
`III. Person of Ordinary Skill in the Art (POSITA)
`19.
`I am familiar with the content of the ’876 patent, which, I have been
`
`informed by counsel, has an earliest possible filing date of April 14, 1997 (the
`
`“Critical Date”). Additionally, I have reviewed the other references cited above in
`
`this declaration. Counsel has informed me that I should consider these materials
`
`through the lens of one of ordinary skill in the art related to the ’876 patent at the
`
`critical date of the patent, and I have.
`
`20. Thus, when I discuss what a POSITA would have known or
`
`understood, I am explaining the POSITA’s knowledge and understanding as of the
`
`
`
`8
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`

`Critical Date. I believe that a person having ordinary skill in the art at the effective
`
`filing date of the ’876 Patent (“POSITA”) would have had at least a Bachelor of
`
`Science Degree in Electrical Engineering, Computer Engineering, or Computer
`
`Science with at least two years of work experience related to computer logic design
`
`and operation including prioritizing controlling data transfers across a bus.
`
`Individuals with additional education or additional industrial experience could still
`
`be of ordinary skill in the art if that additional aspect compensates for a deficit in
`
`one of the other aspects of the requirements stated above. I base my evaluation of
`
`a person of ordinary skill in this art on my own personal experience, including my
`
`knowledge of students, colleagues, and related professionals at the time of interest.
`
`
`
`IV. Claim Construction
`
`21. The challenged claims and proposed claim term constructions are
`
`submitted herewith as Appendix B.
`
`22.
`
`I have been informed by counsel of the following fact. Because the
`
`’876 patent has expired on April 14, 2017, the claims therein are interpreted under
`
`principle set forth by the court in Phillips v. AWH Corp., 415 F.3d 1303, 1312,
`
`1327 (Fed. Cir. 2005). As a starting point, “words of a claim are generally given
`
`their ordinary and customary meaning as understood by a person of ordinary skill
`
`in the art in question at the time of the invention, construing to preserve validity in
`
`
`
`9
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`

`case of ambiguity.” Id. But in cases where the inventors are “acting as his or her
`
`own lexicographer,” “the specification may reveal a special definition given to a
`
`claim term by the patentee that differs from the meaning it would otherwise
`
`possess.” Id., 1314-16, 1319. “In such cases, the inventor’s lexicography
`
`governs.” Id.
`
`23. For the purposes of my analysis in this matter, I have adopted the
`
`“ordinary and customary meanings” of the terms in the claims of the ‘876 Patent
`
`unless certain terms are explicitly defined in the ’876 patent. In particular, counsel
`
`asked me the to interpret the term “channel” for independent claims 2 and 15, as
`
`well as their dependent claims to mean “a time-based transfer window” of a
`
`physical medium for transmitting data because the inventor of the ’876 patent
`
`acted as his own lexicographer while applying this term. See, e.g., the ’876 patent
`
`at 2:66-67, 3:30-33, 3:46-47, 5:46-48.
`
`24. Counsel also asked me to assume that the Patent Owner may assert a
`
`broader construction for the term “channel” in litigation related to the issues of
`
`this IPR. Therefore, I have provided additional analysis (in paragraph 85 and in
`
`Section VII, below) assuming that the term “channel” has its plain and ordinary
`
`meaning.
`
`25.
`
`I also note that in all challenged claims, the term “channel” refers
`
`exclusively to a “communication channel” and not to a “control channel.”
`
`
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`10
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`

`26. Counsel also asked me
`
`to
`
`interpret
`
`the
`
`terms “commence
`
`communication” and “exchanging said communications” in claims 2 and 15 to
`
`mean “directly exchange or directly exchanging data on the assigned channel
`
`without passing through a central controller” because of the arguments adopted
`
`by the Patentee during the prosecution of the ’876 patent. I have followed these
`
`principles in my analysis. In a few instances, I have discussed my understanding of
`
`the claims in the relevant paragraphs below.
`
`
`V. Threshold Issues
`A.
`Implementing control logic, such as the arbitration logic 504,
`using a processor was well known at the Critical Date of the ’876
`Patent
`27. Below, I discuss an aspect of Lambrecht’s FIG. 7 system referred to
`
`as the arbitration logic 504. The arbitration logic 504 is responsible for receiving
`
`communication “requests signals” from the multimedia devices 142A-146A, and in
`
`response, the arbitration logic 504 “grants bus access according to a desired
`
`arbitration method.” Lambrecht at 14:5-12. The control information used by the
`
`arbitration logic 504 includes arbitration information “in determining who should
`
`receive control of the multimedia bus 130.” Id. at 15:25-28.
`
`28. As a well-recognized term in the art, control logic, such as arbitration
`
`logic 504, typically includes software stored in a Random Access Memory
`
`(“RAM”). For example, the prior art reference Carlson shows that it was common
`
`
`
`11
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`

`knowledge before the Critical Date, that control logic could be “a hardware or
`
`software programmable microprocessor” or an Application Specific Integrated
`
`Circuit (ASIC). See, e.g., Carlson, 4:43-55.
`
`29. A POSITA would have understood the arbitration logic 504, as not
`
`just an intangible process, but rather is a tangible thing that implements the
`
`functions attributed to arbitration logic 504 by Lambrecht. In reference to this
`
`understanding, the arbitration logic 504 (or simply “logic 504”) as used in this
`
`document refers to the software and hardware components implementing the
`
`functions attributable to logic 504.
`
`30. While Lambrecht discusses the functions of arbitration logic 504 in
`
`detail, Lambrecht does not go
`
`into detail
`
`in describing
`
`the hardware
`
`implementation of arbitration logic 504 as a standalone component shown in FIG.
`
`7. That being said, a POSITA would have known that arbitration logic 504 would
`
`be implemented in tangible hardware, and that such hardware can fall into only a
`
`few categories. See, e.g., Carlson at 4:43-55 (Thus, it was well known in the art
`
`that a “control circuit,” such as the logic 504, could be implemented with “a
`
`hardware or software programmable microprocessor” or “[a]lternatively” as “an
`
`ASIC device.”).
`
`31.
`
`In one category, the arbitration logic 504 might be implemented by
`
`dedicated hardware, such as an application specific integrated circuit (ASIC),
`
`
`
`12
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`which would be a piece of dedicated hardware specifically designed to meet the
`
`functional requirements of arbitration logic 504. (ASICs are not economically
`
`reasonable for most low volume products since the initial design costs are large,
`
`and this causes the price of each individual ASIC to be unreasonably expensive.)
`
`32.
`
`In another category, arbitration logic 504 can be implemented by a
`
`programmable processor, such as a general purpose microprocessor, programed to
`
`perform all of the functions of arbitration logic 504. In my opinion, the Lambrecht
`
`reference to arbitration logic 504 would teach or suggest to a POSITA a
`
`programmable microprocessor having the processing power for performing the
`
`functions as described for arbitration logic 504.
`
`33. Finally,
`
`in a
`
`third category, arbitration
`
`logic 504 might be
`
`implemented by a combination of dedicated hardware and a programmable
`
`processor where some of the logic 504 is implemented by the dedicated hardware
`
`and some of the logic 504 is implemented by the processor.
`
`34. Because there are only a limited number of ways to implement the
`
`hardware components of the arbitration logic 504, a POSITA as of the Critical
`
`Date would consider the above described categories of hardware based upon
`
`Lambrecht’s disclosure. Moreover, a POSITA would have understood Lambrecht
`
`to suggest, and would have found it obvious that, arbitration logic 504 could
`
`
`
`13
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`

`comprise a processor for the purpose of realizing some or all aspects of arbitration
`
`logic 504.
`
`35.
`
`In fact, this approach is taught in Lambrecht with respect to FIG. 13.
`
`Lambrecht teaches using a processor 702 (located in the real-time section of the
`
`system) to coordinate and control communications between multimedia devices
`
`142-146. Lambrecht at FIG. 13, 19:8-56. The I/O processor 702 performs similar
`
`functions to logic 504 in that they are both responsible for coordinating and
`
`monitoring communications between the multimedia devices. For this additional
`
`reason, upon reviewing the system in FIG. 13, a POSITA would have recognized
`
`the feasibility and advantages of implementing logic 504 using a processor with
`
`capabilities that are similar to those of I/O processor 702.
`
`36.
`
`In general, programmable processors were in wide use as of the
`
`Critical Date, due, in large part, to the flexibility they offer. For example, a
`
`programmable processor enables one to easily update the program instructions for
`
`implementing the logic 504, for example to improve or change the processes
`
`defined by logic, correct errors, and add functionality, without requiring
`
`redesigning and manufacturing new dedicated hardware. It was common as of the
`
`Critical Date, for initial hardware designs to have errors.
`
` By using a
`
`programmable processor, fixing many design errors or improving the logic
`
`functionality may be as simple as a firmware update. Using a processor to
`
`
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`14
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`

`implement logic 504 would yield a predictable result, and a POSITA would expect
`
`to be successful implementing logic 504 on a programmable processor, since
`
`processors were commonplace as of the Critical Date and used as part of many
`
`similar system designs.
`
`37. Moreover, the resulting processor for logic 504 would operate in
`
`similar ways to the processor 702, which Lambrecht illustrated would work in a
`
`similar application (for instance, as discussed below, processor 702 coordinates
`
`and controls communications in a byte sliced implementation of Lambrecht’s
`
`system). A POSITA would have been motivated to implement some or all of the
`
`aspects of the logic 504 with a processor to benefit from the advantages of a
`
`programmable processor. Therefore, in my opinion, it would have been obvious to
`
`a POSITA to implement logic 504 with a programmable processor before the
`
`Critical Date.
`
`B. A POSITA would have been motivated to implement the central
`agent within logic 504
`38. Below, I discuss an aspect of Lambrecht’s system referred to as a
`
`“central agent.” Lambrecht describes a time-slicing scheme for assigning and
`
`managing communication channels. Lambrecht at FIGS. 11-12, 17:62-19:6.
`
`Lambrecht also describes that the “central agent” may be used for implementing
`
`the time slicing scheme. Lambrecht at 18:12-27. Lambrecht teaches that the
`
`“central agent” is a piece of “software,” which as an example, may be executed by
`
`
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`15
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`the CPU 102. Id. at 18:16-20. Nevertheless, it is evident from the plain text of
`
`Lambrecht that the intention was not to limit the “central agent” to being
`
`implemented by the CPU 102 exclusively. In the alternative, the “central agent”
`
`could be one or more code sections executed by some processor other than the
`
`CPU 102.
`
`39.
`
`In my opinion, a POSITA would have understood that there were
`
`multiple ways to implement the “central agent” functionality and would have
`
`considered the logic 504 to be superior to the CPU 102 for implementing the
`
`“central agent” because the logic 504 provides several advantages over the CPU
`
`102, including but not limited to reduced latency, reduced complexity, and reduced
`
`transport delay. These advantages would have motivated a POSITA to implement
`
`the “central agent” using the processor operating the logic 504.
`
`Reduced Latency
`
`40. Lambrecht’s central teachings focus on “an improved computer
`
`system architecture”
`
`that “is optimized
`
`for
`
`real-time multimedia and
`
`communications applications.” Id. at 2:16-20 (emphasis added). In particular,
`
`Lambrecht expressly instructs that the “central agent” should “dynamically
`
`programs timeslots in each of the multimedia devices dependent upon real-time
`
`processes and applications occurring in the computer system.” Id. at 18:24-27.
`
`
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`16
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`41.
`
`In my opinion, logic 504 is better suited for rendering real-time
`
`“central agent” services than the CPU 102. This approach generally more closely
`
`comports with the strategy of performing real-time functions in the real-time part
`
`of the system.
`
`42. Note that CPU 102 is configured to process both real-time loads and
`
`non-real-time loads. In any given processing cycle, the CPU 102 can process
`
`either the demands of allocating time-sliced channels in real-time or the demands
`
`of other non-realtime loads, but not both. As discussed in 7:7-11 of Wing So, it
`
`was common knowledge before the Critical Date that: “Two key challenges in
`
`servicing multimedia are the need for high bandwidth for multimedia data and the
`
`ability to service real-time interrupts. These challenges can create bottlenecks and
`
`interrupt latency which translates into constraints or limits on ability to service
`
`real-time events.” It was also common knowledge, as 9:12-22 of Koval et al.
`
`demonstrates, that “task dispatch latency” may “delay even time-critical threads”
`
`when the processor [CPU] is faced with “heavy system load.”
`
`43. With this background knowledge in mind, it becomes apparent that,
`
`while executing the “central agent” software, the CPU 102 may be unable to fully
`
`dedicate real-time resources for assigning time-sliced channels during the real-time
`
`events of the multimedia devices 142A-146A. This lack of dedication introduces
`
`latency to the control of real-time communications between the multimedia devices
`
`
`
`17
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`

`142A-146A, which may be undesirable in view of the aspiration set forth by
`
`Lambrecht.
`
`44. Lambrecht’s desire for rapidly transferring real-time data between
`
`multimedia devices would have suggested to a POSITA to minimize latency while
`
`updating the time-slicing functionality of the “central agent.” Thus, a POSITA
`
`would have been motivated to implement the “central agent” in a processor located
`
`in the real-time section of the system.
`
`45. Logic 504 would be a great candidate for such a replacement because
`
`unlike the CPU 102, logic 504 is dedicated to providing real-time services to the
`
`multimedia devices 142A-146A. Lambrecht at 15:21-31. These real-time services
`
`include the coordinating and controlling real-time communication channels
`
`between the multimedia devices 142A-146A. Id. Because the processor in the
`
`logic 504
`
`is already
`
`tasked with coordinating and controlling real-time
`
`communications, implementing the “central agent” within logic 504 involves no
`
`more than sharing a common processor.
`
`46. For the benefit of minimizing latency, a POSITA would have had the
`
`freedom to optimize logic 504 for performing the channel allocation tasks of the
`
`“central agent,” as well as the other coordinating and controlling tasks. By
`
`contrast, the CPU 102 might not be able to perform these tasks so rapidly because
`
`it must accommodate many other functions not focused on the channel allocation
`
`
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`18
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`

`tasks of the “central agent.” Unlike the CPU 102, the common processor of logic
`
`504 does not need to consume processing time performing other operations
`
`unrelated to real-time communications. Using logic 504 to implement the “central
`
`agent” can mitigate the latency introduced by the CPU 102 for transferring control
`
`instructions for transferring real-time data between multimedia devices.
`
`Reduced Data Transport Delay
`
`47. Moreover, for the purpose of implementing the “central agent,” less
`
`transport delay occurs between a multimedia processor and the “central agent”
`
`when that “central agent” function is performed by logic 504 rather than CPU 102.
`
`As shown in FIG. 7, logic 504 is connected more directly to the multimedia
`
`devices 142A-146A than the CPU 102. Thus requests for action by the “central
`
`agent” will require less time on their trips to and from the “central agent” when the
`
`“central agent” functionality is realized in logic 504. In particular, note that these
`
`requests (and corresponding responses) must pass through PCI Bridge Chipset 106
`
`when the “central agent” resides in the CPU.
`
`48. One simple example of this situation is where the rate of information
`
`production for a multimedia processor temporarily increases. To communicate the
`
`additional
`
`information
`
`to another other multimedia processor, higher
`
`communication bandwidth at this point is required. Since, as shown in Figure 7,
`
`all multimedia processors are essentially directly connected to logic 504 (via bus
`
`
`
`19
`
`

`

`502), minimal message transport delays for requests and responses will occur
`
`between the multimedia processor and logic 504 – because the “central agent” is
`
`now implemented in logic 504. In contrast, when the “central agent” functions are
`
`performed in the CPU, additional information transport delays will be incurred due
`
`to communication through PCI Bridge Chipset 106. In this case, real-time
`
`requirements may not be satisfied due to transport delays between the multimedia
`
`device and the CPU.
`
`49.
`
` In view of Lambrecht’s
`
`teachings, a POSITA would have
`
`recognized that proximity between logic 504 and the multimedia devices enhances
`
`the real-time functionality of the system.
`
`Off-loading Part of the Work Load of CPU 102
`
`50. Also, using the processor of logic 504 to implement the “central
`
`agent” relieves the CPU 102 from providing services the associated services for the
`
`multimedia devices 142A-146A. As a result, the CPU 102 may allocate more of
`
`its processing time to other non-realtime applications, while the logic 504 is
`
`dedicated to servicing real-time applications. As a result, the CPU will more
`
`quickly accomplish its system level tasks, and less latency will occur in the CPU’s
`
`response to high priority system events because it can be available to respond to
`
`those events while logic 504 performs all the “central agent” tasks.
`
`Lambrecht Teaches a Similar Approach for the System of Figure 13
`
`
`
`20
`
`

`

`51. Lambrecht fully describes the functions performed by the “central
`
`agent” as well as logic 504. Moreover, in an alternate embodiment shown in FIG.
`
`13, Lambrecht discusses using a dedicated multimedia I/O processor 702 to assign
`
`communication channels to multimedia devices 142-146. Lambrecht at FIG. 13,
`
`19:8-56. The processor 702 performs similar functions as the “central agent” in
`
`that processor 702 performs the function of assigning “one data stream to a subset
`
`of the total byte lanes” Lambrecht 19:45-48.
`
`52. Considering the totality of Lambrecht’s teachings, a POSITA would
`
`have recognized that implementing the “central agent” using a processor inside
`
`logic 504 would be predictable and a POSITA would have a reasonable
`
`expectation of success.
`
`53. This is because the implementation involves known components –
`
`programmable processors -- that were commonplace as of the Critical Date and
`
`used for many similar aspects of computers, such as Lambrecht’s I/O processor
`
`702 – used in a conventional manner – to perform functions much like the those of
`
`Lambrecht’s I/O processor 702. Lambrecht, further, places no special emphasis
`
`on the CPU 102, or any special characteristics of the CPU 102, for performing the
`
`“central agent” tasks. Thus, there is no teaching in the Lambrecht specification
`
`that a processor performing the functions of logic 504 could not also perform the
`
`“central agent” functions.
`
`
`
`21
`
`

`

`VI. The Lambrecht System based on Figure 7
`A. Claims 2 and 15
`54. The Lambrecht system describes a computer system that includes a
`
`host computer and may include one or more audio-video (AV) processing systems,
`
`which are coupled to each other via control channel 502 and multimedia bus 130.
`
`Id. at 12:48-14:12. Within the AV processing system, Lambrecht describes
`
`arbitration logic 504 as a standalone component which, as explained above, may
`
`include software stored in a RAM, and a processor for executing the software
`
`(hereinafter “the logic 504”). Id. The logic 504 is coupled to several multimedia
`
`devices 142A-146A via a control channel 502. Id. Logic 504 is a centralized
`
`controller in that it coordinates the direct communications between the multimedia
`
`devices. Id. at 14:8-12, 15:7-16:25, 18:41-19:6. These embodiments of the
`
`Lambrecht system minimize the ongoing control communications between
`
`subsystems, which “provides increased performance for real-time applications.”
`
`Id. at 2:54-67, 28:14-26.
`
`
`
`22
`
`

`

`Lambrecht at FIG. 7
`
`
`
`55. The Lambrecht system
`
`is for coordinating and controlling
`
`communications over a plurality of subsystems. (claim element 2.01) The
`
`system, which is a computer system shown partially in Lambrecht’s FIG. 7,
`
`
`1 See Challenged Claims in Appendix B.
`
`
`
`23
`
`

`

`includes multimedia devices 142A-146A that are “a plurality of subsystems.”
`
`(claim element 2.1) The multimedia devices are coupled to a multimedia bus 130
`
`to communicate data between respective devices, and coupled to a control channel
`
`502 “for addressing and control of the multimedia bus 130.” Id. at 13:46-47,
`
`12:48-62, 13:37-47, 13:61-14:4. Thus, a POSITA would understand that the
`
`Lambrecht system is a real-time communication system that is used for
`
`coordinating and controlling communications over a plurality of subsystems.
`
`(claim element 2.0)
`
`56. The system includes logic 504 connected with

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