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`1111111111111111111111111111111111111111111111111111111111111
`US007673072B2
`
`(12) United States Patent
`Boucher et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,673,072 B2
`Mar. 2,2010
`
`(54) FAST-PATH APPARATUS FOR
`TRANSMITTING DATA CORRESPONDING
`TO A TCP CONNECTION
`
`(75)
`
`Inventors: Laurence B. Boucher, Saratoga, CA
`(US); Stephen E. J. Blightman, San
`Jose, CA (US); Peter K. Craft, San
`Francisco, CA (US); David A. Higgen,
`Saratoga, CA (US); Clive M. Philbrick,
`San Jose, CA (US); Daryl D. Starr,
`Milpitas, CA (US)
`
`(73) Assignee: Alacritech, Inc., San Jose, CA (US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.c. 154(b) by 435 days.
`
`(21) Appl. No.: 11/821,820
`
`(22) Filed:
`
`Jun. 25, 2007
`
`(65)
`
`Prior Publication Data
`
`US 2008/0126553 Al
`
`May 29,2008
`
`(63)
`
`Related U.S. Application Data
`
`Continuation of application No. 10/260,112, filed on
`Sep. 27, 2002, now Pat. No. 7,237,036, which is a
`continuation of application No. 10/092,967, filed on
`Mar. 6, 2002, now Pat. No. 6,591,302, which is a
`continuation-in-part of application No. 10/023,240,
`filed on Dec. 17,2001, now Pat. No. 6,965,941, which
`is a continuation-in-part of application No. 09/464,
`283, filed on Dec. 15, 1999, now Pat. No. 6,427,173,
`which is a continuation-in-part of application No.
`09/439,603, filed on Nov. 12, 1999, now Pat. No.
`6,247,060, which is a continuation-in-part of applica(cid:173)
`tion No. 091067,544, filed on Apr. 27,1998, now Pat.
`No. 6,226,680, said application No. 10/260,112 is a
`continuation-in-part of application No. 09/384,792,
`filed on Aug. 27, 1999, now Pat. No. 6,434,620, which
`is a continuation-in-part of application No. 091141,
`713, filed on Aug. 28,1998, now Pat. No. 6,389,479,
`
`said application No. 10/260,112 is a continuation-in(cid:173)
`part of application No. 091970,124, filed on Oct. 2,
`2001, now Pat. No. 7,124,205, and a continuation-in(cid:173)
`part of application No. 09/855,979, filed on May 14,
`2001, now Pat. No. 7,133,940, and a continuation-in(cid:173)
`part of application No. 09/802,550, filed on Mar. 9,
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`part of application No. 09/802,426, filed on Mar. 9,
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`part of application No. 09/802,551, filed on Mar. 9,
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`part of application No. 09/675,700, filed on Sep. 29,
`2000, and a continuation-in-part of application No.
`09/675,484, filed on Sep. 29, 2000, now Pat. No.
`6,807,581, and a continuation-in-part of application
`No. 09/514,425, filed on Feb. 28, 2000, now Pat. No.
`6,427,171, and a continuation-in-part of application
`No. 09/416,925, filed on Oct. 13, 1999, now Pat. No.
`6,470,415.
`
`(60) Provisional application No. 601061,809, filed on Oct.
`14, 1997, provisional application No. 601098,296,
`filed on Aug. 27, 1998.
`
`(51)
`
`(52)
`
`(58)
`
`Int. Cl.
`G06F 15116
`(2006.01)
`U.S. Cl. ....................... 7091245; 709/230; 709/233;
`709/234; 709/232; 709/239; 370/235; 370/468;
`370/237; 370/230; 370/233
`Field of Classification Search ................. 709/245,
`709/230-234,239,250; 370/235,468,237,
`370/230, 233, 234
`See application file for complete search history.
`
`(56)
`
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`50
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`52
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`46
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`48
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`UPPER
`LAYER
`UPPER LAYER
`INTERFACE
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`TRANSPORT
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`NETWORK
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`DATA LINK
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`44
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`56
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`40
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`58
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`INTEL Ex.1001.001
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`

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`US 7,673,072 B2
`Page 2
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`
`INTEL Ex.1001.002
`
`

`

`US 7,673,072 B2
`Page 3
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`corniproducts,html, 2 pages, downloaded Nov. 25, 1998.
`iReady News Archives, Toshiba, iReady shipping Internet chip, 1
`page, printed Nov. 25, 1998.
`Interprophet article entitled "Technology", http://www.interprophet.
`cornitechnology.html, 17 pages, printed Mar. 1, 2000.
`iReady Corporation, article entitled "The 1-1000 Internet Tuner", 2
`pages, date unknown.
`iReady article entitled "About Us Introduction", Internet pages
`frornhttp://www.iReadyco.comiabout.html.3pages.printed Nov.
`25, 1998.
`iReady News Archive article entitled "Revolutionary Approach to
`Consumer Electronics Internet Connectivity Funded", San Jose, CA,
`Nov. 20,1997. 2 pages, printed Nov. 2, 1998.
`iReady News Archive article entitled "Seiko Instruments Inc. (SII)
`Introduces World's First Internet-Ready Intelligent LCD Modules
`Based on iReady Technology," Santa Clara, CA and Chiba, Japan,
`Oct. 26, 1998.2 pages, printed Nov. 2, 1998.
`NEWSwatch article entitled "iReady internet Tuner to Web Enable
`Devices", Tuesday, Nov. 5, 1996, printed Nov. 2, 1998,2 pages.
`EETimes article entitled "Tuner for Toshiba, Toshiba Taps iReady for
`Internet Tuner", by David Lammers, 2 pages, printed Nov. 2, 1998.
`"Comparison of Novell Netware and TCPIIP Protocol Architec(cid:173)
`tures", by J.S. Carbone, 19 pages, printed Apr. 10, 1998.
`Adaptec article entitled "AEA-7110C-a DuraSAN product", 11
`pages, printed Oct. 1, 2001.
`iSCSI HBA article entitled "iSCSI and 2Gigabit fibre Channel Host
`Bus Adapters from Emulex, QLogic, Adaptec, JNI", 8 pages, printed
`Oct. 1, 2001.
`iSCSI HBA article entitled "FCE-3210/641O 32 and 64-bit PCI-to(cid:173)
`Fibre Channel HBA", 6 pages, printed Oct. 1, 2001.
`ISCSI.com article entitled "iSCSI Storage", 2 pages, printed Oct. 1,
`2001.
`"Two-Way TCP Traffic Over Rate Controlled Channels: Effects and
`Analysis", by Kalampoukas et aI., IEEE Transactions on Network(cid:173)
`ing, vol. 6, No.6, Dec. 1998, 17 pages.
`IReady News article entitled "Toshiba Delivers First Chips to Make
`Consumer Devices Internet-Ready Based on iReady Design", Santa
`Clara, CA, and Tokyo, Japan, Oct. 14, 1998, printed Nov. 2, 1998,3
`pages.
`
`INTEL Ex.1001.003
`
`

`

`US 7,673,072 B2
`Page 4
`
`Internet pages of InterProphet entitled "Frequently Asked Ques(cid:173)
`tions", by Lynne Jolitz, printed Jun. 14,2000,4 pages.
`"File System Design For An NFS File Server Appliance", Article by
`D. Hitz, et ai., 13 pages.
`Adaptec Press Release article entitled "Adaptec Announces
`EtherStorage Technology", 2 pages, May 4, 2000, printed Jun. 14,
`2000.
`Adaptec article entitled "EtherStorage Frequently Asked Questions",
`5 pages, printed Jui. 19,2000.
`Adaptec article entitled "EtherStorage White Paper", 7 pages, printed
`Jui. 19,2000.
`CIBC World Markets article entitled "Computers; Storage", by J.
`Berlino et al., 9 pages, dated Aug. 7, 2000.
`Merrill Lynch article entitled "Storage Futures", by S. Milunovich,
`22 pages, dated May 10, 2000.
`CBS Market Watch article entitled "Montreal Start-Up Battles Data
`Storage Botttieneck", by S. Taylor, dated Mar. 5, 2000, 2 pages,
`printed Mar. 7, 2000.
`Internet-draft article entitled "SCSI/TCP (SCSI over TCP)", by J.
`Satran et al., 38 pages, dated Feb. 2000, printed May 19, 2000.
`Internet pages entitled Technical White Paper-Xpoint's Disk to LAN
`Acceleration Solution for Windows NT Server, printed Jun. 5, 1997,
`15 pages.
`Jato Technologies article entitled Network Accelerator Chip Archi(cid:173)
`tecture, twelve-slide presentation, printed Aug. 19, 1998, 13 pages.
`EETimes article entitled Enterprise System Uses Flexible Spec,
`dated Aug. 10,1998, printed Nov. 25,1998,3 pages.
`Internet pages entitled "Smart Ethernet Network Interface Cards",
`which Berend Ozceri is developing, printed Nov. 25, 1998,2 pages.
`Internet pages of Xaqti corporation entitled "GigaPower Protocol
`Processor Product Review," printed Nov. 25, 1999,4 pages.
`U.S. Appi. No. 601283,896, Titled: CRC Calculations for Out of
`Order PUDs, filed Apr. 12, 2003, Inventor: Amit Oren, Assignee:
`Siliquent Technologies Ltd.
`Internet pages entitled "DART: Fast Application Level Networking
`via Data-Copy Avoidance," by Robert J. Walsh, printed Jun. 3, 1999,
`25 pages.
`Andrew S. Tanenbaum, Computer Networks, Third Edition, 1996,
`ISBN 0-13-349945-6.
`Article from Rice University entitled "LRP: A New Network Sub(cid:173)
`system Architecture for Server Systems", by Peter Druschel and
`Gaurav Banga, 14 pages.
`Internet RFC/STD/FYI/BCP Archives article with heading
`"RFC2140" entitled "TCP Control Block Interdependence", web
`address http://www.faqs.org/rfcs/rfc2140.htrnl.9pages.printed Sep.
`20,2002.
`WindRiver article entitled "Tornado: For Intelligent Network Accel(cid:173)
`eration", copyright Wind River Systems, 2001, 2 pages.
`WindRiver White Paper entitled "Complete TCP/IP Offload for
`High-Speed Ethernet Networks", Copyright Wind River Systems,
`2002, 7 pages.
`Intel article entitled "Solving Server Bottlenecks with Intel Server
`Adapters", Copyright Intel Corporation, 1999,8 pages.
`Schwaderer et ai., IEEE Computer Society Press publication entitled,
`"XTP in VLSI Protocol Decomposition for ASIC Implementation",
`from 15th Conference on Local Computer Networks, 5 pages, Sep.
`30-0ct. 3, 1990.
`Beach, Bob, IEEE Computer Society Press publication entitled,
`"UltraN et: An Architecture for Gigabit Networking", from 15th Con(cid:173)
`ference on Local Computer Networks, 18 pages, Sep. 30-0ct. 3,
`1990.
`
`Chesson et ai., IEEE Syposium Record entitled, "The Protocol
`Engine Chipset", from Hot Chips III, 16 pages, Aug. 26-27,1991.
`Maclean et ai., IEEE Global Telecommunications Conference,
`Globecom '91, presentation entitled, "An Outboard Processor for
`High Performance Implementation of Transport Layer Protocols", 7
`pages, Dec. 2-5, 1991.
`Ross etai., IEEE article entitled "FXI000: Ahigh performance single
`chip Gigabit Ethernet NIC", from Compcon '97 Proceedings, 7
`pages, Feb. 23-26, 1997.
`Strayer et ai., "Ch. 9: The Protocol Engine" from XTP: The Transfer
`Protocol, 12 pages, Jui. 1992.
`Publication entitled "Protocol Engine Handbook", 44 pages, Oct.
`1990.
`Koufopavlou et ai., IEEE Global Telecommunications Conference,
`Globecom '92, presentation entitled, "Parallel TCP for High Perfor(cid:173)
`mance Communication Subsystems", 7 pages, Dec. 6-9, 1992.
`Lilienkamp et ai., Publication entitled "Proposed Host-Front End
`Protocol", 56 pages, Dec. 1984.
`Thia et ai. Publication entitled "High-Speed OSI Protocol Bypass
`Algorithm with Window Flow Control," Protocols for High Speed
`Networks, pp. 53-68, 1993.
`U.S. Appi. No. 601053,240, Titled: TCP/IP Network Accelerator and
`Method of Use, filed Jui. 17, 1997, Inventor: William Jolizt et ai.
`Thia et ai. Publication entitled "A Reduced Operational Protocol
`Engine (ROPE) for a multiple-layer bypass architecture," Protocols
`for High Speed Networks, pp. 224-239, 1995.
`Form 10-K for Exelan, Inc., for the fiscal year ending Dec. 31, 1987
`(10 pages).
`Form 10-K for Exelan, Inc., for the fiscal year ending Dec. 31, 1988
`(10 pages).
`* cited by examiner
`Primary Examiner-Jude J Jean Gilles
`(74) Attorney, Agent, or Firm-Mark Lauer; Silicon Edge
`Law Group, LLP
`
`(57)
`
`ABSTRACT
`
`A system for protocol processing in a computer network has
`an intelligent network interface card (INIC) or communica(cid:173)
`tion processing device (CPD) associated with a host com(cid:173)
`puter. The INIC provides a fast-path that avoids protocol
`processing for most large multi-packet messages, greatly
`accelerating data communication. The INIC also assists the
`host for those message packets that are chosen for processing
`by host software layers. A communication control block for a
`message is defined that allows DMA controllers of the INIC
`to move data, free of headers, directly to or from a destination
`or source in the host. The context is stored in the INIC as a
`communication control block (CCB) that can be passed back
`to the host for message processing by the host. The INIC
`contains specialized hardware circuits that are much faster at
`their specific tasks than a general purpose cpu. A preferred
`embodiment includes a trio of pipelined processors with
`separate processors devoted to transmit, receive and manage(cid:173)
`ment processing, with full duplex communication for four
`fast Ethernet nodes.
`
`21 Claims, 89 Drawing Sheets
`
`INTEL Ex.1001.004
`
`

`

`35~ STORAGE r---
`
`I
`I
`I
`I
`I
`I
`I
`30 I
`~ CPD
`
`1 -
`
`~33
`
`I
`I
`I
`I
`L _____ - - - - - - - - - - - - - - - - -
`
`r 22
`
`REMOTE
`HOST
`
`25\
`
`(50
`
`42,,-
`
`u.s. Patent
`
`Mar. 2,2010
`
`Sheet 1 of89
`
`US 7,673,072 B2
`
`20
`r------------------------,
`HOST
`1--/
`I
`
`,
`
`28
`
`-
`
`CPU
`
`CONTEXT
`
`~
`
`52
`'--
`
`FIG. 1
`
`( 46
`
`UPPER
`LAYER
`UPPER LAYER 48\
`INTERFACE
`
`\
`
`44
`
`54)
`TRANSPORT
`4~
`38"'-
`
`NETWORK
`
`r - DATA LINK
`36
`
`30\
`
`56
`~
`,Ir
`
`INIC/CPD
`
`....
`
`FIG. 2
`
`STORAGE
`
`"-
`
`35
`
`~8
`
`INTEL Ex.1001.005
`
`

`

`u.s. Patent
`
`Mar. 2,2010
`
`Sheet 2 of89
`
`US 7,673,072 B2
`
`RECEIVE PACKET
`FROM NETWORK
`BYCPD
`
`VALIDATE PACKET,
`SUMMARIZE
`HEADERS
`
`47
`
`57
`
`61
`
`5~
`
`FAST PATH
`CANDIDATE?
`
`NO
`
`SEND PACKET TO
`STACK FOR SLOW-
`PATH PROCESSING
`
`67
`
`YES
`
`53
`
`65
`
`NO
`
`SEND PACKET TO
`STACK FOR SLOW-
`PATH PROCESSING
`
`CREATE CCB FOR
`MESSAGE
`
`51
`
`CCB?
`
`YES
`
`69
`
`SEND TO
`DESTINATION
`IN HOST VIA
`FAST-PATH
`
`FIG. 3
`
`INTEL Ex.1001.006
`
`

`

`u.s. Patent
`
`Mar. 2,2010
`
`Sheet 3 of89
`
`US 7,673,072 B2
`
`REMOTE
`HOST
`
`25
`
`FIG.4A
`
`65
`r - - - - - - - l
`I
`f-----L+K:::-l
`I
`I
`I
`I
`I
`I
`
`40
`38
`36
`
`SESS
`TRANS
`NETW
`DUNK
`~44
`
`SESS
`TRANS
`NETW
`DUNK
`
`56
`
`~44
`
`I
`I
`35 I
`'-1
`I
`L _______
`
`40
`38
`36
`
`42
`40
`38
`36
`
`SESS
`TRANS
`NETW
`DLINK
`
`~44
`
`r--- ---,
`I
`I
`I
`1
`70 1
`35
`:
`'--i
`1
`I
`L _______ I
`
`1
`
`REMOTE
`HOST
`
`REMOTE
`HOST
`
`REMOTE
`HOST
`
`32
`
`32
`
`FIG.4C
`
`FIG.4D
`
`INTEL Ex.1001.007
`
`

`

`u.s. Patent
`
`Mar. 2,2010
`
`Sheet 4 of89
`
`US 7,673,072 B2
`
`REMOTE
`HOST
`
`42
`~SE~S~S~--.-J~--rMI :
`TRANS
`NETW
`,..-_,--...., DLINK
`96
`
`99
`
`1
`
`L.......-_-' 1
`
`1
`1
`
`L - -,- - --,
`)
`35·...-
`~44
`
`~--------~
`
`FIG. 5
`
`15l
`
`152-, ,----- -- --------1
`1
`FAST-PATH
`: : ~ SOURCEIDEST
`168 -r
`.. ~
`
`APPLICATION
`
`C157 . -----\:-------
`
`1
`
`I
`
`158
`
`1
`1
`1
`1
`1
`1
`1
`-'
`
`INTEL Ex.1001.008
`
`1
`166 - - 1 .
`1
`1
`164~ TRANSPORT
`1
`:-t---
`162
`1
`1
`1
`1
`1
`1
`1
`1
`160,-+-
`1
`1
`1 HARDWARE LOGIC
`1 SLOW-PATH
`1
`..l.
`~I
`L __________________ '.
`I
`1
`171
`~155
`"
`
`185
`150 '" 170
`: ___ L ___ ~ ______ - \_ -
`
`PROCESSOR
`
`S
`
`FIG. 6
`
`1
`
`NETWORK
`
`DATA LINK
`
`

`

`u.s. Patent
`
`Mar. 2,2010
`
`Sheet 5 of89
`
`US 7,673,072 B2
`
`MEDIA ACCESS r----.-- 172
`CONTROLLER
`I
`
`l'
`ASSEMBLY r------- 174
`REGISTER
`
`(178
`)
`
`..
`FLYBY
`.~-- SEQUENCER
`MULTIPLEXOR r----.-- 180
`
`"
`
`PACKET
`CONTROL
`SEQUENCER
`J
`
`SRAM
`
`...-
`
`SRAM
`CONTROL
`
`...-
`
`"
`
`DRAM CONTROL
`
`C 186
`
`l'
`
`DRAM
`
`r------- 188
`
`QUEUE
`184"'-- MANAGER
`
`FIG. 7
`
`INTEL Ex.1001.009
`
`

`

`u.s. Patent
`
`Mar. 2,2010
`
`Sheet 6 of89
`
`US 7,673,072 B2
`
`) 174
`
`PACKET
`176 ______ CONTROL
`SEQUENCER
`
`I----~
`
`.. ASSEMBLY
`REGISTER
`
`178
`
`r---- 191
`MAC
`~ 1 -4 - - - - - - -1
`SEQUENCER
`
`1
`
`r---- 192
`NETWORK _
`1 -4 - - - - - - - - - J
`SEQUENCER
`
`TRANSPORT ~ 194
`I-0Il-1--------1
`SEQUENCER
`
`SESSION ~ 195
`14 - - - - - -
`SEQUENCER """
`
`MULTIPLEXOR
`
`FIG. 8
`
`INTEL Ex.1001.010
`
`

`

`u.s. Patent
`
`Mar. 2,2010
`
`Sheet 7 of89
`
`US 7,673,072 B2
`
`FAST-PATH~", SOURCEIDEST
`I'
`'t3~~ __ :~~~i_~3~_i~4 -r- r:;237
`222~ APPLICATION ,~
`~ f - - - - - - - -H
`PROCESSOR)
`220
`I
`I
`I
`, '" HARDWARE LOGIC 4 :
`217---r TRANSPORT
`262, I ~
`I
`II
`I - - - - - - - - - - - t - l
`~ ~HARDWARELOGIC3 S:
`215~NETWORK
`r+--; HARDWARE LOGIC 2
`212
`I
`I
`I
`/
`' - - - I I - - - - - - -H
`: HARDWARE LOGIC 1
`: \ SLOW-PATH; MAC
`I
`I : '----------'
`" L~210-----t-----;6~- '. C • ------',~-----
`
`240 ./
`
`,~
`
`~
`
`250
`
`205
`
`202
`
`FIG. 9
`
`TDIUSERS ~ 382
`
`- - -
`
`TDI FILTER DRIVER
`I~
`& UPPER LAYER INTERFACE
`
`I~ ATCP
`
`360
`
`- - -
`TCP ~ 358
`
`366
`;~
`
`IP
`
`IP ~ 355
`
`350
`
`363 ~ MAC
`- - -
`375 ~ NDIS
`
`MAC ~ 353
`---
`
`)1'
`
`,Ir
`
`I'
`,,..
`
`377 ~ INIC MINIPORT DRIVER
`
`FIG. 11
`
`INTEL Ex.1001.011
`
`270
`
`231
`
`:
`I
`
`II
`
`242
`'--
`
`

`

`u.s. Patent
`
`Mar. 2,2010
`
`Sheet 8 of89
`
`US 7,673,072 B2
`
`r--------------------------------I
`202/~,_~
`I
`I
`I
`
`300
`"\ 318~
`
`, ' - - - - -
`
`UPPERLAYER
`
`~.I--': ___ -"
`
`"
`
`I
`I
`I
`:
`I
`~III
`- 316
`I ~
`I
`
`:
`:
`I
`I
`I
`,~.
`330
`1--'
`I
`.~I
`325
`r----'
`I
`I
`322~ NETWORK
`I
`I 1--_____ --1
`I
`I
`320~ DATALINK
`DATALINK ~ 312
`I
`I
`I
`I'
`I'
`I
`I
`L ________________________ -t. _____ 1
`'--310
`,w-
`'w-
`
`UPPER LAYER INTERFACE
`
`TRANSPORT
`
`TRANSPORT
`
`NETWORK
`
`~314
`
`240~
`
`306 ~ INIC MINIPORT DRIVER
`
`J
`
`1
`
`INIC
`
`200~
`
`(
`
`210
`
`INIC
`MEMORY ~304
`
`FIG. 10
`
`INTEL Ex.1001.012
`
`

`

`190 ._,,-~-------cLiENT------1
`
`,...--
`
`I,i-----~
`
`168
`
`166
`
`164
`157
`162
`
`160
`
`5MB
`
`NETBIOS
`
`TCP
`
`IP
`
`MAC
`
`~159
`
`-------------1
`SERVER
`l_"-" 290
`I
`I
`
`5MB
`
`NETBIOS
`
`TCP
`
`IP
`
`MAC
`
`INrc
`
`210
`
`INIC
`
`L _______________ __ _
`
`L. _____ _
`
`___ J
`
`240
`
`244
`
`242
`
`FIG. 12
`
`~
`7Jl
`•
`~
`~
`~
`
`~ = ~
`
`N
`
`~
`~ :-:
`N o .... o
`
`~
`
`('D
`('D
`
`rFJ =(cid:173)
`.....
`\0
`o ....
`
`QO
`\0
`
`222
`
`220
`
`217
`231
`215
`
`212
`
`200
`
`d
`rJl
`-....l
`0..,
`-....l
`
`-....l
`
`W -=
`N = N
`
`INTEL Ex.1001.013
`
`

`

`u.s. Patent
`
`Mar. 2,2010
`
`Sheet 10 of 89
`
`US 7,673,072 B2
`
`210
`
`400 -, 240
`\
`_______ L ___ _
`
`200~
`.,
`
`42
`
`244
`
`----,
`
`MAC-A
`
`402 MAC-B
`
`04
`
`MAC-C
`
`406
`
`MAC-D
`
`1
`
`1
`
`:
`
`412
`
`1
`1
`1
`
`416 1
`
`XMT&
`RCV-A
`
`418
`
`XMT&
`RCV-B
`
`420
`
`428
`
`426
`
`XMT&
`RCV-C
`430
`
`422
`42
`
`XMT&
`RCV-D
`
`43
`
`REG FILE
`WCS
`ROM
`
`477
`
`:---MfCRO----: 470
`1 PROCESSOR L_/
`1 r - - - - - - - - ,
`1
`1
`1
`1
`1
`
`: 484
`
`464
`
`440
`
`SRAM
`
`EXTERNAL
`MEMORY
`CTRL
`
`SRAM
`CTRL
`____ ,_1
`'-444
`
`1
`1
`
`1
`1
`
`446
`
`450
`
`468
`
`PCI BUS INTERFACE UNIT
`
`1
`1
`
`1 ______ - - - - - - - - - - - - - - - - - -
`
`1
`1
`___________________ J
`
`257
`
`FIG. 13
`
`455
`1 - - - - - - -
`
`1
`1
`
`1
`
`1
`1
`1
`
`DRAM
`
`460
`
`INTEL Ex.1001.014
`
`

`

`u.s. Patent
`
`Mar. 2,2010
`
`Sheet 11 of 89
`
`US 7,673,072 B2
`
`CLOCK r--r-------L----- L ______ /- ______ L _____ L __
`
`/
`
`/
`I
`I
`I
`I
`I
`I
`
`/
`
`/
`
`500'-,
`,
`
`)
`I
`
`492.....,
`
`CONTROLS FOR FIRST REGISTER SET
`
`490\
`
`505
`
`-../"'
`
`533\
`
`FIRST REGISTER SET
`
`~ I
`I
`I :
`I
`, ,
`I
`>-- f------- - - - - - - - - -