throbber

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`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________
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`INTEL CORP. and CAVIUM, INC.,
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`Petitioners,
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`v.
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`ALACRITECH, INC.,
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`Patent Owner
`________________
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`Case IPR2017-014061
`U.S. Patent No. 7,673,072
`________________
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`PATENT OWNER’S RESPONSE
`PURSUANT TO 35 U.S.C. § 313 AND 37 C.F.R. § 42.107
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`1 Cavium, Inc., which filed a Petition in Case IPR2017-01707, has been
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`joined as a petitioner in this proceeding.
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`I.
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`II.
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`U.S. Patent No. 7,673,072
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`TABLE OF CONTENTS
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`Page
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`INTRODUCTION ........................................................................................... 1
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`BACKGROUND OF THE TECHNOLOGY ................................................. 2
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`III. OVERVIEW OF THE ’072 PATENT ............................................................ 8
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`A.
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`B.
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`The ’072 Patent Specification ............................................................... 8
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`The ’072 Patent Claims ....................................................................... 14
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`IV. PROSECUTION HISTORY OF THE ’072 PATENT ................................. 15
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`V. OVERVIEW OF THE ASSERTED PRIOR ART ........................................ 16
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`A. U.S. Patent No. 5,768,618 to Erickson et al. (“Erickson”) ................. 16
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`B.
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`Andrew S. Tanenbaum, Computer Networks, 3rd ed.
`(1996) (“Tanenbaum96”) .................................................................... 18
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`VI. CLAIM CONSTRUCTION .......................................................................... 19
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`A.
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`B.
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`“context” .............................................................................................. 20
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`“prepending” and “status information” ............................................... 22
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`VII. LEVEL OF ORDINARY SKILL IN THE ART ........................................... 23
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`VIII. THE CITED REFERENCES DO NOT RENDER THE
`CHALLENGED CLAIMS OBVIOUS ......................................................... 23
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`A.
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`B.
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`C.
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`The Combination Does Not Show or Suggest “Dividing,
`By The Interface Device, The Data Into Segments” (All
`Challenged Claims) ............................................................................. 24
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`The Combination Does Not Show or Suggest
`“transferring status information for the context to the
`interface device during the same operation as
`transferring protocol header information to the interface
`device” (Claim 2) ................................................................................ 33
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`The Combination Does Not Show or Suggest “receiving,
`by the interface device, receive packets that correspond to
`the [context / protocol information], and updating the
`[context / status information] by the interface device to
`account for the receive packets” (Claims 7, 14, and 21) .................... 34
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`D.
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`There Is No Motivation to Combine Erickson and
`Tanenbaum .......................................................................................... 35
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`1.
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`2.
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`3.
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`4.
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`5.
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`6.
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`7.
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`8.
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`Tanenbaum Expressly Teaches Away From a
`Combination Using Erickson .................................................... 35
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`A POSITA Would Not Have Combined
`Tanenbaum With Erickson Because the Two
`References are Incompatible ..................................................... 39
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`Tanenbaum Does Not Include an Express
`Motivation to Combine ............................................................. 42
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`A POSITA Would Not Have Had an Expectation
`of Success in Combining Tanenbaum with
`Erickson .................................................................................... 43
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`Petitioners Mischaracterize Erickson as Being
`Similar to Tanenbaum ............................................................... 45
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`The Complexity of the Subject Matter of Erickson
`and Tanenbaum Weighs Against Combining Them ................ 46
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`Petitioner’s Expert Agreed That Marketplace
`Demands Discouraged Offload ................................................. 49
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`Contrary to Petitioner’s Assertions, Combining
`Erickson with Tanenbaum Would Have Increased
`Complexity, Rather Than Reduced It ....................................... 51
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`(a) Complexity added by the window size,
`acknowledgement, and re-transmission
`inherent in TCP ............................................................... 52
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`(b) Combining Erickson with Tanenbaum
`Would Result in Increased I/O Bus Access,
`Which is Contrary to the Goals of Erickson,
`and the Need For Additional Logic ................................ 54
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`IX. THE STRONG EVIDENCE OF SECONDARY
`CONSIDERATIONS WEIGHS AGAINST OBVIOUSNESS .................... 56
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`1.
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`The Claimed Invention Addresses a Long-felt, Yet
`Unresolved Need in the Art for Accelerated
`Network Communications ........................................................ 56
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`2.
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`3.
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`The Claimed Inventions Were Commercially
`Successful ................................................................................. 58
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`The Claimed Invention Received Praise in the
`Industry ..................................................................................... 59
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`4. Many Others Tried and Failed to Develop the
`Claimed Technology ................................................................. 60
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`5.
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`Experts Were Skeptical of the Claimed Invention
`and Taught Away From It ......................................................... 61
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`X.
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`THE PETITION FAILS TO DISCLOSE ALL REAL PARTIES
`IN INTEREST ............................................................................................... 63
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`XI. THE PETITION PRESENTS SUBSTANTIALLY THE SAME
`PRIOR ART AND ARGUMENTS PREVIOUSLY BEFORE
`THE OFFICE ................................................................................................. 65
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`XII. ALACRITECH RESERVES ITS RIGHTS UNDER THE
`PENDING OIL STATES CASE AT THE UNITED STATES
`SUPREME COURT ...................................................................................... 65
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`XIII. CONCLUSION ............................................................................................. 66
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`TABLE OF AUTHORITIES
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`Page
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`CasesCasesCases Cases
`Belden Inc. v. Berk–Tek LLC,
` 805 F.3d 1064 (Fed. Cir. 2015) ............................................................... 38
`CCS Fitness, Inc. v. Brunswick Corp.
`288, F.3d 1359 (Fed. Cir. 2002) ............................................................... 19
`CFMT, Inc. v. Yieldup Int’l Corp.,
` 349 F.3d 1333 (Fed. Cir. 2003) ......................................................... 28, 35
`Fortinet, Inc. v. Sophos, Inc.,
` IPR 2015-00617 (Aug. 13, 2015) ............................................................ 20
`Garmin Int’l, Inc. v. Patent of Cuozzo Speed Techs. LLC,
` IPR2012-00001 (PTAB Jan. 9, 2013) ..................................................... 28
`Genetics Institute, LLC v. Novartis Vaccines and Diagnostics, Inc.,
` 655 F.3d 1291 (2011)............................................................................... 49
`In re Ethicon, Inc.,
` 844 F.3d 1344 (Fed. Cir. 2017) ............................................................... 30
`In re Gulack,
` 703 F.2d 1381 (Fed. Cir. 1983) ............................................................... 28
`In re Rijckaert,
` 9 F.3d 1531 (Fed. Cir. 1993) ................................................................... 28
`In re Royka,
` 490 F.2d 981 (C.C.P.A. 1974) ................................................................. 28
`KSR Int’l Co. v. Teleflex Inc.,
` 550 U.S. 398 (2007) ................................................................................. 44
`Link Corp. v. Securus Techs., Inc.,
` IPR2014-00785 (PTAB Oct 7, 2015) ...................................................... 28
`Medshape, Inc. v. Cayenne Medical, Inc.,
` IPR2015-00848 (Sept. 14, 2015) ............................................................. 20
`Nautilus, Inc. v. Biosig Instruments, Inc.,
` 134 S. Ct. 2120 (2014) ............................................................................. 22
`Personal Web Technologies, LLC v. Apple, Inc.,
` 848 F.3d 987 (Fed. Cir. 2017) ................................................................. 38
`United States v. Adams,
` 383 U.S. 39 (1966) ................................................................................... 44
`W.L. Gore & Assocs., Inc. v. Garlock, Inc.,
` 721 F.2d 1540 (Fed. Cir. 1983) ............................................................... 30
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`Statutory Authorities
`35 U.S.C. § 112 ............................................................................................. 20
`35 U.S.C. § 311(b) ............................................................................ 20, 30, 31
`35 U.S.C. § 312(a)(2) .................................................................................... 63
`35 U.S.C. § 325(d) ........................................................................................ 65
`
`Rules and Regulations
`37 C.F.R. § 42.6(e) ....................................................................................... 68
`37 C.F.R. § 42.8(b)(1) .................................................................................. 63
`37 C.F.R. § 42.22 .......................................................................................... 66
`37 C.F.R. § 42.23 .......................................................................................... 66
`37 C.F.R. § 42.24 .......................................................................................... 67
`37 C.F.R. § 42.24(b) ..................................................................................... 67
`37 C.F.R. § 42.100(b) ................................................................................... 19
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`PATENT OWNER’S LIST OF EXHIBITS
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`Ex. 2001
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`Not Used
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`Ex. 2002
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`Ex. 2003
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`Ex. 2004
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`Ex. 2005
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`Intel Corporation’s Motion to Intervene, Case No. 2:16-
`cv-00693-JRG-RSP, Dkt. 71 (E.D. Tex., Oct. 31, 2016)
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`Declaration of Christopher Kyriacou, Case No. 2:16-cv-
`00693-JRG-RSP, Dkt. 71-5 (E.D. Tex., Oct. 31, 2016)
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`Jonathan Corbet; Alessandro Rubini; Greg Kroah-
`Hartman (2005), Linux Device Drivers, 3rd edition,
`Chapter 10, “Interrupt Handling”
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`Defendant Dell Inc.’s First Supplemental Responses to
`Plaintiff’s Second Set of Common Interrogatories to
`Defendants and Intervenors (No. 11)
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`Ex. 2006
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`Not Used
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`Ex. 2007
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`Ex. 2008
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`Declaration of Garland Stephens, Case No. 2:16-cv-
`00693-JRG-RSP, Dkt. 71-2 (E.D. Tex., Oct. 31, 2016)
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`Excerpts of Declaration of Mr. Mark R. Lanning
`Regarding Claim Construction, Case No. 2:16-cv-00693-
`JRG-RSP, Dkt. 303-5 (E.D. Tex. Jul. 6, 2017)
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`Ex. 2009
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`Cavium’s Motion to Intervene, Case No. 2:16-cv-00693-
`JRG-RSP, Dkt. 109 (E.D. Tex., Jan. 13. 2017)
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`Ex. 2010
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`Not Used
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`Ex. 2026
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`Declaration of Kevin Almeroth, Ph.D. in Support of
`Patent Owner’s Response to the Petition
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`Ex. 2027
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`Curriculum Vitae of Kevin Almeroth, Ph.D.
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`Ex. 2028
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`Transcript from the Deposition of Robert Horst, Ph.D.
`dated January 25, 2018
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`Ex. 2029
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`Ex. 2030
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`Transcript from the Deposition of Robert Horst, Ph.D.
`dated January 26, 2018
`
`Memorandum Order and Opinion on Claim
`Construction, Case No. 2:16-cv-00693-RWS-RSP,
`Docket 362 (Filed September 21, 2017)
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`Ex. 2031
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`The Architecture of a Gb/s Multimedia Protocol Adapter
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`Ex. 2032
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`A Fast Track Architecture for UDP/IP and TCP/IP
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`Ex. 2033
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`A Communication Architecture for High-speed
`Networking
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`Ex. 2034
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`Server Network Scalability and TCP Offload
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`Ex. 2035
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`Alacritech and NetXen Join Forces to Deliver Solutions
`for Microsoft TCP Chimney Offload Technology
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`Ex. 2036
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`QLogic Licenses Alacritech
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`Ex. 2037
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`Neterion Licenses Alacritech’s Patents
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`Ex. 2038
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`Alacritech Licenses
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`Ex. 2039
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`Ex. 2040
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`An Evaluation of an Attempt at Offloading TCP/IP
`Protocol Processing onto an i960RN-based iNIC
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`Alacritech, Pioneer In Network Acceleration, Unveils
`Appliance To Alleviate Enterprise Storage Woes
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`Ex. 2041
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`TCP offload is a dumb idea whose time has come
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`Ex. 2042
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`TCP/IP Headers (https://nmap.org/book/tcpip-ref.html)
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`Ex. 2043
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`TCP/IP message processing
`(http://www.thegeekstuff.com/2011/11/tcp-ip-
`fundamentals/)
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`Ex. 2300
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`Horst Paper
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`Ex. 2301
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`Listing of Challenged Claims
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`I.
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`INTRODUCTION
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`Patent Owner Alacritech Inc. respectfully submits this Patent Owner
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`Response. Petitioners Intel Corporation and Cavium, Inc. (“Petitioners”) filed
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`respective Petitions for Inter Partes Review (“Petition”) of claims 1-21 of U.S.
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`Patent No. 7,673,072, and the Board instituted proceedings on Ground 1. The
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`challenged claims are not obvious in view of the Erickson and Tanenbaum
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`references relied upon in Ground 1 because the references, alone or in
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`combination, fail to disclose: (1) the “dividing, by the interface device, the data
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`into segments” element present in all the independent claims; (2) the “transferring
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`status information for the context to the interface device during the same operation
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`as transferring protocol header information to the interface device” element of
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`claim 2; (3) and the “receiving, by the interface device, receive packets that
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`correspond to the [context / protocol information], and updating the [context /
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`status information] by the interface device to account for the receive packets”
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`element of claims 7, 14, and 21. Moreover, the Petition fails to prove that there
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`would have been a motivation to combine the references with any expectation of
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`arriving at the claimed subject matter, particularly in view of Tanenbaum teaching
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`away from the use of Erickson’s system for its stated purpose of protocol offload,
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`as well as the evidence of secondary considerations of non-obviousness.
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`II. BACKGROUND OF THE TECHNOLOGY
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`Both in 1997 and today, sending and receiving information over the Internet
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`involves the use of many different protocols that set out the rules for how devices
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`on the Internet can communicate with one another. (Ex. 2026, ¶ 59.) Multiple
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`conceptual models exist for characterizing the interactions between these protocols
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`in the context of the Internet and other telecommunication or computing systems.
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`The Open Systems Interconnection model (or “OSI model”) is one well known
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`example, describing a seven layer stack where a particular layer serves the layer
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`above it and is served by the layers below it. Id. The seven layers of the OSI
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`model are:
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`Layer 7: Application Layer
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`Layer 6: Presentation Layer
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`Layer 5: Session Layer
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`Layer 4: Transport Layer
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`Layer 3: Network Layer
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`Layer 2: Data Link Layer
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`Layer 1: Physical Layer
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`with layer 1 (the Physical Layer) being the lowest layer in the model. Id.
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`The Internet Protocol (or “IP”) is an example of a well-known network
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`(layer 3) protocol. (Id., ¶ 61.) IPv4 was published as RFC 760 in January 1980
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`while its successor IPv6 was published as RFC 2460 in December 1998. Id. The
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`IP protocol describes a set of rules for dividing a message into multiple parts
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`(called “IP packets”) and then transmitting those packets from an IP sender to an
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`IP destination across multiple routers or other links in a computer network. Each
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`packet of information includes an IP address for its destination, analogous to
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`sending a letter through the mail by placing the letter inside an envelope that has
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`the recipient’s postal address printed on it. Id. The format of an IP header is
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`depicted below:
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`(Id.; Ex. 2042)2
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`The Transmission Control Protocol, referred to as “TCP,” is one of the main
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`protocols used to send and receive information over the Internet. (Ex. 2026, ¶ 62.)
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`TCP is well known in the computer networking industry—one early TCP rule set
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`was published as a Request for Comment (or “RFC”) by the Internet Engineering
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`Task Force (“IETF”) in September 1981 (RFC 793). That rule set was based on an
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`even earlier rule set published in December 1974 as RFC 675. TCP is an example
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`of a transport (layer 4) protocol in the OSI model. Id. TCP is responsible for
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`adding reliability and ordering to the stream of network information—for example,
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`the packets of information sent using IP as the network-layer protocol may not
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`arrive at the destination in the same order intended by the sender of the message.
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`Id. TCP sets rules for breaking up and transmitting the message so that the
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`recipient is able to reliably receive and reassemble the message. Another common
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`analogy from the physical world is the example of sending a multi-page letter
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`through the mail by separately numbering each page and mailing it in its own
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`envelope. IP, like the postal service, will route the envelope-like packets to the
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`destination, but TCP (like the numbering of the individual pages) sets the rules to
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`2 This figure accurately depicts an IP header as of October 1997, as supported by
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`the testimony of Dr. Almeroth. (Ex. 2026 at ¶ 61.)
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`allow the recipient to verify that all of the pages have been received and to
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`reassemble the pages in the right order. Id.
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`TCP describes, for example, how two devices on the Internet may establish a
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`connection over which TCP data packets may be communicated between them.
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`(Ex. 2026, ¶ 63.) By way of a negotiation process known as a three-way
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`handshake, such a connection can be established between two nodes, and once that
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`connection establishment phase completes, data transfer can begin. Typically, a
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`TCP connection is managed by a device operating system so that applications such
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`as a web browser or a web server like a CDN caching server can pass data to the
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`operating system’s TCP protocol “stack,” and the operating system will manage
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`transmission of that data to the receiver and will pass received data from the other
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`device up to the application layer. Id. The format of a TCP header is depicted
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`below:
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`(Id.; Ex. 2042.3)
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`Transmitting a message requires processing each of the layers in that
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`protocol stack sequentially so that the message can then be transmitted over the
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`data medium. The receiving computer is also required to process those same
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`layers in reverse until the message is handed off to the appropriate program (e.g., a
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`3 This figure accurately depicts an TCP header as of October 1997, as supported
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`by the testimony of Dr. Almeroth. (Ex. 2026 at ¶ 63.)
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`web server). (Ex. 2026, ¶ 64.) One example of processing a message using
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`TCP/IP is depicted below:
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`(Id.; Ex. 2043.4)
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`Much of this processing is typically handled by the CPU. (Ex. 2026, ¶ 65.)
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`Thus, sending and receiving data over a network can negatively impact the CPU’s
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`4 This figure accurately depicts an example of processing a message using TCP/IP
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`as of October 1997, as supported by the testimony of Dr. Almeroth. (Ex. 2026 at ¶
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`64.)
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`ability to perform other functions, particularly as the volume of data sent or
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`received increases. Id. For the purposes of this case, the manner by which the
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`CPU handles the required protocol processing—i.e., the specific software steps it
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`takes to perform the needed TCP and IP processing—is immaterial. Id. At most, it
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`is sufficient that the CPU does perform or is capable of performing that processing,
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`whether through software included as part of the operating system or through some
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`other means. Id.
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`III. OVERVIEW OF THE ’072 PATENT
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`A. The ’072 Patent Specification
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`The ’072 patent,
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`titled “Fast-path apparatus for
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`transmitting data
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`corresponding to a TCP connection,” describes a novel system for accelerating
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`network processing. In particular, the ’072 Patent discloses a system with “a
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`specialized microprocessor designed for processing network communications,
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`avoiding the delays and pitfalls of conventional software layer processing, such as
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`repeated copying and interrupts to the CPU,” and “freeing the host CPU from most
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`protocol processing and allowing improvements in other task.” Ex. 1001 at 5:44-
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`47, 7:47-49. (Ex. 2026, ¶ 67.)
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`The ’072 patent explains that, at the time of the invention, communications
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`networks were growing “increasingly popular and the information communicated
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`thereby [becoming] increasingly complex and copious” creating increased network
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`protocol processing such that “a large fraction of the processing power of a host
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`CPU may be devoted to controlling protocol processes, diminishing the ability of
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`that CPU to perform other tasks.” Ex. 1001, 5:5-11. The ’072 patent explains that
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`the then-existing standard protocol processing involved too many data moves (id.
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`at 35:1-27), too much processing by the CPU (id. at 35:29-36:3), too many
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`interrupts (id. at 36:4-34), and inefficient use of the peripheral component
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`interconnect (“PCI”) bus (id. at 36:36-61; Ex. 2026, ¶ 67.).
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`The ’072 patent solves these problems with a specialized network interface
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`device (i.e., the INIC) that is capable of performing certain processing normally
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`handled by the host CPU. (Ex. 1001 at 7:41-55.) The claims of the ’072 patent
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`focus on offloading processing associated with the transmission side of the
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`protocol processing—i.e., when a computer transmits or sends data across the
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`network. See id. at 97:30-31 (“to form transmit packets”). The ’072 patent
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`explains, for example, that “[i]n fast-path mode, the host gives raw data to the
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`INIC which it must carve into MSS sized segments, add headers to the data,
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`perform checksums on the segment, and then send it out on the drive.” Id. at
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`38:55-61 (emphasis added). This “carving” process conducted by the INIC is
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`reflected in Claim 1 as well as all other independent claims, which recite “dividing,
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`by the interface device, the data into segments.” Id. at 97:26 (emphasis added).
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`As analyzed herein, the “dividing” step being conducted by “the interface device”
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`is not disclosed by either of the cited references or their combination. (Ex. 2026, ¶
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`68.)
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`Prior to the ’072 patent, “performing multilayered protocol processing on a
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`general-purpose processor” was still “the long-standing practice.” Ex. 1001, 5:28-
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`29. Indeed, many prior artists at the time advocated against the approach taken by
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`the ’072 patent, citing the problems that would be created by attempting to offload
`
`protocol processing for complicated protocols such as TCP/IP, as well as
`
`questioning the benefits that would even be achieved by such offloading. For
`
`example, Petitioners’ Tanenbaum reference explains:
`
`A tempting way to go fast is to build fast network
`
`interfaces in hardware. The difficulty with this strategy
`
`is that unless the protocol is exceedingly simple,
`
`hardware just means a plug-in board with a second CPU
`
`and its own program. To avoid having the network
`
`coprocessor be as expensive as the main CPU, it is often
`
`a slower chip. The consequence of this design is that
`
`much of the time the main (fast) CPU is idle waiting for
`
`the second (slow) CPU to do the critical work. It is a
`
`myth to think that the main CPU has other work to do
`
`while waiting. Furthermore, when two general-purpose
`
`CPUs communicate, race conditions can occur, so
`
`elaborate protocols are needed between
`
`the
`
`two
`
`processors to synchronize them correctly. Usually, the
`
`
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`10
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`Case No. IPR2017-01406
`U.S. Patent No. 7,673,072
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`best approach is to make the protocols simple and have
`
`the main CPU do the work.
`
`Ex. 1006 at 588-89 (emphasis added). The issues caused by prior art approaches to
`
`protocol offloading were also explained in the ’072 patent:
`
`In order to keep the system CPU from having to process
`
`the packet headers or checksum the packet, we must
`
`perform this task on the INIC. This is a daunting task.
`
`There are more than 20,000 lines of C code that make up
`
`the FreeBSD TCP/IP protocol stack. Clearly this is more
`
`code
`
`than could be efficiently handled by a
`
`competitively priced network card. Furthermore, as
`
`noted above, the TCP/IP protocol stack is complicated
`
`enough to consume a 200 MHz Pentium-Pro.
`
`Ex. 1001, 37:18-25 (emphasis added); Ex. 2026, ¶ 69.
`
`In fact, even Petitioners’ expert, Dr. Horst, wrote in an article published in
`
`2001 that “the current economic justification for hardware acceleration is poor
`
`given the low cost of host CPU cycles. The I/O load for many applications is
`
`dominated by disk latency, not transfer rate, and hardware protocol accelerators
`
`have little effect on the I/O performance in these environments.” (Ex. 2300,
`
`ABSTRACT.)
`
` Accordingly, Dr. Horst’s own contemporaneous opinions
`
`advocated against the use of a separate processor for protocol processing.
`
`
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`11
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`Case No. IPR2017-01406
`U.S. Patent No. 7,673,072
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`Despite this industry skepticism, the ’072 inventors came up with the
`
`claimed arrangement, which allows
`
`for enhanced network and system
`
`performance, a stark reduction or elimination of unnecessary processing by the
`
`host CPU, faster data throughput, increased system stability, and an overall better
`
`user experience. Instead of using an unspecified processor on a network card to
`
`carry out some protocol software, the ’072 patent discloses “a specialized
`
`microprocessor designed for processing network communications.” Ex. 1001,
`
`5:44-47. This specialized microprocessor, residing in an intelligent network
`
`interface card (INIC), is described, for example, in Fig. 13 and corresponding
`
`embodiments described in the ’072 patent. (Ex. 2026, ¶ 70.)
`
`
`
`12
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`Case No. IPR2017-01406
`U.S. Patent No. 7,673,072
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`The ’072 patent explains:
`
`
`
`FIG. 13 provides a simplified diagram of the INIC 200,
`
`which combines the functions of a network interface
`
`controller and a protocol processor in a single ASIC chip
`
`400. . . . The MAC units 402, 404, 406 and 408 are each
`
`connected to a transmit and receive sequencer, XMT &
`
`RCV-A 418, XMT & RCV-B 420, XMT & RCV-C 422
`
`
`
`13
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`Case No. IPR2017-01406
`U.S. Patent No. 7,673,072
`
`and XMT & RCV-D 424, by wires 410, 412, 414 and
`
`416, respectively. Each of the transmit and receive
`
`sequencers can perform several protocol processing
`
`steps on the fly as message frames pass through that
`
`sequencer. In combination with the MAC units, the
`
`transmit and receive sequencers 418-422 can compile the
`
`packet status for the data link, network, transport,
`
`session and,
`
`if appropriate, presentation and
`
`application
`
`layer protocols
`
`in hardware, greatly
`
`reducing
`
`the
`
`time for such protocol processing
`
`compared to conventional sequential software engines.
`
`Ex. 1001 at 18:25-27, 62-67, and 19:1-7 (emphasis added). In other words, the
`
`’072 specification discloses a particular hardware solution that reduces processing
`
`time theretofore unknown in the art. (Ex. 2026, ¶ 70.)
`
`B.
`
`The ’072 Patent Claims
`
`The ’072 Patent includes 21 claims. All 21 claims are challenged in the
`
`Petition. Claims 1, 9, and 15 are independent claims and each recites “dividing, by
`
`the interface device, the data into segments.” Claims 2-8, 10-14, and 16-21 depend
`
`on the independent claims. All of the challenged claims are reproduced in Ex.
`
`2031, with labeling for convenience. Independent claim 1 is reproduced below:
`
`Claim 1 of the ’072 Patent
`
`Label
`
`Limitation
`
`
`
`14
`
`

`

`Case No. IPR2017-01406
`U.S. Patent No. 7,673,072
`
`A method comprising:
`
`establishing, at a host computer, a transport layer connection,
`including creating a context that includes protocol header information
`for the connection;
`transferring the protocol header information to an interface device;
`
`transferring data from the network host to the interface device, after
`transferring the protocol header information to the interface device;
`dividing, by the interface device, the data into segments;
`
`creating headers for the segments, by the interface device, from a
`template header containing the protocol header information; and
`prepending the headers to the segments to form transmit packets.
`
`1.p
`
`1.1
`
`1.2
`
`1.3
`
`1.4
`
`1.5
`
`1.6
`
`
`
`IV. PROSECUTION HISTORY OF THE ’072 PATENT
`
`The ’072 patent was filed as Application No. 11/821,820 on June 25, 2007
`
`and issued March 2, 2010. It is a continuation of U.S. Application No. 10/260,112
`
`filed Sep. 27, 2002, which in turn is a continuation of U.S. Application No.
`
`10/092,967 filed Mar. 6, 2002, which in turn is a continuation-in-part of U.S.
`
`Application No. 10/023,240 filed Dec. 17, 2001, which in turn is a continuation-in-
`
`part of U.S. Application No. 09/464,283 filed Dec. 15, 1999, which in turn is a
`
`continuation-in-part of U.S. Application No. 09/439,603 filed Nov. 12, 1999,
`
`which in turn is a continuation-in-part of U.S. Application No. 09/067,544, filed
`
`Apr. 27, 1998, which in turn claims the benefit of Provisional Application No.
`
`
`
`15
`
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`

`Case No. IPR2017-01406
`U.S. Patent No. 7,673,072
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`60/061,809 filed Oct. 14, 1997. The ’072 patent was allowed over the cited art,
`
`including the Erickson and Tanenbaum references, in a first action allowance.
`
`V. OVERVIEW OF THE ASSERTED PRIOR ART
`
`As described above, the instituted Ground relies on a combination of the
`
`Erickson and Tanenbaum references as alleged § 103(a) prior art to all Challenged
`
`Claims. However, as discussed in detail below, Erickson and Tanenbaum do not,
`
`alone or in combination, teach or fairly suggest all the limitations recited in the
`
`Challenged Claims, nor was there any motivation to combine these references.
`
`Tellingly, both Erickson and Tanenbaum were already considered by the Patent
`
`Office during the original prosecution of the ’072 patent, and the Challenged
`
`Claims were allowed over these references.
`
`A. U.S. Patent No. 5,768,618 to Erickson et al. (“Erickson”)
`
`Erickson appears on the face of the ’072 patent under “References Cited”
`
`and was initialed by the Examiner in an Information Disclosure Statement (IDS)
`
`dated October 26, 2009. Ex. 1002.303; see also Ex. 1001.002. Erickson was
`
`therefore already considered by the Examiner during the prosecution of the ’072
`
`patent, which was found to be allowable over Erickson. (Ex. 2026, ¶ 77.)
`
`Erickson discloses an input/output (I/O) device connected to a computer to
`
`facilitate fast I/O data transfers. (Ex. 1005 at Abstract.) An address space for the
`
`I/O device is created in the virtual memory of the computer, wherein the address
`
`
`
`16
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`Case No. IPR2017-01406
`U.S. Patent No. 7,673,072
`
`space comprises virtual registers that are used to directly control the I/O device.
`
`Control registers and/or memory of the I/O device are mapped into the virtual
`
`address space, and the virtual address space is backed by control registers and/or
`
`memory on the I/O device. When the I/O device detects writes to the address
`
`space, a pre-defined sequence of actions can be triggered in the I/O device by
`
`programming specified values into the data written into the mapped virtual address
`
`space. (Ex. 2026, ¶ 78.)
`
`Figure 7 of Erickson shows a UDP datagram header “template” that resides
`
`in the I/O adapter’s memory. (Id. at 7:39-46.) A user provides the starting

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