(12) United States Patent
`(10) Patent N0.:
`US 6,334,153 132
`
`Boucher et al.
`(45) Date of Patent:
`*Dec. 25, 2001
`
`U5006334153B2
`
`(54) PASSING A COMMUNICATION CONTROL
`BLOCK FROM HOST TO A LOCAL DEVICE
`SUCH THAT A MESSAGE IS PROCESSED
`
`5,163,131
`5,212,778
`5,280,477
`
`11/1992 Row et al.
`........................... 395/200
`5/1993 Dally et al.
`395/400
`
`1/1994 Trapp .................................. 370/851
`
`ON THE DEVICE
`
`(75)
`
`Inventors: Laurence B. Boucher, Saratoga;
`Stephen E. J. Blightman, San Jose;
`Peter K. Craft, San Francisco; David
`A-Higgen, SaratOga; Clive M-
`PDIIDI‘lck, San Jose; Daryl D. Starr,
`Milpitas, all of CA (US)
`
`(73) Assignee: Alacritech, Inc., San Jose, CA (US)
`.
`*
`.
`.
`.
`.
`.
`) Notice.
`Subjectto any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(
`
`Tlhis patent is subject to a terminal dis-
`C aimer.
`
`(21) Appl. No.: 09/748,936
`
`(22)
`
`Filed:
`
`Dec. 26, 2000
`
`Related US. Application Data
`
`(63)
`
`(60)
`
`fgniiglggtion ofPappllécéité0£1417\l<()).689/439,}?03, filed 9n NOV.
`,
`, now at.
`0.
`,
`,
`, w 10
`is a continuation
`of application No. 09/067,544, filed on Apr. 27, 1998, now
`Pat. No. 6,226,680.
`Provisional application No. 60/061,809, filed on Oct. 14,
`1997.
`
`Int. Cl.7 ........................... G06F 15/16; G06F 15/173
`(51)
`(52) US. Cl.
`........................... 709/230; 709/250; 709/238
`(58) Field of Search ..................................... 709/250 230
`709/236 238 243 228 245’
`’
`’
`’
`’
`
`(56)
`
`References Cited
`
`US. PATENT DOCUMENTS
`12/1992 Johnson et al
`2/1991 Davis et al.
`10/1991 Hirata et al.
`3/1992 Ward et al.
`
`364/200
`
`364/900
`......................... 364/900
`............................ 365/78
`
`4 336 538
`4:991:133
`5,056,058
`5,097,442
`
`(List continued on next page.)
`
`FOREIGN PATENT DOCUMENTS
`
`PCT/E48994:
`WO98/19412
`WO98/50852
`WO99/04343
`
`11/1998 (EP) .
`5/1998 (W0).
`11/1998 (W0) .
`1/1999 (W0) .
`
`OTHER PUBLICATIONS
`Internet pages entitled: DART Fast Application—Level Net-
`working Via Data—Copy Avoidance, by Robert J. Walsh,
`printed Jun. 3, 1999.
`
`(List continued on next page.)
`Primary Examiner—Zarni Maung
`y
`g
`74 Attorne , A em, or Firm—Mark Lauer; T. Lester
`Wallace
`
`(57)
`
`ABSTRACT
`
`A system for protocol processing in a computer network has
`an intelligent network interface card (INIC) or communica-
`tion processing device (CPD) associated with a host com-
`puter. The INIC provides a fast-path that avoids protocol
`'
`'_
`prOCCSSIng for most large. “11.11“ paCket messages, greatly
`accelerating data communication. The INIC also aSSists the
`hOSt for those message PaCketS that are Chosen for process-
`ing by host software layers. A communication control block
`for a message is defined that allows DMA controllers of the
`INIC to move data, free of headerS, directly to or from a
`destination or source in the hOSt- The COHtCXt is stored in the
`INIC as a communication control block (CCB) that can be
`passed back to the host for message processing by the host.
`The INIC contains specialized hardware circuits that are
`much faster at their specific tasks than a general purpose
`CPU. A preferred embodiment includes a trio of pipelined
`processors with separate processors devoted to transmit,
`receive and management processing, with full duplex com-
`munication for four faSt Ethernet “Odes
`
`2 Claims, 82 Drawing Sheets
`
`
`
`INTEL EX. 1259.001
`
`INTEL Ex. 1259.001
`
`

`

`US 6,334,153 132
`
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`5,289,580
`5,303,344
`5,412,782
`5,448,566
`5,485,579
`5,506,966
`5,511,169
`5,548,730
`5,566,170
`5,588,121
`5,590,328
`5,592,622
`5,629,933
`5,634,099
`5,634,127
`5,642,482
`5,664,114
`5,671,355
`5,678,060
`5,692,130
`5,699,317
`5,701,434
`5,749,095
`5,751,715
`5,752,078
`5,758,084
`5,758,089
`5,758,186
`5,758,194
`5,771,349
`5,790,804
`5,794,061
`5,802,580
`5,812,775
`5,815,646
`5,878,225
`5,930,830
`5,991,299
`6,009,478
`6,034,963
`6,061,368
`6,247,060 *
`
`
`
`..
`
`.....
`
`........................... 395/275
`2/1994 Latif et al.
`.. 395/200
`4/1994 Yokoyama et al.
`.
`
`5/1995 Hausman et al.
`.. 395/250
`..... 370/94.1
`..
`9/1995 Richter et al.
`
`. 395/200.12
`1/1996 Hitz et al.
`
`4/1996 Ban ............... 395/250
`4/1996 Suda ............
`395/280
`8/1996 Young et al.
`.. 395/280
`10/1996 Bakke et al.
`........ 370/60
`
`. 395/200.15
`12/1996 Reddin et al.
`
`.......... 395/675
`12/1996 Seno et al.
`
`1/1997 Isfeld et al.
`. 395/200.02
`
`5/1997 Delp et al.
`...... 370/411
`5/1997 Andrews et al.
`. 395/200.07
`
`...... 395/680
`5/1997 Cloud et al.
`6/1997 Pardillos .........
`395/200.2
`
`.............. 395/200.64
`9/1997 Krech, Jr. et al.
`9/1997 Collins .............................. 395/200.2
`10/1997 Yakoyama et al
`...... 709/212
`11/1997 Shobu et al.
`..... 395/200.12
`..
`12/1997 Sartore et al.
`. 395/230.06
`12/1997 Nakagawa ............................ 395/484
`5/1998 Hagersten ............................ 711/141
`5/1998 Chan et al.
`.
`.. 370/455
`
`...... 395/827
`5/1998 Delp et al.
`5/1998 Silverstein et al.
`.
`..... 395/200.58
`
`..... 395/200.64
`5/1998 Gentry et al.
`
`...... 395/831
`5/1998 Hamilton et al.
`5/1998 Kuzma ..................... 395/886
`
`. 395/188.01
`6/1998 Picazo Jr., et al
`
`8/1998 Osborne .................. 395/200.75
`
`..... 395/800.01
`8/1998 Hansen et al.
`..
`
`9/1998 McAlpice ................. 711/149
`
`. 395/200.43
`9/1998 Van Seters et al.
`
`...... 395/163
`9/1998 Purcell et al.
`3/1999 Bilansky et al.
`. 395/200.57
`7/1999 Mendelson et al.
`.. 711/171
`11/1999 Radogna et al.
`.. 370/392
`12/1999 Panner et al.
`...... 710/5
`.
`3/2000 Minami et al.
`.. 370/401
`5/2000 Hitzelberger ......................... 370/537
`6/2001 Boucher et al.
`..................... 709/238
`OTHER PUBLICATIONS
`
`
`
`
`
`
`Jato Technologies Internet pages entitled: Network Accel-
`erator Chip Architecture, twelve—slide presentation, printed
`Aug. 19, 1998.
`EETIMES article entitled: Enterprise System Uses Flexible
`Spec, by Christopher Harrer and Pauline Shulman, dated
`Aug. 10, 1998, Issue 1020, printed Nov. 25, 1998.
`Internet pages entitled: iReady About Us and iReady Prod-
`ucts, printed Nov. 25, 1998.
`Internet pages entitled: Smart Ethernet Network Interface
`Card, with Berend Ozceri is developing, printed Nov. 25,
`1998.
`
`Internet pages entitled : Hardware Assisted Protocol Pro-
`cessing, which Eugene Feinberg is working on, printed Nov.
`25, 1998.
`Internet pages of XaQti Corporation entitled: Giga Power
`Protocol Processor Product Preview, printed Nov. 25, 1998.
`Internet pages of Xpoint Technologies www.Xp0int.c0m
`web site (5 pages), printed Dec. 19, 1997.
`Internet pages relating to iReady Corporation and the iReady
`Internet Tuner Module, printed Nov. 2, 1998.
`Internet pages entitled: Asante and 100BASE—T Fast Eth-
`ernet, printed May 27, 1997.
`Internet pages entitled: A Guide to the Paragon XP/S—A7
`Supercomputer at Indiana University, printed Dec. 21, 1998.
`60/053,240 (US. Provisional Application), by Jolitz et al.
`(listed filing date Jul. 18, 1997).
`Zilog Product Brief entitled “Z85C30 CMOS SCC Serial
`Communication Controller”, Zilog Inc., 3 pages (1997).
`Richard Stevens, “TCP/IP Illustrated, vol. 1, The Protocols”,
`pp. 325—326 (1994).
`Andrew Tanenbaum, “Computer Networks”, Third Edition,
`ISBN 0—13—349945—6, entire book (1996).
`Internet pages entitled: Northridge/Southbridge vs.
`Hub Architecture, 4 pages, printed Feb. 19, 2001.
`Gigabit Ethernet Technical Brief, Achieving End—to—End
`Performance. Alteon Networks, Inc., First Edition, Sept.
`1996.
`
`Intel
`
`VT8501 Apollo MVP4 Documentation, VIA Technologies,
`Inc., pp. i—iv, 1—11, cover and copyright page, revision 1.3
`(Feb. 1, 2000).
`Internet pages directed to; Technical Brief on Alteon Eth-
`ernet Gigabit NIC technology, www.czlteoncom, 14 pages,
`printed Mar. 15, 1997.
`
`Internet pages of InterProphet entitled: Frequently Asked
`Questions, by Lynne Jolitz, printed Jun. 14, 1999.
`Internet pages entitled: Technical White Paper—Xpoints
`Disk—to—LAN Acceleration Solution for Windows NT
`
`Server, printed Jun. 5, 1997.
`
`* cited by examiner
`
`INTEL EX. 1259.002
`
`INTEL Ex. 1259.002
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 1 0f 82
`
`US 6,334,153 B2
`
`
`
`50
`
`CONTEXT
`
`UPPER
`LAYER
`
`UPPER LAYER
`INTERFACE
`
`TRANSPORT
`
`STORAGE
`
`
`
`35
`
`
`
`
`
`
`
`
`
`
`
`
`
`NETWORK
`
`
`
`DATA LINK
`
`56
`
`58
`
`INIC/CPD
`
`INTEL EX. 1259.003
`
`INTEL Ex. 1259.003
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 2 0f 82
`
`US 6,334,153 B2
`
`RECEIVE PACKET
`FROM NETWORK
`BY CPD
`
`VALIDATE PACKET,
`SUMMARIZE
`HEADERS
`
`59
`
`
`FAST PATH
`
`
`CANDIDATE?
`
`
`YES
`
`47
`
`57
`
`NO
`
`SEND PACKET TO
`STACK FOR SLOW-
`PATH PROCESSING
`
`61
`
`65
`
`67
`
`53
`
`CACHE
`
`
`MATCH
`N0
`CCB IN
`WITH CCB?
`CPD
`
`
`SEND PACKET TO
`STACK FOR SLOW-
`PATH PROCESSING
`
`
`
`51
`
`
`
` SEND TO
`
`DESTINATION
`IN HOST VIA
`
`FAST-PATH
`
`CREATE CCB
`FOR MESSAGE
`
`FIG. 3
`
`INTEL EX. 1259.004
`
`INTEL Ex. 1259.004
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 3 0f 82
`
`US 6,334,153 B2
`
`
`
`INTEL EX. 1259.005
`
`INTEL Ex. 1259.005
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 4 0f 82
`
`US 6,334,153 B2
`
`
`
`152
`L"
`F ——————— 'L ------ 'I
`
`”SWAT?“
`
`
`1,50
`159
`166
`
`164
`r ......... 1 ..........
`
`
`
`
`170
`PROCESSOR
`S
`162
`
`
`171
`
`HARDWARE LOGIC
`
`
`
`
`
`i
`SOURCE/DEST
`APPLICATION
`TRANSPORT
`I5I
`NETWORK
`IEI
`:l
`
`INTEL EX. 1259.006
`
`INTEL Ex. 1259.006
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 5 0f 82
`
`US 6,334,153 B2
`
`MEDIA ACCESS
`CONTROLLER
`
`ASSEMBLY
`REGISTER
`
`FLY BY
`SEQUENCER
`
`MULTIPLEXOR
`
`
`1 82
`
`
` SRAM
`CONTROL
`
`
`
`
`
`
`
`
`PACKET
`CONTROL
`
`
`SEQUENCER
`
`
`
`
`
`
`DRAM CONTROL
`
`FIG. 7
`
`INTEL EX. 1259.007
`
`INTEL Ex. 1259.007
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 6 0f 82
`
`US 6,334,153 B2
`
`174
`
`176
`
`178
`
`
`PACKET
`CONTROL
`fis§1§4F§g
`
`
`
`
`
` MAC
`
`NETWORK
`SEQUENCER
`
`
`
`
`SEQUENCER
`813mm;
`
`
`
`
`
`TRANSPORT
`
`
`813ng
`
`
`
`SESSION
`SEQUENCER
`
`MULTIPLEXOR
`
`
`
`FIG. 8
`
`INTEL EX. 1259.008
`
`INTEL Ex. 1259.008
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 7 0f 82
`
`US 6,334,153 B2
`
`
`
`,r ------------------- 290 230 264 270
`
`
`
`
`
`PROCESSOR I
`HARDWARE LOGIC 4—
`HARDWARE LOGIC 3
`HARDWARE LOGIC2
`
`
`I
`_l
`
`
`I
`NETWORK
`
`HARDWARE LOGIC1| _|
`
`
`
`
`
`
`
`
`
`\
`I
`
`202
`
`332
`
`TDI USERS
`
`''''''''
`380
`
`TDI FILTER DRIVER
`& UPPER LAYER INTERFACE
`
`
`
`
`
`"""""
`358
`
`355
`
`350
`
`360
`
`370
`
`366
`
`377
`
`
`
`FIG. 11
`
`INTEL EX. 1259.009
`
`INTEL Ex. 1259.009
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 8 0f 82
`
`US 6,334,153 B2
`
` TRANSPORT
`
`
`
`
`FIG. 10
`
`INTEL EX. 1259.010
`
`INTEL Ex. 1259.010
`
`

`

`US. Patent
`
`D
`
`NNN
`
`0
`
`m,:N2cs
`
`1amam
`
`M8N%SN
`
`US 6,334,153 132
`
`27:
`
`SN
`
`o2
`
`l'"""-"""' """""""'"""'lI
`
`IIIIIIIII IIIIIIIIIII J
`
`anE.EHZmEU
`
`HaH.
`
`L_.7____ __ ___ _ _ ___ ___ ___
`ll
`02
`02
`m2
`#8
`mg
`
`wE
`
`I
`
`o2
`
`52
`
`INTEL EX. 1259.011
`
`INTEL Ex. 1259.011
`
`

`

`210
`
`SuU_r...........Juu_._____...__2mHmm_Wn0uwummAmmmmHSumuusunWn_u1Immmu2,_n5mma“.mRu"A:e_OS_1Duwmm"“ISMCuo_FCOmm_uGWRm\:Pu_M4uI_.unF"fl.L
`B.............................3...........................................
`6.,AMMmomm3,_mmm2
`
`
`4
`
`US. Patent
`
`2
`
`L
`
`INTEL EX. 1259.012
`
`INTEL Ex. 1259.012
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 11 0f 82
`
`US 6,334,153 B2
`
`,— __________
`
`---
`
`
`
`
` RAM FILE
`REGISTER
`
`INSTRUCTigIEIDDECODER
`
`OPERAND MULTIPLEXER
`
`
`
`THIRD REGISTER SET
`
`
`
`
`INTEL EX. 1259.013
`
`INTEL Ex. 1259.013
`
`

`

`US. Patent
`
`m.D
`
`.5,
`
`nmmm.
`
`US 6,334,153 132
`
`
`
`2~533%0mm008mmm@2mevafimH55:«SE25mag95
`
`Du?
`
`moo
`
`mmé3%_EB:
`_8%x833A\\
`”a?
`
`mom
`
`m3flflm
`
`N3,
`
`Q<OADadamuffinQCain
`
`5E052b52b0mm
`
`53053015:0
`
`Q<OAQ<OAExamuh,-ofi
`
`+K
`
`”3m33movmmmm
`
`BE2,;
`
`.................................magma
`
`IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII—o
`
`mmmm
`mamam
`
`ommmeow
`
`EonSon
`
`man?man?
`
`INTEL EX. 1259.014
`
`INTEL Ex. 1259.014
`
`
`
`

`

`US. Patent
`
`3,
`
`2B
`
`Mw:m3_u$mequ
`nzémmo"wRmoz<"%mmooomo
`225252"ES"38mmmmmmm.
`”5%~53m5_mEmmomSonSonme2m“D57:6E"
`
`UU
`
`mmHmHOm—m
`
`mSE32M
`
`L.
`
`3On.m205Mo:
`
`
`
`6IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII."mMamamam0%amamam3%gm9%asEm3%dab860gm;Emmo803550m
`
`INTEL EX. 1259.015
`
`INTEL Ex. 1259.015
`
`

`

`US. Patent
`
`US 6,334,153 132
`
`mmama65m8#5E”5&3#552Emma80SoEb
`
`21.8me228:095SE9meDiB<Ba“mwsu“I.§--§mmESmozéoxm3,3mu,33M02;WBEmE"2mDn
`
`yyryyryyrryg
`
`J
`
`
`
`2%m..................................................................................Hugo
`
`02.UHm
`
`INTEL EX. 1259.016
`
`INTEL Ex. 1259.016
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 15 0f 82
`
`US 6,334,153 B2
`
`
`
`
`
`
`
`
`TCP
`I
`
`
`
`EH
`
`
`
`
`CLIENT
`
`
`
`FAST-PATH
`
`TDI
`
`SLOW-PATH
`
`INIC
`
`NetBIOS
`
`TCP
`
`P
`
`C")
`
`PHYSICAL
`
`II..-
`
`
`_
`
`
`Ethernet
`PCI
`
`FIG. 16
`
`Header buffer descriptors
`
`Header buffers
`
`Data buffers
`
`Headers
`(fast-path)
`
` TCP/SMB
`
`DATA
`buffer handle
`(slow-path)
`
`INTEL EX. 1259.017
`
`INTEL Ex. 1259.017
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 16 of 82
`
`US 6,334,153 B2
`
`Command buffers
`
`Response
`buffer queue
`
`Command
`buffer queue
`
`'
`
`
`
`
`
`Command
`buffer handle
`
`identifier
`
`Command
`buffer handle
`
`identifier
`
`buffer handle
`
`identifier
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 18
`
`
`
`
`
`
`
`
`
`Command
`buffer handle
`
`buffer handle
`
`Command
`buffer handle
`
`
`
`
`
`INTEL EX. 1259.018
`
`INTEL Ex. 1259.018
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 17 0f 82
`
`US 6,334,153 B2
`
`RCV
`XMT
`
`RMISS
`
`Error bits are sent
`RCV has occured.
`Command has been completed
`
`RCV drop occured due to no buffers
`
`FIG. 19
`
`ISR
`IMR
`HBAR
`DBHR
`
`0x0
`0x4
`0x8
`OXC
`
`Interrupt Status
`Interrupt Mask
`Header Buffer Address
`Data Buffer Handle
`
`Data Buffer Address
`0x10
`DBAR
`Command Buffer Address XMTO
`0x14
`CBARO
`Command Buffer Address XMTl
`0x18
`CBARl
`Command Buffer Address XMT2
`OXIC
`CBAR2
`Command Buffer Address XMT3
`0x20
`CBAR3
`Command Buffer Address RCV
`0x24
`CBAR4
`Response Buffer Address
`0x28
`RBAR
`e______flr_______4
`
`FIG. 20
`
`INTEL EX. 1259.019
`
`INTEL Ex. 1259.019
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 18 0f 82
`
`US 6,334,153 B2
`
`
`
`Iface
`
`ifaddr
`
`sockaddr_dl
`
`00:60:97:DB:9B:A6
`
`
`
`
`
`sockaddr_in
`
`192.100.1.2
`
`INTEL EX. 1259.020
`
`IlIIIII
`
`m:
`II
`
`IIIIIII
`
`aIpco
`
`INTEL Ex. 1259.020
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 19 of 82
`
`US 6,334,153 B2
`
`Filter Driver
`
`
`
`
`Microsoft
`TCP/1P
`Driver
`
`
`
`FIG. 23
`
`Buffer Desc
`
`Buffer Desc
`
`
`
`
`
`
`
`
`
`
`
`
`
`Buffer Desc
`
`
`
`Example of incoming TCP pkt
`
`Example of incoming ARP Frame
`
`FIG. 24
`
`FIG. 25
`
`INTEL EX. 1259.021
`
`INTEL Ex. 1259.021
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 20 0f 82
`
`US 6,334,153 132
`
`o
`
`”8%H863
`
`it"
`
`8%«86$
`
`«an
`
`$5
`
`ExamlI8%swam
`
`I%
`
`vampmaafl
`
`53-2558e
`
`53-meQB
`
`Dom.UHL
`
`mom.UHm
`
`<©N.UHm
`
`INTEL EX. 1259.022
`
`Homwsm
`
`Sam
`
`swam
`
`Howmsm
`
`893m
`
`sham
`
`8%swam
`
`“863
`
`$3
`
`593m
`
`swam
`
`INTEL Ex. 1259.022
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 21 0f 82
`
`US 6,334,153 B2
`
`
`
`Command
`Buffer
`
`
`
`
` Buffer
`
`Desc
`
`INTEL EX. 1259.023
`
`INTEL Ex. 1259.023
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 22 0f 82
`
`US 6,334,153 B2
`
`
`
`FIG. 29
`
`SRAM requirements for the Receive and Transmit engines:
`
`TCB buffers
`Header buffers
`TCB hash index
`Timers
`DRAM Fifo queues
`
`256 bytes* 16
`128 bytes* 16
`16 bytes* 256
`
`128 bytes* 16
`
`4096
`2048
`4096
`128
`2048
`~ 12K bytes
`
`L_________\F—_—————J
`
`FIG. 30
`
`INTEL EX. 1259.024
`
`INTEL Ex. 1259.024
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 23 of 82
`
`US 6,334,153 B2
`
`Summary of the main loop of Receive:
`
`forever
`
`{
`
`while there are any Receive events
`if (a new event)
`{
`if (no new context available)
`ignore the event;
`
`{
`
`} c
`
`all appropriate event handler to service the event;
`this may make a waiting process runnable or set up
`a new process to be run (get free context, hddr buffer,
`TCB buffer, set the context up).
`
`} w
`
`hile any process contexts are runable {
`run them by jumping to the start/resume address;
`if (process complete)
`free the context;
`
`} L
`
`_________W_________J
`
`FIG. 31
`
`INTEL EX. 1259.025
`
`INTEL Ex. 1259.025
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 24 of 82
`
`US 6,334,153 B2
`
`0
`
`
`
`
`
`
`Format of the SMB header of an SMB frame:
`
`31
`
`
`
`FLAGS
`
`
`
`TYPE
`
`0er
`
`COM
`
`<—
`
`LENGTH
`
`—*
`
`ERR--
`
`REB/FLG
`
`Reserved
`
`PID
`
`MID
`
`WW 1
`
`__
`
`.
`_rved
`TID
`
`UID
`
`WCT
`
`
`
`
`
`NetBIOS header
`
`SMB header
`
`BCC
`
`Notes (interesting fields):
`LENGTH
`17 bit Length of SMB message (0 - 128K)
`COM
`SMB command
`WCT
`Count (16 bit) of parameter words in VWV [ ]
`VWV
`Variable number of parameter words
`BCC
`Bytes of data following
`
`INTEL EX. 1259.026
`
`INTEL Ex. 1259.026
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 25 0f 82
`
`US 6,334,153 B2
`
`Summary of the main loop of Transmit:
`
`forever
`
`{
`
`while there are any Transmit events
`if (a new event)
`{
`if (no new context available)
`ignore the event;
`
`{
`
`} c
`
`all appropriate event handler to service the event;
`this may make a waiting process runnable or set up
`a new process to be run (get free context, hddr buffer,
`TCB buffer, set the context up).
`
`} w
`
`hile any process contexts are runable {
`run them by jumping to the start/resume address;
`if (process complete)
`free the context;
`
`} \
`
`_______W_#_____J
`
`FIG. 33
`
`INTEL EX. 1259.027
`
`INTEL Ex. 1259.027
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 26 of 82
`
`US 6,334,153 B2
`
`Bit 22 -
`
`Bit 31 - 24 Byte enable 7 - 0. Only the low order four bits are
`valid for 32 bit addressing mode.
`Bit 23 - 0 Memory access
`1 Configuration access
`0 Read (to Host)
`1 Write (to Host)
`Bit 21 - 1 Data Valid
`Bit 20 - 16 Reserved
`Bit 15 - 0 Address
`
`\______flr_________4
`
`FIG. 34
`
`Configuration Space 1
`
`SRAM Address Offset
`
`00
`04
`08
`DC
`10
`3C
`
`Configuration Space 2
`
`00
`04
`08
`0C
`10
`3C
`
`00
`04
`08
`DC
`10
`14
`
`00
`18
`08
`1C
`20
`24
`
`,
`
`All other reads to configuration space will return 00.
`
`,
`
`FIG. 3 5
`
`INTEL EX. 1259.028
`
`INTEL Ex. 1259.028
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 27 of 82
`
`US 6,334,153 B2
`
`1/0 accesses are not enabled
`Bit 0 - O
`Bit 1 - 1 Memory accesses are enabled
`Bit 2 - 1 Bus master is enabled
`Bit 3 - 0
`Special Cycle is not enabled
`Bit 4 - 1 Memory Write and Invalidate is enabled
`Bit 5 - 0 VGA palette snooping is not enabled
`Bit 6 - 1
`Parity checking is enabled
`Bit 7 - 0 Address data stepping is not enabled
`Bit 8 - SERR# is enabled
`Bit 9 - 0 Fast back to back is not enabled
`
`FIG. 36
`
`Bit 5 - l
`
`66 MHz capable is enabled. This bit will be set if the INIC
`Detects the system running at 66 MHz on reset
`User Definable Features is not enabled
`Bit 6 - 0
`Fast Back-to-Back slave transfers enabled
`Bit 7 - 1
`Parity Error enabled - This bit is initialized to 0
`Bit 8 - 1
`Bit 9,10 - 00 - Fast device select will be set if we are at 33 MHz
`01 - Medium device select will be set if we are at 66 MHz
`Bit 11 - 1 Target Abort is implemented. Initialized to 0.
`Bit 12 - 1 Target Abort is implemented. Initialized to 0.
`Bit 13 - 1 Master Abort is implemented. Initialized to 0.
`Bit 14 - l
`SERR# is implemented. Initialized to 0.
`Bit 15 - 1
`Parity error is implemented. Initialized to 0.
`
`FIG. 37
`
`INTEL EX. 1259.029
`
`INTEL Ex. 1259.029
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 28 0f 82
`
`US 6,334,153 B2
`
`MIIA
`
`MIIB
`
`MIIC
`
`MIID
`
`thA
`&
`Rch
`Seq
`
`thB
`&
`Rch
`Seq
`
`thC
`&
`Rch
`Seq
`
`thD
`&
`Rch
`Seq
`
`REG FILE
`8K1 WCS
`1K1 ROM
`
`EXTERNAL
`MEMORY
`BUS
`
`”FROG
`
`1
`
`128 Sram
`goUE
`MA Ctrl
`
`EXTERNAL
`MEMORY Ctrl
`
`PCI BUS
`INTERFACE UNIT
`
`PCI BUS
`
`FIG. 38
`
`INTEL EX. 1259.030
`
`INTEL Ex. 1259.030
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 29 0f 82
`
`US 6,334,153 B2
`
`MODULE
`
`
`DESCR
`
`
`SPEED
`
`AREA
`
`4.37 ns n0m.,
`6.40 ns n0m.,
`3.50 ns n0m.,
`5.00 ns n0m.,
`6.10 ns n0m.,
`
`1Kx128 sport,
`Scratch RAM,
`8Kx49 sport,
`wcs,
`128x7 sport,
`MAP,
`1Kx49 32001,
`ROM,
`512x32 tport,
`REGs,
`.75 mm2 x 4 =
`Macs,
`.5 mm2 =
`PLL,
`MISC LOGIC, 117,260 gates / (5035 gates / mm”:
`TOTAL CORE
`
`06.77 mm2
`18.29 mm2
`00.24 mm2
`00.45 mm2
`03.49 mm2
`03.30 mm2
`00.55 mm2
`23.29 mm2
`56.22 mm2
`
`
`
`(Core side)2
`Core side
`Die side
`Die area
`
`Pads needed
`LSI PBGA
`
`= core side + 1.0 mm (I/O ce11s)
`= 8.5 mm x 8.5 mm
`
`= 220 signals x 1.25 (vss, Vdd)
`
`=
`=
`=
`=
`
`=
`=
`
`56.22 mm2
`07.50 mm
`08.50 mm
`72.25 mm2
`
`275 pins
`272 pins
`
`FIG. 39
`
`INTEL EX. 1259.031
`
`INTEL Ex. 1259.031
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 30 0f 82
`
`US 6,334,153 132
`
`80 MB/s
`
`512 B
`
`156,250 frames / s
`
`(lOMB/s/lOOBase) x 2 (full duplex) x 4 connections
`Average frame size
`Frame rate = 80MB/s / 512B
`Cpu overhead / frame = (256B context read) + (64B header read) +
`(128B context write) + (128B misc.)
`Total bandwidth = (512B in) + (512B out) + (512B Cpu)
`Dram Bandwidth required = (1536B/frame) x (156,250 frames/s)
`Dram Bandwidth @ 60MHZ = (32 bytes / 167ns)
`Dram Bandwidth @ 66MHz = (32 bytes / 150ns)
`PCI Bandwidth required
`PCI Bandwidth available @ 30 MHz, 32b, average
`PCl Bandwidth available @ 33 MHz, 32b, average
`PCl Bandwidth available @ 60 MHz, 32b, average
`PCI Bandwidth available @ 66 MHZ, 32b, average
`PCl Bandwidth available @ 30 MHz, 64b, average
`PCl Bandwidth available @ 33 MHZ, 64b, average
`PCl Bandwidth available @ 60 MHz, 64b, average
`PCl Bandwidth available @ 66 MHz, 64b, average
`200MB/s
`k————————V————————J
`
`5128 / frame
`
`1536B / frame
`
`240MB/s
`
`202MB/s
`
`224MB/s
`
`80MB/s
`
`46MB/s
`
`50MB/s
`
`92MB/s
`
`100MB/s
`
`92MB/s
`
`lOOMB/s
`
`l84MB/s
`
`||IIIIIIIIllllIIIIIIIIHIIII
`
`FIG. 40
`
`Receive frame interval = 512B / 40MB/s
`Instructions / frame @ 60MHZ = (12.8us/frame) / (50ns/instruction)
`instructions/frame
`Instructions / frame @ 66MHz = (12.8us/frame) / (45ns/instruction)
`instructions/frame
`Required instructions / frame
`Wig
`
`12.8us
`
`256
`
`284
`
`250 instructions/frame
`
`FIG. 41
`
`INTEL EX. 1259.032
`
`INTEL Ex. 1259.032
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 31 0f 82
`
`US 6,334,153 B2
`
`CLK
`
`1
`
`ii
`
`ILAG
`ALU FLAG
`C'Cs
`REG's
`
`LQAD LQAD
`DANAAAFETCHDAD
`Ctr-1CM
`STCOEAE Ctr-lCtrl
`slamlDEIDG
`INSTR.FIETC-HI
`REG Aldr
`&BISEAldr
`IClTACkAIddr
`
`X
`
`“CR
`
`STAck &Addr
`
`
`amDEBUGEAddr
`LOAD
`Ctrl
`
`
`
`
`STAck
`EXCHANGE
`
`PGM
`Ctrl
`
`PC SM AAA]? DEBUG
`° &BASE Addr
`
`
`
`
`IALU ALUITXOPD‘s CsC'
`
`
`ALU TEST LAG QCH0P SEL SEL QCMD
`-UTESTF&M
`“WinQAL
`
`
`
`
`‘
`
`FILE
`
`ALU
`OUT
`
`ALU 12% TEST FLAG QFLGS
`cos
`SEL
`RSLT
`SEL QAder
`
`
`g
`Sram LOAD LQAD
`.
`Ctr-lCtr-l
`AAA
`AAA
`Add-rFIL-E
`
`
`512 32
`Data
`CTX REGs
`C
`C
`I'ASFED
`
`
`INCR
`Ill
`5
`scratch
`
`
`_STRUCTII&1\IIDDECODER_PERANDMULTIPLEXER
`
`
`419m
`
`addr
`
`dout Hut
`
`LIT
`
`
`
`PGMCtrl
`
`PC
`
`FIG. 42
`
`INTEL EX. 1259.033
`
`INTEL Ex. 1259.033
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 32 0f 82
`
`US 6,334,153 B2
`
`INSTRUCTION-WORD FORMAT
`
`
`TYPE
`
`|55z49| MM |41:33|
`
`I32z24|
`
`[2m [1_5_:_(_lQ_1
`
`Jcc
`
`ObOOOOOOO
`
`0b00, Alqu, OpdASel,
`
`OdeSel,
`
`TstSel, Literal
`
`Jmp
`
`ObOOOOOOO
`
`0b01, Alqu, OpdASel,
`
`OdeSel,
`
`FlgSel, Literal
`
`Jsr
`
`Rts
`
`Ob0000000
`
`OblO, Alqu, OpdASel,
`
`OdeSel,
`
`FlgSel, Literal
`
`ObOOOOOOO
`
`Obl 1, Alqu, OpdASel,
`
`OdeSel,
`
`Ohff,
`
`Literal
`
`Nxt
`
`ObOOOOOOO
`
`Obll, Alqu, OpdASel,
`
`OdeSel,
`
`FlgSel, Literal
`
`Map MapAddr
`
`OBXX, OBXXXXX,OBXXXXXXXXX,OBXXXXXXXXX, OHXX, OHXXXX
`
`FIG. 43
`
`INTEL EX. 1259.034
`
`INTEL Ex. 1259.034
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 33 0f 82
`
`US 6,334,153 B2
`
`SEQUENCER BEHAVIOR
`
`if (MapEn & (MapAddr != 0b0000000)){
`Stackc = Stackc;
`StackB = StackB;
`StackA = StackA;
`InstrAddr = 0h8000 | Pc[2:0] | (MapAddr << 3);
`Pc = InstrAddr + (Execute & ~DbgMd);
`Fetch = DbgMd ? DbgAddrzlnstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`
`//re-map instr
`
`else if (Pngtrl = Jcc){
`Stackc = Stackc;
`StackB = StackB;
`StackA = StackA;
`InstrAddr = ~Tst@TstSel ? Pc:(AluDst==Pc) ? AluOutzLiteral;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`
`//conditional jump
`
`else if (Pngtrl == Jmp){
`Stackc = Stackc;
`StackB = StackB;
`StackA = StackA;
`InstrAddr = (AluDst == Pc) ? AluOutzLiteral;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`
`else if (Pngtrl = Jsr){
`Stacke = StackB;
`StackB = StackA;
`StackA = Pc;
`InstrAddr = (AluDst == Pc) ? AluOut:Literal;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`
`else if (FlgSe == Rts){
`InstrAddr = StackA;
`StackA = StackB;
`StackB = Stackc;
`Stackc = ErrVec;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddrzlnstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`
`else
`
`InstrAddr = Pc;
`StackA = StackA;
`StackB = StackB;
`Stackc = Stackc;
`Pc = InstrAddr + (Execute & ~DbgMd)
`Fetch = DbgMd ? DbgAddr:InstrAddr;
`DbgAddr = DbgAddr + (Execute & DbgMd);}
`
`//jump
`
`//jump subroutine
`
`//retum subroutine
`
`//continue
`
`FIG. 44
`
`INTEL EX. 1259.035
`
`INTEL Ex. 1259.035
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 34 0f 82
`
`US 6,334,153 B2
`
`ALU OPERATIONS
`
`Alqu
`
`OPERATION
`
`0b00000
`
`0b00001
`
`0b00010
`
`0b00011
`
`0b00100
`
`0b00101
`
`0b00110
`
`0b00111
`
`0b01000
`
`0b01001
`
`0b01010
`
`0b01011
`
`0b01100
`
`0b01101
`
`0b01110
`
`0b01111
`
`A= (AV& ~(1 << B));
`
`=(B >= 32) ? 1:0;
`
`C——
`
`A = (A & B);
`C = 0; V = 0;
`
`A = (Literal & B);
`C = 0; V = 0;
`
`A = (~Literal & B);
`C = 0; V = 0;
`
`A= (A|(1 << B));
`C——
`=(B >= 32) ? 1: 0;
`
`A = (A | B);
`C = 0; V = 0;
`
`A = (Literal | B);
`C = 0; V = 0;
`
`A = (~Literal | B);
`C = 0; V = 0;
`
`for (i=31, i>=0; i——) if B[i] continue; A=i;
`C = 0; V= (B) ? 0: 1;
`
`A = (A A B);
`C = 0;
`= O;
`
`A = ({Litera1} AB);
`C = 0; V = 0;
`
`A = ({~~Literal} " B);
`C = 0; V = 0;
`
`A = B;
`C = O; V = 0;
`
`A=B[31:24] AB[23:16] AB[15:08] "B[07:00];
`C = 0; V = ;
`
`A = {B[23: 16],B[31: 24],B [07:00],B[15:08]};
`C = 0; V = 0;
`
`A = {B[15: 00], B[31:16]};
`C = 0; V = 0;
`
`//bit clear
`
`//logical and
`
`//logical and
`
`//logical and not
`
`//bit set
`
`//logical or
`
`//logical or
`
`//logical or not
`
`//priority enc
`
`//logical xor
`
`//logical xor
`
`//logical xor not
`
`//move
`
`//hash
`
`//swap bytes
`
`//swap doublets
`
`FIG. 45
`
`INTEL EX. 1259.036
`
`INTEL Ex. 1259.036
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 35 0f 82
`
`US 6,334,153 132
`
`//add B
`
`//add B, carry
`
`//add constant
`
`//sub constant
`
`//sub B
`
`//sub B, borrow
`
`//sub A
`
`//sub A, borrow
`
`//shift left A
`
`//shift left B
`
`//shift left B
`
`//compare
`
`//shift right A
`
`//shift right B
`
`//shift right B
`
`//compare
`
`FUNCTION
`
`A=m+m;
`C = (A + B)[32]; V = 0;
`
`A=(A+B+C);
`C=(A+B+C)[32];V=0;
`
`A = (Literal + B);
`C = (Literal + B)[32]; V = 0;
`
`A = (-Literal + B);
`C = (—Literal + B)[32]; V = O;
`
`A=(A-B);
`C =(A— B)[32]; V= 0;
`
`A=(A-B-~C);
`C=(A-B-~C)[32];V=0;
`
`A = (-A + B);
`C = (-A + B)[32]; V = 0;
`
`A (-A + B - ~C);
`(-A + B - ~C)[32]; V = 0;
`
`C A
`
`=(A<<B);
`C= A[3l];V=(B>= 32)?0:1;
`
`A = (B << Literal);
`C = B[31]; V = (Literal >= 32)? 0:1;
`
`A=<B<<1);
`C= B[31];V=0;
`
`n=(A-B);
`C =(A- B)[32]; V: 0;
`
`A: (A >> B);
`C= A[0]; V= (B >= 32) ? 1:0;
`
`A = (B >> Literal);
`C = A[0]; V = (Literal >= 32)? 1:0;
`
`A=(B>> 1);
`c= A[0]; V=0;
`
`n=(B-A);
`c =(B — A)[32]; V: 0;
`
`Alugg
`
`0b10000
`
`0b10001
`
`0b10010
`
`0b10011
`
`0b10100
`
`0b10101
`
`0b10110
`
`0b10111
`
`Obl 1000
`
`0b11001
`
`0b11010
`
`0b11011
`
`0b11100
`
`0b11101
`
`0b11110
`
`0b11111
`
`FIG. 46
`
`INTEL EX. 1259.037
`
`INTEL Ex. 1259.037
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 36 of 82
`
`US 6,334,153 B2
`
`9%—
`0b0000aaaaa
`
`SELECTED OPERANDS
`
`File
`
`File@(0pdSel[4:0] | FileBase);
`Allows paged access to any part of the register file.
`
`0b000 1 aaaaa
`
`CpuReg
`
`File@{2'b11, CpuId, 0 dSel[4:0 };
`Allows direct access to
`pu speci 1c registers.
`
`ObOOIXXXXXX reserved
`
`Reserved for future expansion.
`
`ObOIOOOOOXX
`
`CpuStatus
`
`0b0000000000000BHD00000000000000CC
`This is a read—only register providing information about the Cpu executing
`(OpdSel[l :0]) cycles after the current cycle. "CC" represents a value
`indicating the Cpu. Currently, only Cpuld values of 0, l and 2 are returned.
`"H" represents the current state of Hit, "D" indicates DbgMd and "B"
`indicates BigMd. Writing this register has no effect.
`
`0b010000 1 XX
`
`reserved
`
`Reserved for future expansion.
`
`0b01000 lOXX
`
`Pc
`
`0b0100011XX
`
`DbgAddr
`
`OXOOOOAAAA
`Writing to this address causes the program control logic to use AluOut as the
`new Pc value in the event of a Jmp, Jcc or Jsr instruction for the Cpu
`executing during the current cycle. If the current instruction is Nxt, Ma , or
`Rts, the register write has no effect. Reading this register returns the va ue in
`Pc for the Cpu executing (0pdSel[1:0]) cycles after the current cycle.
`
`OxDOOOAAAA
`Writing to this register alters the contents of the debug address register
`(DbgAddr) for the Cpu executing (OJidSel[1:0]) cycles afier the current
`cycle. DbgAddr provides the fetch a dress for the control-store when
`Db Md has been selected and the Cpu is executing. DbgAddr is also used
`as t e control-store address when performing a Wchs@DbgAddr or
`RdWcs Db Addr operation. “D” represents bit 31 of the register. It is a general
`purpose agt at is used for event indication during simulation. Reading this
`register returns a value of 0x00000000.
`
`0b01001XXXX reserved
`
`Reserved for future expansion.
`
`0b010100000
`
`RamAddr {0b1CCC, 0x000, 0b1, AAAA}
`RamAddr = AluOut[15] ? AluOut : (AluOut | RamBase);
`PrevCC = AluOut[3l] ? CCC
`: AluCC;
`
`A read/write register. When reading this register, the Alu condition codes from the previous
`instruction are returned together with RamAddr.
`
`bit
`31
`30
`29
`28
`27:16
`15
`14:0
`
`name
`
`PrevC
`PrevV
`PrevZ
`
`RamAddr
`
`tion
`descri
`Always 1.
`Previous Alu Carry.
`Previous Alu Overflow.
`Previous Alu Zero.
`Always 0.
`Always 1.
`Contents of last Sram address used.
`
`When writing this register, if a1u_out[31] is set, the previous condition codes will be overwritten with
`bits 30:28 of AluOut. If AluOut[15] is set, bits 14:0 will be written to the RamAddr. If AluOut [15]
`is not set, bits 14:0 will be ored with the contents of the RamBase and written to the RamAddr
`
`FIG. 47
`
`INTEL EX. 1259.038
`
`INTEL Ex. 1259.038
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 37 0f 82
`
`US 6,334,153 B2
`
`OQdSel
`0b010100001
`
`SELECTED OPERANDs
`
`AddrRegA
`
`0x0000AAAA
`
`AddrRegA = AluOut;
`
`A read/write o erand which loads AddrRegA used to provide the address for read and write
`(wlelmtions. W en AddrRegA[15] is set, the contents Will be presented directly to the ram.
`en AddrRegA[15% is_ reset, the contents will first be ored With the contents of the RamBase
`register before resen
`ation to the ram. Writing to this register takes priority over Literal loads
`ue of the register.
`usmg FlgOp.
`eading this register returns the current va
`
`0b010100010
`
`AddrRegB OXOOOOAAAA
`
`AddrRegB = AluOut;
`
`A read/write operand which loads AddrRegB used to provide the address for read and write
`0 erations.
`\lghen AddrRe B[15] is set, the contents will be presented directly to the ram. When
`AddrRegBU 5
`is reset, the contents Will first be ored With the contents of the RamBase
`register before resentation to the ram. Writing to this register takes priority over Literal loads
`usmg FlgOp.
`eading this register returns the current va ue of the register.
`
`0b010100011
`
`0X0000AAAA
`AddrRegAb
`AddrRegA = AluOut; AddrRegB = AluOut;
`
`0b010100100
`
`A destination only operand which loads AddrRegB and AddrRegA used, to provide the address
`for read and write operations Writing to this re ister takes(priority over Literal loads usmg
`FlgOp. Reading this register returns the value x0000000
`RamBase
`OXOOOOAAAA
`RamBase = AluOut;
`
`0b010100101
`
`A read/write register which provides'the base address for ram read and write cycles. When
`RamAddrHS] is set, the contents Will not be used. When RamAddr[15] is reset, the contents
`Will first be ored. With the contents of the RamBase re ister before presentation to the ram.
`Reading this register returns the value for the current pu.
`FileBase
`0b000000000000OOOOOOOOOOOAAAAAAAAA
`FileBase = AluOut'
`FileAddr = 0pdSei[8] ? OpdSel:(0pdSel + FileBase);
`A read/write register which provides the base address for file read and write cycles. When
`0 dSel 8] is set, the conten 5 Will not be used and OpdSel Will be presented irectl
`to the
`a dress ines of the file. When 0 dSel[8] is reset, the contents w111 first be_ored.w1t
`the
`contents of the FileBase register efore presentation to the file. Reading this register returns the
`value for the current Cpu.
`
`0b010100110
`
`InstrRegL
`
`0x11111111
`
`This is a read-only re ister which returns the contents of InstrReg[3 l :0]. Writing to
`this register has no e fect.
`
`0b010100111
`
`InstrRegH
`
`0x00111111
`
`register which returns the contents of InstrReg[55:32]. Writing to this
`This is a read-onl
`register has no ef ect.
`
`FIG. 48
`
`INTEL EX. 1259.039
`
`INTEL Ex. 1259.039
`
`

`

`US. Patent
`
`Dec. 25, 2001
`
`Sheet 38 0f 82
`
`US 6,334,153 B2
`
`OQdSel
`
`SELECTED OPERANDS
`
`0b010101000
`
`Minusl
`
`Oxffffffff
`
`This is a read-only register which supplies a value 0xffffffff.. Writing to this
`register has no effect.
`
`0b010101001
`
`FreeTime
`
`A free-runningtimer with a resolution of l .00 microseconds and a maximum count
`of 71 minutes. This timer is cleared during reset.
`
`0b010101010
`
`LiteralL
`
`Instr[15:0]
`A read-only register. Writing to this register has no effect
`
`0b0101010ll
`
`LiteralH
`
`Instr[15:0]<<16;
`A read-only register. Writing to this register has no effect
`
`0b010101100
`
`MacData - Writing to this address loads the AluOut data into the MacData register for use
`during Mac operations. The Mac operation, resulting from writing to the MacOp register,
`determines the definition of the MacData register contents as follows.
`
`MacOQ
`Mstop
`
`WrMefg
`
`MacData definition
`ObXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
`MacData is not used for the StopM operation.
`
`hrstl, rsvd, rsvd, crcen, fulld, hrstl, hugen, nopre, paden, prtyl, xdllO,
`ipgrl[6:0],
`ipgr2[6:0], ipgt[6:0].
`Loads the Machg register with the contents of the MacData register. Refer to
`LSI Logic's Ethernet-I 1 0 Core Technical Manual for detailed definitions ofthese
`bits.
`
`Werng
`
`ObXXXXXXXXXXXXXXXXXXXXXSSSSSSSSSSS
`Loads seed[10:0] into the Mac's random number generator.
`
`RdPhy
`
`WrPhy
`
`ObXXXXRRRRXXXXPPPPXXXXXXXXXXXXXXXX
`Reads register[R]