Filed: May 15, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`INTEL CORP., CAVIUM, INC., and
`WISTRON CORPORATION,
`Petitioner,
`
`v.
`
`ALACRITECH, INC.,
`Patent Owner.
`______________________
`
`Case IPR2017-013921
`U.S. Patent No. 7,337,241
`Title: FAST-PATH APPARATUS FOR RECEIVING DATA CORRESPONDING
`TO A TCP CONNECTION
`______________________
`
`PETITIONER’S REPLY TO PATENT OWNER’S RESPONSE TO
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,337,241
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`1 Cavium, Inc., which filed a Petition in Case IPR2017-01728, has been joined as a
`
`petitioner in this proceeding. Wistron Corporation, who filed a Petition in Case
`
`IPR2018-00328, has been joined as a petitioner in this proceeding.
`
`
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`I. 
`
`II. 
`
`TABLE OF CONTENTS
`
`Page
`INTRODUCTION .......................................................................................... 1 
`
`ALTEON IS PRIOR ART ............................................................................... 2 
`
`A.  Alteon Was Accessible To A POSA From Alteon.com Before
`The Alleged Priority Date ..................................................................... 3 
`
`B. 
`
`C. 
`
`Patent Owner Has Admitted That A Substantively Identical
`Alteon Reference Is Prior Art ................................................................ 3 
`
`The Company Alteon And Alteon.com Was Known To Those
`Of Skill In The Art ................................................................................ 4 
`
`III.  THE COMBINATION OF ERICKSON, TANENBAUM96 AND
`ALTEON RENDERS CLAIMS 1-8 OBVIOUS ............................................. 4 
`
`A. 
`
`B. 
`
`C. 
`
`D. 
`
`E. 
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That
`The Prior Art Discloses Validation of Network and Transport
`Layer Headers “Without an Interrupt Dividing the Processing”
`of the Layer Headers (Claim 1) ............................................................. 4 
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That
`The Prior Art Discloses Sending the Data From Each Packet to
`a Destination in Memory Without Sending Any of the Headers
`(Claim 1) ................................................................................................ 7 
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That
`The Prior Art Discloses Processing MAC Layer Headers
`without an Interrupt (Claim 2) .............................................................. 8 
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That
`The Prior Art Discloses Processing an Upper Layer Header by a
`Second Mechanism (Claim 3) ............................................................... 8 
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That
`Prior Art Discloses Sorting the Packets by Classifying Each as
`Having IP and TCP Headers (Claim 6) ................................................. 9 
`
`i
`
`

`

`IV.  PATENT OWNER HAS FAILED TO REBUT PETITIONER’S
`SHOWING THAT ERICKSON, TANENBAUM96, AND ALTEON
`REFERENCES SHOULD BE COMBINED .................................................. 9 
`
`A.  A POSA Would Have Been Motivated to Combine Erickson,
`Tanenbaum96, and Alteon .................................................................... 9 
`
`C. 
`
`Alteon and Erickson Are Compatible ................................................. 11 
`
`V. 
`
`THE COMBINATION OF ERICKSON, TANENBAUM96 AND
`ALTEON RENDERS CLAIMS 9-17, 19-21, AND 24 OBVIOUS ............. 13 
`
`A. 
`
`B. 
`
`C. 
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That
`The Prior Art Discloses “Prepending the MAC, Network, and
`Transport Layer Headers at One Time as a Sequence of Bits ”
`(Claim 9) .............................................................................................. 13 
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That
`The Prior Art Discloses Prepending Each Packet Header
`Without an Interrupt Dividing the Prepending of the MAC, IP,
`and TCP Headers (Claim 17) .............................................................. 14 
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That
`The Prior Art Discloses Dividing the Data Into Multiple
`Segments and Prepending a Packet Header to Each of the
`Segments by a Second Processor/Mechanism (Claims 9 and 17) ...... 15 
`
`VI.  PATENT OWNER HAS FAILED TO REBUT PETITIONER’S
`SHOWING THAT ERICKSON AND TANENBAUM96 SHOULD
`BE COMBINED ............................................................................................ 16 
`
`VII.  THE COMBINATION OF ERICKSON, TANENBAUM96 AND
`ALTEON RENDER CLAIMS 18, 22, AND 23 OBVIOUS ........................ 18 
`
`VIII.  THE EVIDENCE OF OBVIOUSNESS FAR OUTWEIGHS
`PATENT OWNER’S ALLEGED “OBJECTIVE EVIDENCE” .................. 19 
`
`A. 
`
`B. 
`
`Patent Owner Has Not Shown Nexus Between The Challenged
`Claims Of The 241 Patent and The “Objective Evidence” ................. 19 
`
`There Is No Evidence of Long-Felt Need ........................................... 20 
`ii
`
`

`

`C. 
`
`D. 
`
`E. 
`
`F. 
`
`There Is No Evidence of Commercial Success ................................... 20 
`
`There Is No Evidence of Praise ........................................................... 23 
`
`There Is No Evidence of Trying and Failing ...................................... 23 
`
`There Is No Evidence of Skepticism ................................................... 24 
`
`IX.  THE REAL PARTY OF INTEREST IS CORRECTLY NAMED ............... 24 
`
`X.  CONCLUSION ............................................................................................ 25 
`
`
`
`
`iii
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases 
`Bosch Auto. Serv. Sols., LLC v. Matal,
`878 F.3d 1027 (Fed. Cir. 2017) ............................................................................ 22
`In re Cree, Inc.,
`818 F.3d 694 (Fed. Cir. 2016) .............................................................................. 20
`In re Fritch,
`972 F.2d 1260 (Fed. Cir. 1992) ............................................................................ 12
`In re Merck & Co.,
`800 F.2d 1091 (Fed. Cir. 1986) ............................................................................ 15
`Meiresonne v. Google, Inc.,
`849 F.3d 1379 (Fed. Cir. 2017) ............................................................................ 11
`MRC Innovations, Inc. v. Hunter Mfg., LLP,
`747 F.3d 1326 (Fed. Cir. 2014) ............................................................................ 19
`
`Wyers v. Master Lock Co.,
`616 F.3d 1231 (Fed. Cir. 2010) ............................................................................ 19
`Statutes and Regulations 
`Eastern District of Texas Patent L.R. 3-1(f) ............................................................ 20
`
`
`
`
`iv
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`EXHIBIT LIST
`
`Description
`
`U.S. Patent No. 7,337,241 (“241 Patent”)
`Excerpts from Prosecution File History of U.S. Patent
`No. 7,337,241 (“241 File History”)
`Declaration of Robert Horst
`Curriculum Vitae of Robert Horst
`U.S. Patent No. 5,768,618 (“Erickson”)
`Tanenbaum, Andrew S., Computer Networks, Prentice-Hall, Inc.,
`New Jersey (1996). (“Tanenbaum96”)
`Transmission Control Protocol, “Darpa Internet Protocol
`Specification”, RFC: 793, Sept. 1981. (“RFC 793”)
`Stevens, W. Richard, TCP/IP Illustrated Volume 1: The
`Protocols, Addison-Wesley (1994). (“Stevens1”)
`Lilinkamp, J., Mandell. R. and Padlipsky, M., “Proposed Host-
`Front End Protocol”, Network Working Group Request for
`Comments: 929, Dec. 1984. (“RFC 929”)
`Number Not Used
`Librarian Declaration of Rice Mayors regarding Andrew S.
`Tanenbaum, Computer Networks (3rd ed. 1996)
`(Ex.1006,“Tanenbaum96”)
`Number Not Used
`Stevens, W. Richard and Wright, Gary R., TCP/IP Illustrated
`Volume 2: The Implementation, Addison-Wesley (1995).
`(“Stevens2”)
`Number Not Used
`Thia, Y.H., Woodside, C.M., “A Reduced Operation Protocol
`Engine (ROPE) for a Multiple-Layer Bypass Architecture”,
`Protocols for High Speed Networks (Dordrecht), 1995. (“Thia”)
`
`v
`
`Exhibit #
`
`Ex. 1001
`
`Ex. 1002
`
`Ex. 1003
`Ex. 1004
`Ex. 1005
`
`Ex. 1006
`
`Ex. 1007
`
`Ex. 1008
`
`Ex. 1009
`
`Ex. 1010
`
`Ex. 1011
`
`Ex. 1012
`
`Ex. 1013
`
`Ex. 1014
`
`Ex. 1015
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`Exhibit #
`
`Ex. 1016
`
`Ex. 1017
`
`Ex. 1018
`
`Ex. 1019
`
`Description
`
`Biersack, E. W., Rütsche E., “Demultiplexing on the ATM
`Adapter: Experiments with Internet Protocols in User Space”,
`Journal on High Speed Networks, Vol. 5, No. 2, May 1996.
`(“Biersack”)
`Rütsche, E., Kaiserswerth, M., “TCP/IP on the Parallel Protocol
`Engine”, Proceedings, IFIP Conference on High Performance
`Networking, Liege (Belgium), Dec. 1992. (“Rütsche92”)
`Rütsche, E., “The Architecture of a Gb/s Multimedia Protocol
`Adapter”, Computer Communication Review, 1993.
`(“Rütsche93”)
`Padlipsky, M. A., “A Proposed Protocol for Connecting Host
`Computers to Arpa-Like Networks Via Directly-Connected Front
`End Processors”, Network Working Group RFC #647, Nov. 1974.
`(“RFC 647”)
`
`Ex. 1020
`
`U.S. Patent No. 5,619,650 (“Bach”)
`
`Ex. 1021
`
`U.S. Patent No. 5,915,124 (“Morris”)
`
`Ex. 1022
`
`Ex. 1023
`
`Ex. 1024
`
`Cooper, E.C., et al., “Protocol Implementation on the Nectar
`Communication Processor”, School of Computer Science,
`Carnegie Mellon University, Sept. 1990. (“Cooper”)
`Kung, H.T., et al., “A Host Interface Architecture for High-Speed
`Networks”, School of Computer Science, Carnegie Mellon
`University and Network Systems Corporation. (“Kung”)
`Exhibit D to Declaration of Dr. Gregory L. Chesson in Support of
`Microsoft’s Opposition to Alacritech’s Motion for Preliminary
`Injunction: “Protocol Engine Handbook”, Protocol Engines
`Incorporated, Oct. 1990. (“Chesson”)
`
`vi
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`Exhibit #
`
`Ex. 1025
`
`Ex. 1026
`
`Ex. 1027
`
`Ex. 1028
`
`Ex. 1029
`
`Ex. 1030
`
`Ex. 1031
`
`Ex. 1032
`
`Ex. 1033
`
`Ex. 1034
`
`Description
`
`Kanakia, H., Cheriton, D.R., “The VMP Network Adapter Board
`(NAB): High-Performance Network Communication for
`Multiprocessors”, Communications Architectures & Protocols,
`Stanford University, Aug. 1988. (“Kanakia”)
`Kung, H.T., Cooper, E.C., et al., “Network-Based
`Multicomputers: An Emerging Parallel Architectures”, School of
`Computer Science, Carnegie Mellon University. (“Kung and
`Cooper”)
`Dalton, C., et al., “Afterburner: Architectural Support for High-
`Performance Protocols”, Networks & Communications
`Laboratories, HP Laboratories Bristol, July 1993. (“Dalton”)
`Murphy, E., Hayes, S., Enders, M., TCP/IP Tutorial and
`Technical Overview Fifth Edition, Prentice-Hall, Inc. New Jersey,
`(1995). (“Murphy”)
`MacLean, A.R., Barvick, S. E., “An Outboard Processor for High
`Performance Implementation of Transport Layer Protocols”,
`IEEE Globecom ’91, Phoenix, AZ, Dec. 1991. (“MacLean”)
`Clark, D.D., et al., “An Analysis of TCP Processing Overhead”,
`IEEE Communications Magazine, June 1989. (“Clark”)
`
`U.S. Provisional Application 60/061,809 (“Alacritech 1997
`Provisional Application”)
`Culler, E.C., et al., “Parallel Computing on the Berkeley NOW”,
`Computer Science Division, University of California, Berkeley.
`(“Culler”)
`“Gigabit Ethernet Technical Brief: Achieving End-to-End
`Performance”, Alteon Networks, Inc. First Edition, Sept. 1996.
`(“Alteon”)
`Smith, J.A., Primmer, M., “Tachyon: A Gigabit Fibre Channel
`Protocol Chip”, Hewlett-Packard Journal, Article 12, Oct. 1996.
`(“Smith”)
`
`vii
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`Exhibit #
`
`Ex. 1035
`
`Ex. 1036
`
`Description
`
`Patterson, D.A., Hennessy, J.L., Computer Architecture: A
`Quantitative Approach, Morgan Kaufmann Publishers, Inc., San
`Mateo, CA (1990). (“Patterson”)
`Internet Protocol, “Darpa Internet Protocol Specification”, RFC:
`791, Sept. 1981. (“RFC 791”)
`
`Ex. 1037
`
`Number Not Used
`
`Ex. 1038
`
`Ex. 1039
`
`Exs. 1040-
`1050
`
`Woodside, C. M., Ravindran, K. and Franks, R. G.. “The protocol
`bypass concept for high speed OSI data transfer.” IFIP Workshop
`on Protocols for High Speed Networks. 1990. (“Woodside”)
`Joint Claim Construction and Pre-Hearing Statement Pursuant to
`Rule 4-3 (Alacritech, Inc. v. Dell Inc, Intel Corporation, et al.)
`(“JCCS”)
`
`Numbers Not Used
`
`Ex. 1051
`
`U.S. Patent No. 4,027,293
`
`Ex. 1052
`
`U.S. Patent No. 5,329,630
`
`Exs. 1053-
`1061
`
`Ex. 1062
`
`Exs. 1063-
`1076
`
`Numbers Not Used
`
`Rebuttal Declaration of Paul S. Min in Support of Plaintiff’s
`Claim Construction Brief (“Min Rebuttal Declaration”)
`
`Numbers Not Used
`
`Ex. 1077
`
`Deposition of Paul S. Min on March 21, 2017 (“Min Depo”)
`
`viii
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`Exhibit #
`
`Exs. 1078-
`1086
`
`Ex. 1087
`
`Exs. 1088-
`1109
`
`Description
`
`Numbers Not Used
`
`Librarian Declaration of Christopher Butler regarding “Gigabit
`Ethernet Technical Brief: Achieving End-to-End Performance”,
`Alteon Networks, Inc. First Edition, Sept. 1996. (Ex.1033,
`“Alteon”) (“First Butler Declaration”)
`
`Numbers Not Used
`
`Ex. 1110
`
`Declaration of Garland Stephens
`
`Ex. 1111
`
`Declaration of S. Christopher Kyriacou
`
`Ex. 1112
`
`Exs. 1113-
`1200
`
`Ex. 1201
`
`Ex. 1202
`
`Ex. 1203
`
`Ex. 1204
`
`Alacritech’s Answer from Alacritech v. CenturyLink, et al.
`16cv693
`
`Numbers Not Used
`
`A true and correct copy of the following website as of December
`27, 2017:
`https://web.archive.org/web/19970622102719/http://www.alteon.
`com/index.html “Archived version of the Alteon home page”.
`A true and correct copy of the following website as of December
`27, 2017:
`https://web.archive.org/web/19970622102647/http://www.alteon.
`com:80/presintr.html
`A true and correct copy of the following website as of December
`27, 2017:
`https://web.archive.org/web/19970622102901/http://www.alteon.
`com:80/techbr01.html
`A true and correct copy of the following website as of December
`27, 2017:
`
`ix
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`Exhibit #
`
`Description
`
`https://web.archive.org/web/19970622103538/http://www.alteon.
`com:80/whitpapr.pdf
`
`Ex. 1205
`
`Request for Comments (“RFC”) 2026
`
`A true and correct copy of the following website as of December
`27, 2017: https://www.rfc-
`editor.org/search/rfc_search_detail.php?rfc=929&pubstatus%5B
`%5D=Any&pub_date_type=any
`A true and correct copy of the following website as of December
`27, 2017: https://www.rfc-
`editor.org/search/rfc_search_detail.php?rfc=793&pubstatus%5B
`%5D=Any&pub_date_type=any
`
`Numbers Not Used
`
`Declaration of Robert Horst, Ph. D. In Support of Petitioner’s
`Response in Opposition to Patent Owner’s Contingent Motion to
`Amend (April 4, 2018)
`
`Numbers Not Used
`
`Ex. 1206
`
`Ex. 1207
`
`Exs. 1208-
`1209
`
`Ex. 1210
`
`Exs. 1211-
`1214
`
`Ex. 1215
`
`Second Affidavit of Christopher Butler (March 16, 2018)
`
`Ex. 1216
`
`Number Not Used
`
`Ex. 1217
`
`The Memory-Integrated Network Interface by Ron Minnich, et al.
`(February 1995)
`
`Ex. 1218
`
`Number Not Used
`
`Ex. 1219
`
`Budding Alteon to Offer Gigabit Ethernet Switch, InfoWorld,
`(August 26, 1996)
`
`x
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`Exhibit #
`
`Ex. 1220
`
`Ex. 1221
`
`Ex. 1222
`
`Ex. 1223
`
`Ex. 1224
`
`Ex. 1225
`
`Description
`
`IBM, Alteon Strike Gigabit Ethernet deal, InfoWorld (May 12,
`1997)
`
`Internet pages directed to Technical Brief on Alteon Ethernet
`Gigabit NIC (Printed Mar. 15, 1997)
`
`The design of Nectar : a network backplane for heterogeneous
`multicomputers by E. Arnould, et al. (1989)
`Declaration of Robert Horst, Ph.D. In Support of Petitioner’s
`Reply to Patent Owner’s Response to petition for Inter Partes
`Review of U.S. patent No. 7,337, 241.
`Deposition of Kevin C. Almeroth, Ph.D., Volume 1 (May 03,
`2018)
`
`Deposition of Kevin C. Almeroth, Ph.D., Volume 2 (May 04
`2018)
`
`Ex. 1226
`
`Number Not Used
`
`Ex. 1227
`
`New ASIC drives Alacritech into storage by R. Merritt, EE Times
`(January 11, 2011)
`
`Ex. 1228
`
`Internet page from Alacritech.com downloaded on May 6, 2018
`
`Ex. 1229
`
`Number Not Used
`
`Ex. 1230
`
`Ex. 1231
`
`Why Are We Deprecating Network Performance Features? By B.
`Wilson downloaded on May 2, 2018
`Alacritech, Inc.’s Answer and Counterclaims to Intel
`Corporation’s Complaint in Intervention from Alacritech v.
`CenturyLink, et al., 16cv693, Eastern District of Texas (D.I. 94)
`(December 13, 2016)
`
`xi
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`Exhibit #
`
`Ex. 1232
`
`Ex. 1233
`
`Description
`
`Alacritech’s First Amended and Supplemental Patent Initial
`Disclosure from Alacritech v. CenturyLink, et al., 16cv693,
`Eastern District of Texas (February 24, 2017)
`Alacritech, Inc.’s Answer and Counterclaims to Cavium Inc.’s
`Complaint in Intervention from Alacritech v. CenturyLink, et al.,
`16cv693, Eastern District of Texas (D.I. 137) (February 24, 2017)
`
`Ex. 1234
`
`Number Not Used
`
`Ex. 1235
`
`Patent Local Rules for the Eastern District of Texas
`
`Ex. 1236
`
`Updated Curriculum Vitae of Robert Horst
`
`Ex. 1237
`
`Number Not Used
`
`Ex. 1238
`
`Number Not Used
`
`Ex. 1239
`
`Ex. 1240
`
`Comparison of Alteon (Ex. 1033) and “Internet pages directed to
`Technical Brief on Alteon Ethernet Gigabit NIC (Printed Mar. 15,
`1997)” (Ex. 1221)
`IETF SNMP Working Group Internet Draft SNMP
`Communications Services by Frank J. Kastenholz (April 1991)
`
`Ex. 1241
`
`Number Not Used
`
`Ex. 1242
`
`Ex. 1243
`
`John S. Quarterman, Abraham Silberschatz, and James L.
`Peterson. 1985. 4.2BSD and 4.3BSD as examples of the UNIX
`system. ACM Comput. Surv. 17, 4 (December 1985), 379-418.
`The Internet Archive: Building an 'Internet Library' downloaded
`at: https://web.archive.org/web/20000408223908
`/https://archive.org/about/index.html
`
`xii
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`Description
`
`History of Search Engines: From 1945 to Google Today
`downloaded at: http://www.searchenginehistory.com/
`History Of Search Engines by Tom Seymour, et al., International
`Journal of Management & Information Systems, Volume 15,
`Number 4 (2011)
`Press Release: Alteon Networks and Network Appliance
`Demonstrate Gigabit Ethernet Connectivity at NetWorld+Interop
`Atlanta (September 18, 1996)
`Sun to OEM Alteon's Gigabit Ethernet products by Robert
`McMillan (May 1, 1997)
`Modeling and analysis of the Unix communication subsystems by
`Yi-Chun Chu and Toby J. Teorey In Proceedings of the 1996
`conference of the Centre for Advanced Studies on Collaborative
`research (CASCON '96) (1996)
`Excerpt from Report of Alacritech’s Expert Dr. Kevin C.
`Almeroth Concerning Intel’s Infringement from from Alacritech
`v. CenturyLink, et al., 16cv693, Eastern District of Texas
`(October 23, 2017)
`Declaration of Dr. Kevin C. Almeroth in Support of Alacritech’s
`Motion for Preliminary Injunction of Microsoft’s Infringement of
`Claim 1 of U.S. Patent 6,697,868 from Alacritech, Inc. v.
`Microsoft Corporation, Northern District of California,
`04cv03284 (D.I. 27) (November 19, 2004)
`Declaration of Dr. Kevin C. Almeroth in Support of Alacritech’s
`Reply to Microsoft’s Opposition to of Alacritech’s Motion for
`Preliminary Injunction from Alacritech, Inc. v. Microsoft
`Corporation, Northern District of California, 04cv03284 (D.I. 73)
`(February 11, 2005)
`
`Exhibit #
`
`Ex. 1244
`
`Ex. 1245
`
`Ex. 1246
`
`Ex. 1247
`
`Ex. 1248
`
`Ex. 1249
`
`Ex. 1250
`
`Ex. 1251
`
`
`
`
`xiii
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`I.
`
`INTRODUCTION
`Nothing in Patent Owner’s Response (“Response”) rebuts Petitioner’s
`
`showing that Alteon is prior art or that the challenged claims are obvious. The
`
`Internet Archive shows that Alteon was not only available before the priority date
`
`of the 241 Patent, but that it was accessible from Alteon’s main webpage. Patent
`
`Owner itself printed information from this website on March 15, 1997—6 months
`
`before the priority date—that is a nearly verbatim copy of the relevant portions of
`
`Alteon and submitted it to the Patent Office. Moreover, nothing in Erickson or
`
`Tanenbaum96 suggests that TCP/IP processing is divided by an interrupt, and the
`
`alleged priority application for the 241 Patent itself admits that the prior art
`
`processed TCP/IP packets using fewer than one interrupt per packet. Alteon
`
`merely shows that a POSA would have understood this.
`
`Patent Owner also contends that several limitations of the challenged claims
`
`are not met, but its arguments focus on the prior art references in isolation and fail
`
`to address the combination identified by Petitioner—namely, using the teachings of
`
`Tanenbaum96 to implement TCP functionality disclosed in Erickson. These
`
`arguments fail as a matter of law.
`
`In addition, Patent Owner argues that a POSA would not combine Erickson
`
`with Tanenbaum96 because TCP/IP and UDP/IP are “fundamentally
`
`incompatible.” This argument also fails. Erickson explicitly states that the
`
`1
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`disclosed network interface device supports TCP/IP and identifies Tanenbaum96
`
`as a source of information about TCP/IP. Ex. 1005 at 8:3-5, 4:40-42. Further, TCP
`
`and UDP were the only two transport protocols available for the IP protocol, and
`
`were known alternatives. A POSA would have been motivated to consult
`
`Tanenbaum96 to implement Erickson’s TCP functionality and had a more than
`
`reasonable expectation of success in implementing the combination of Erickson
`
`with Tanenbaum96 because, as Tanenbaum96 points out, TCP/IP implementations
`
`were freely available and were documented in detail.
`
`Finally, Patent Owner argues that “secondary considerations” weigh against
`
`a finding of obviousness. But its cursory, unsubstantiated assertions about the
`
`“secondary considerations” are completely untethered to the challenged claims of
`
`the 241 Patent and unsupported by any evidence relevant to the claims.
`
`II. ALTEON IS PRIOR ART
`Patent Owner’s Response notably does not argue that Alteon is not prior art,
`
`only that Petitioner has failed to put forth sufficient evidence. This is likely
`
`because Patent Owner submitted a version of Alteon to the Patent office during
`
`prosecution and admitted that the submitted version is prior art. Ex. 1002 at .309-
`
`10 (Rows Q and N). The sum total of evidence leads to the undeniable conclusion
`
`that Alteon was available prior art and would have been readily found by a POSA.
`
`2
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`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`A. Alteon Was Accessible To A POSA From Alteon.com Before The
`Alleged Priority Date
`As of at least January 13, 1997, Alteon was available on Alteon’s website.
`
`Ex. 1087 at .004. This is undisputed. Ex. 2026, ¶ 102 n. 4; Paper 4 (“Pet.”) at 40.
`
`Patent Owner’s only argument is that a POSA would not have been able to find it.
`
`However, as explained by Dr. Horst, the Internet Archive has a clear record
`
`that Alteon was available through a series of links from the Alteon.com home page
`
`at least by June 22, 1997, which is months before the earliest possible priority date
`
`of the 241 Patent. Ex. 1223, ¶¶ 23-28.
`
`Moreover, like the Internet Archive, search engines also use crawlers to
`
`index web pages for searching. If the Internet Archive could find it, so could a
`
`search engine, such as Altavista. Ex. 1223, ¶¶ 24-25. A POSA would certainly
`
`have relied on search engines in 1997 to locate relevant art. Ex. 1223, ¶ 25
`
`B.
`
`Patent Owner Has Admitted That A Substantively Identical
`Alteon Reference Is Prior Art
`Patent Owner cited both Alteon (Ex. 1033) and a web page printout from
`
`Alteon (Ex. 1221) which Patent Owner identified as “Internet pages directed to
`
`Technical Brief on Alteon Ethernet Gigabit NIC technology. . ., printed Mar. 15,
`
`1997.” As Dr. Horst points out, the relevant part of this “Technical Brief” is
`
`substantively identical to Alteon. Ex. 1223, ¶ 27; Ex. 1239 (comparison). Every
`
`citation in the Petition and Dr. Horst’s declarations are also contained in Ex. 1221.
`
`3
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`

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`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`C. The Company Alteon And Alteon.com Was Known To Those Of
`Skill In The Art
`A POSA would have had knowledge of the Alteon.com home page as of
`
`early 1997. Several large corporations had partnered with Alteon to promote its
`
`Interface Card. See Ex. 1223, ¶ 28. Dr. Horst identified Alteon as one of the few
`
`developers of Gigabit technology at the time of the alleged invention. Ex. 1223, ¶
`
`28. A POSA would have been motivated to look to documentation provided by
`
`Alteon. Ex. 1223, ¶ 28.
`
`III. THE COMBINATION OF ERICKSON, TANENBAUM96 AND
`ALTEON RENDERS CLAIMS 1-8 OBVIOUS
`A.
`Patent Owner Has Failed to Rebut Petitioner’s Showing That The
`Prior Art Discloses Validation of Network and Transport Layer
`Headers “Without an Interrupt Dividing the Processing” of the
`Layer Headers (Claim 1)
`The Board recognized that Petitioner relies on Erickson, not Alteon, to teach
`
`that the validation of headers is done by the interface and not the host computer.
`
`Paper 11 at 14. Alteon discloses the absence of interrupts for each incoming
`
`packet, and thus for many or most incoming packets there cannot be an interrupt to
`
`the host. Ex. 1003, ¶ 169; Ex. 1033 at .022. A POSA would have been motivated
`
`to minimize the number of interrupts and certainly not issue interrupts during the
`
`validation of each packet. Ex. 1003, ¶ 171; Pet. at 48. Importantly, neither
`
`Erickson nor Tanenbaum96 discloses or suggests that interrupts divide the
`
`4
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`processing of headers during TCP/IP protocol processing. Pet. at 48. This alone
`
`should be sufficient.
`
`Patent Owner argues that Alteon’s interrupt timer and adaptive interrupts do
`
`not disclose the validation of layer headers without an interrupt. Paper 34 at 33.
`
`However, as the Board recognized, the Patent Owner’s arguments are just “attacks
`
`[on the] references individually” and are “not responsive to the Petitioner’s
`
`assertions.” Paper 11 at 14. Petitioners rely on the teachings of Tanenbaum96 to
`
`implement Erickson’s TCP functionality for the validation of layer headers by
`
`Erickson’s network interface device. Id. Patent owner does not address header
`
`validation by this combination.
`
`Alteon’s “interrupt timer” discloses the use of fewer than one interrupt per
`
`processed packet. Patent Owner argues that the interrupts are limited to data copy
`
`related interrupts, implying that there are additional, undisclosed interrupts present.
`
`Paper 34 at 33. But there is no such limitation in the Alteon disclosure, and no
`
`such undisclosed interrupts. Ex. 1033 at .022 (“. . .Alteon’s Gigabit Ethernet
`
`technology not only reduces the number of times data is copied . . ., it allows a
`
`single interrupt to be issued for multiple data packets . . .”). Patent Owner goes on
`
`to argue that a copy operation does not implicate validation and that traditionally
`
`the protocol stack validates the packet on the host. Paper 34 at 33. Not only is the
`
`protocol stack on the network adapter in Petitioner’s proposed combination, but
`
`5
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`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`Alteon itself discloses “Off-loading TCP/IP checksum,” validating TCP/IP headers
`
`by a network adapter, in the very next sentence. Ex. 1033 at .022.
`
`Even if Alteon did not teach that packet processing with fewer than one
`
`interrupt per packet was known—which it clearly does—the combination of
`
`Erickson and Tanenbaum96 alone still teaches this limitation. As explained by Dr.
`
`Horst, the existence of the TCP entity on the network interface device necessitates
`
`that the checksum would have been validated by the network interface device. Ex.
`
`1003, ¶¶ 69, 91, 100, 149. Thus, there is no reason to interrupt the processing of
`
`the host computer receiving the transmission. See Paper 11 at 19 (the Board
`
`applying similar reasoning to transmission for Claim 17). Erickson also discloses
`
`polling status registers in shared memory space to manage host and network
`
`adapter interaction, an approach that a POSA would have understood does not
`
`require interrupts. Ex. 1223, ¶¶ 50-52.
`
`Importantly, Patent Owner’s alleged priority application admits that fewer
`
`than one interrupt per received packet was normal in the prior art. When
`
`discussing the alleged problems in the prior art, the 1997 Provisional notes that
`
`“[a] 64k SMB request . . . is typically made up of 44 TCP segments” and that if
`
`“we assume 4 incoming frames per input, and an acknowledgement for every 2
`
`segments, . . . we are still left with 33 interrupts . . .” Ex. 1031 at .006. Thus, even
`
`Patent Owner’s alleged priority application admits that the prior art employed
`
`6
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`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`fewer than one interrupt for each received segment (33 interrupts for 44 segments).
`
`Ex. 1223, ¶¶ 53-56. A significant fraction (11 packets) were received without any
`
`interrupts to the host. There are simply not enough interrupts to interrupt
`
`validation of the transport and network layer headers of each packet. At least some
`
`must be validated without being divided by an interrupt. Ex. 1223, ¶¶ 53-61.
`
`B.
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That The
`Prior Art Discloses Sending the Data From Each Packet to a
`Destination in Memory Without Sending Any of the Headers
`(Claim 1)
`Patent Owner argues that because Alteon discloses the transfer of header
`
`information to the protocol stack on the host, the proposed combination does not
`
`disclose this limitation. Again, Patent Owner just “attacks [the] references
`
`individually” and fails to “respon[d] to the Petitioner’s assertions.” Paper 11 at 14.
`
`As stated above, in the combination of Erickson in view of Tanenbaum96
`
`and Alteon, Tanenbaum96’s “fast path” header prediction TCP/IP processing is
`
`performed by Erickson’s interface. Alteon also teaches the transfer of data without
`
`headers from the protocol stack (which, in the combination, is on the network
`
`adapter for the “fast path”) to the application (which is on the host). Pet. at 58; Ex.
`
`1223, ¶ 29. Because this transfer is without headers, the combination discloses the
`
`transfer of data from each packet to a destination in host memory without the
`
`headers. Pet. at 56-58; Ex. 1223, ¶ 29.
`
`7
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`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`C.
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That The
`Prior Art Discloses Processing MAC Layer Headers without an
`Interrupt (Claim 2)
`As discussed above, the Board recognized that Petitioner relies on Erickson
`
`in view of Tanenbaum96, not Alteon, to teach that the validation of headers is done
`
`by Erickson’s network interface device and not the host computer. Erickson
`
`discloses the use of Ethernet headers (MAC headers) in Figure 6. Ex. 1005. Thus,
`
`for the same reasons as above that the combination teaches that the TCP and IP
`
`headers are validated without an interrupt to the host, the MAC and IP layer
`
`headers are validated without an interrupt to the host. See Pet. at 58.
`
`D.
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That The
`Prior Art Discloses Processing an Upper Layer Header by a
`Second Mechanism (Claim 3)
`As explained in the Petition, Tanenbaum96 discloses the processing of the
`
`upper layer headers on the host such as SMTP or electronic mail headers. Pet. at
`
`59-60. The Patent Owner’s Response ignores this. The Board recognized that
`
`Petitioner relies on Erickson in view of Tanenbaum96 to teach that the validation
`
`of transport layer and network headers is done by the interface and not the host
`
`computer. Paper 11 at 14. Once the network and transport layer headers are
`
`removed and the data is transferred to the host, the host processes the upper layer
`
`headers. Pet. at 59. Tanenbaum96 discloses this in its discussion of different
`
`application headers. Ex. 1006 at .055, Fig. 1-19.
`
`8
`
`

`

`Case IPR2017-01392
`U.S. Patent No. 7,337,241
`
`E.
`
`Patent Owner Has Failed to Rebut Petitioner’s Showing That
`Prior Art Discloses Sorting the Packets by Classifying Each as
`Having IP and TCP Headers (Claim 6)
`Patent Owner’s only argument that the limitations of claim 6 are not
`
`disclosed by the combination of Erickson, Tanenbaum96, and Alteon is that it was
`
`not enabled for TCP implementations. Paper 34 at 42. For the same reasons
`
`discussed above, the proposed combination discloses a TCP implementation.
`
`IV. PATENT OWNER HAS FAILED TO REBUT PETITIONER’S
`SHOWING THAT ERICKSON, TANENBAUM96, AND ALTEON
`REFERENCES SHOULD BE COMBINE