throbber
Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 1 of 139 PageID #: 2233
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
`
`
`ALACRITECH, INC.,
`
`Plaintiff,
`
`v.
`
`CENTURYLINK, INC., et al.,
`
`Defendants.
`
`
`
`Civil Action No. 2:16-cv-693-JRG
`
`JURY TRIAL DEMANDED
`
`
`
`
`
`
`
`
`
`
`ANSWER AND COUNTERCLAIMS TO
`
`INTEL CORPORATION’S COMPLAINT IN INTERVENTION
`
`Plaintiff Alacritech, Inc. (“Alacritech”) responds to Intervenor Intel Corporation’s
`
`(“Intel”) Complaint in Intervention as follows. Any allegation Alacritech does not expressly
`
`admit should be deemed denied.
`
`PARTIES
`
`1.
`
`Alacritech admits that Intel purports to seek declaratory judgment of non-
`
`infringement in its Complaint in Intervention. Alacritech denies the remaining allegations of
`
`Paragraph 1 of the Complaint in Intervention.
`
`2.
`
`Alacritech is without knowledge or information sufficient to form a belief as to
`
`the truth of the allegations of Paragraph 2 of the Complaint in Intervention, and therefore denies
`
`them.
`
`3.
`
`4.
`
`Alacritech admits the allegations of Paragraph 3 of the Complaint in Intervention.
`
`Alacritech admits that it has brought patent claims against Defendant Dell, Inc.
`
`(“Dell”) in this action under 35 U.S.C. §§ 101 et seq, and that this Court has subject matter
`
`jurisdiction over those claims pursuant to 28 U.S.C. §§ 1331 and 1338(a). Alacritech is without
`
`
`
`1
`
`INTEL EX. 1231.001
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 2 of 139 PageID #: 2234
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`knowledge or information sufficient to form a belief as to the truth of the remaining allegations
`
`of Paragraph 4 of the Complaint in Intervention, and therefore denies them.
`
`5.
`
`Alacritech admits the allegations of Paragraph 5 of the Complaint in Intervention.
`
`BACKGROUND AND INTEL’S INTEREST IN THIS LAWSUIT
`
`6.
`
`Alacritech admits that on June 30, 2016, it filed its Complaint in this action
`
`accusing Dell of making, using, selling, offering to sell and/or importing Dell products and
`
`services that infringe United States Patent Nos. 7,124,205; 7,237,036; 7,337,241; 7,673,072;
`
`7,945,699; 8,131,880; 8,805,948; and 9,055,104 (respectively, the ‘205 Patent, the ‘036 Patent,
`
`the ‘241 Patent, the ‘072 Patent, the ‘699 Patent, the ‘880 Patent, the ‘948 Patent, and the ‘104
`
`Patent; collectively, the “Asserted Patents”). Alacritech is without knowledge or information
`
`sufficient to form a belief as to the truth of the remaining allegations of Paragraph 6 of the
`
`Complaint in Intervention, and therefore denies them.
`
`7.
`
`8.
`
`Alacritech admits the allegations of Paragraph 7 of the Complaint in Intervention.
`
`Alacritech admits that some of Alacritech’s allegations under the Asserted Patents
`
`are directed against infringing Dell products and services that have certain Intel component’s.
`
`Alacritech denies the remaining allegations of Paragraph 8 of the Complaint in Intervention.
`
`9.
`
`Alacritech admits that its Complaint alleges that Dell infringes certain of the
`
`asserted patents by making, using, selling, offering for sale, and/or importing Dell products and
`
`services that have the Intel Ethernet Network Daughter Card X520-DA2/I350-T2 as a
`
`component, among other components. Alacritech further admits that its infringement allegations
`
`are based, in part, on Dell products and services that have the Intel 82599 Ethernet Controller as
`
`a component, among other components, and that the Intel 82599 Datasheet is cited in
`
`
`
`2
`
`INTEL EX. 1231.002
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 3 of 139 PageID #: 2235
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`Alacritech’s Complaint. Alacritech denies the remaining allegations of Paragraph 9 of the
`
`Complaint in Intervention.
`
`10.
`
`Alacritech is without knowledge or information sufficient to form a belief as to
`
`the truth of the allegations of Paragraph 10 of the Complaint in Intervention, and therefore denies
`
`them.
`
`11.
`
`Alacritech is without knowledge or information sufficient to form a belief as to
`
`the truth of the allegations of Paragraph 11 of the Complaint in Intervention, and therefore denies
`
`them.
`
`COUNT 1
`
`DECLARATORY JUDGMENT REGARDING U.S. PATENT NO. 7,124,205
`
`12.
`
`Alacritech incorporates by reference Paragraphs 1-11 of this Answer as if set forth
`
`fully here.
`
`13.
`
`Alacritech denies the allegations of Paragraph 13 of the Complaint in
`
`Intervention.
`
`14.
`
`Alacritech denies the allegations of Paragraph 14 of the Complaint in
`
`Intervention.
`
`15.
`
`Alacritech denies the allegations of Paragraph 15 of the Complaint in
`
`Intervention.
`
`16.
`
`Alacritech denies the allegations of Paragraph 16 of the Complaint in
`
`Intervention.
`
`COUNT II
`
`DECLARATORY JUDGMENT REGARDING U.S. PATENT NO. 7,237,036
`
`
`
`3
`
`INTEL EX. 1231.003
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 4 of 139 PageID #: 2236
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`17.
`
`Alacritech incorporates by reference Paragraphs 1-16 of this Answer as if set forth
`
`fully here.
`
`18.
`
`Alacritech denies the allegations of Paragraph 18 of the Complaint in
`
`Intervention.
`
`19.
`
`Alacritech denies the allegations of Paragraph 19 of the Complaint in
`
`Intervention.
`
`20.
`
`Alacritech denies the allegations of Paragraph 20 of the Complaint in
`
`Intervention.
`
`21.
`
`Alacritech denies the allegations of Paragraph 21 of the Complaint in
`
`Intervention.
`
`COUNT III
`
`DECLARATORY JUDGMENT REGARDING U.S. PATENT NO. 7,337,241
`
`22.
`
`Alacritech incorporates by reference Paragraphs 1-21 of this Answer as if set forth
`
`fully here.
`
`23.
`
`Alacritech denies the allegations of Paragraph 23 of the Complaint in
`
`Intervention.
`
`24.
`
`Alacritech denies the allegations of Paragraph 24 of the Complaint in
`
`Intervention.
`
`25.
`
`Alacritech denies the allegations of Paragraph 25 of the Complaint in
`
`Intervention.
`
`26.
`
`Alacritech denies the allegations of Paragraph 26 of the Complaint in
`
`Intervention.
`
`COUNT IV
`
`
`
`4
`
`INTEL EX. 1231.004
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 5 of 139 PageID #: 2237
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`DECLARATORY JUDGMENT REGARDING U.S. PATENT NO. 7,673,072
`
`27.
`
`Alacritech incorporates by reference Paragraphs 1-26 of this Answer as if set forth
`
`fully here.
`
`28.
`
`Alacritech denies the allegations of Paragraph 28 of the Complaint in
`
`Intervention.
`
`29.
`
`Alacritech denies the allegations of Paragraph 29 of the Complaint in
`
`Intervention.
`
`30.
`
`Alacritech denies the allegations of Paragraph 30 of the Complaint in
`
`Intervention.
`
`31.
`
`Alacritech denies the allegations of Paragraph 31 of the Complaint in
`
`Intervention.
`
`COUNT VI
`
`DECLARATORY JUDGMENT REGARDING U.S. PATENT NO. 8,131,880
`
`32.
`
`Alacritech incorporates by reference Paragraphs 1-31 of this Answer as if set forth
`
`fully here.
`
`33.
`
`Alacritech denies the allegations of Paragraph 33 of the Complaint in
`
`Intervention.
`
`34.
`
`Alacritech denies the allegations of Paragraph 34 of the Complaint in
`
`Intervention.
`
`35.
`
`Alacritech denies the allegations of Paragraph 35 of the Complaint in
`
`Intervention.
`
`36.
`
`Alacritech denies the allegations of Paragraph 36 of the Complaint in
`
`Intervention.
`
`
`
`5
`
`INTEL EX. 1231.005
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 6 of 139 PageID #: 2238
`
`COUNT VII
`
`DECLARATORY JUDGMENT REGARDING U.S. PATENT NO. 8,805,948
`
`37.
`
`Alacritech incorporates by reference Paragraphs 1-36 of this Answer as if set forth
`
`fully here.
`
`38.
`
`Alacritech denies the allegations of Paragraph 38 of the Complaint in
`
`Intervention.
`
`39.
`
`Alacritech denies the allegations of Paragraph 39 of the Complaint in
`
`Intervention.
`
`40.
`
`Alacritech denies the allegations of Paragraph 40 of the Complaint in
`
`Intervention.
`
`41.
`
`Alacritech denies the allegations of Paragraph 41 of the Complaint in
`
`Intervention.
`
`COUNT VIII
`
`DECLARATORY JUDGMENT REGARDING U.S. PATENT NO. 9,055,104
`
`42.
`
`Alacritech incorporates by reference Paragraphs 1-41 of this Answer as if set forth
`
`fully here.
`
`43.
`
`Alacritech denies the allegations of Paragraph 43 of the Complaint in
`
`Intervention.
`
`44.
`
`Alacritech denies the allegations of Paragraph 44 of the Complaint in
`
`Intervention.
`
`45.
`
`Alacritech denies the allegations of Paragraph 45 of the Complaint in
`
`Intervention.
`
`
`
`6
`
`INTEL EX. 1231.006
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 7 of 139 PageID #: 2239
`
`46.
`
`Alacritech denies the allegations of Paragraph 46 of the Complaint in
`
`Intervention.
`
`REQUEST FOR RELIEF
`
`Alacritech denies that Intel is entitled to any of the relief requested in its Request for
`
`Relief.
`
`DEMAND FOR JURY TRIAL
`
`Alacritech admits that Intel demands a trial by jury on all issues so triable in this action.
`
`Alacritech also demands a trial by jury on all issues so triable.
`
`
`
`
`
`7
`
`INTEL EX. 1231.007
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 8 of 139 PageID #: 2240
`
`
`
`COUNTERCLAIMS FOR PATENT INFRINGEMENT
`
`In these counterclaims for patent infringement under 35 U.S.C. § 271 in response to Intel
`
`Corporation’s (“Intel”) intervention in Case No. 2:16-cv-00692 to defend Dell, Plaintiff
`
`Alacritech, Inc. (“Alacritech”), by and through its undersigned counsel, complains and alleges as
`
`follows against Intervenor Intel, based on Alacritech’s own personal knowledge and upon
`
`information and belief with respect to Intel’s actions:
`
`THE PARTIES
`
`1.
`
`Alacritech is a California corporation with its principal place of business at P.O.
`
`Box 20307, San Jose, California 95160.
`
`2.
`
`Intel is a Delaware corporation with its principal place of business in Santa Clara,
`
`California.
`
`NATURE OF THE ACTION
`
`3.
`
`This is a civil action for patent infringement arising under the patent laws of the
`
`United States, 35 U.S.C. § 1, et seq.
`
`4.
`
`Intel has infringed and continues to infringe, has contributed to and continues to
`
`contribute to the infringement of, and has actively induced and continues to actively induce
`
`others to infringe the following Alacritech patents: U.S. Patent Numbers 7,124,205; 7,237,036;
`
`7,337,241; 7,673,072; 7,945,699; 8,131,880; 8,805,948; and 9,055,104 (collectively, the
`
`“Asserted Patents”). Alacritech is the legal owner by assignment of the Asserted Patents, which
`
`were all duly and legally issued by the United States Patent and Trademark Office. Alacritech
`
`seeks injunctive relief and monetary damages.
`
`
`
`8
`
`INTEL EX. 1231.008
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 9 of 139 PageID #: 2241
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`JURISDICTION AND VENUE
`
`5.
`
`This is a civil action for patent infringement arising under the patent laws of the
`
`United States, 35 U.S.C. § 1, et seq., including § 271. This Court has subject matter jurisdiction
`
`over this action under 28 U.S.C. §§ 1331 and 1338(a).
`
`6.
`
`This Court has personal jurisdiction over Intel because, among other reasons, of
`
`Intel’s filing of its Complaint in Intervention in this action, and Intel’s Motion to Intervene
`
`whereby Intel expressly asked this Court for the opportunity to adjudicate its declaratory
`
`judgment claims in this District, and because of this Court’s grant of Intel’s request.
`
`7.
`
`In addition, Intel regularly conducts business in Texas, including in this District,
`
`and Intel has committed and continues to commit direct and indirect acts of patent infringement
`
`complained of herein within this District and elsewhere in Texas and the United States. For
`
`example, Intel maintains facilities in Austin, Texas. In addition, Intel advertises, sells, and
`
`provides its products and services, including infringing products and services complained of
`
`herein, directly to businesses and consumers in this District. As such, Intel has purposefully
`
`availed itself of the privilege of conducting business within this District, has established
`
`sufficient minimum contacts with this District such that Intel should reasonably and fairly
`
`anticipate being haled into this Court, and has purposefully directed activities at residents in this
`
`District, wherein at least a portion of the claims alleged herein arise out of or are related to those
`
`activities.
`
`8.
`
`Venue is proper in this District under 28 U.S.C. §§ 1391(b)-(c) and 1400(b) at
`
`least because, as discussed above, Intel is subject to personal jurisdiction in this District,
`
`regularly conducts business in this District, and has committed and continues to commit direct
`
`and indirect acts of patent infringement complained of herein within this District.
`
`
`
`9
`
`INTEL EX. 1231.009
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 10 of 139 PageID #: 2242
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`FACTUAL BACKGROUND
`
`Alacritech’s History
`
`9.
`
`Alacritech was founded in 1997 by technology pioneer Larry Boucher, the creator
`
`and author of the original Small Computer System Interface (“SCSI”) specification and a
`
`visionary, award-winning leader in server adapter, storage and networking technologies.
`
`10. Mr. Boucher has more than 50 years of experience in the industry. Following a
`
`twelve-year tenure in IBM’s Storage Division, he served as director of design services at Shugart
`
`Associates, where he developed the Shugart Associates System Interface (“SASI”) and then
`
`SCSI, the industry standard for connecting storage and other peripherals to PCs and servers. In
`
`1981, Mr. Boucher founded Adaptec, Inc., which became a global leader for host adapters and
`
`other innovative storage solutions. After taking Adaptec public, Mr. Boucher founded Auspex
`
`Systems, Inc., a manufacturer of enterprise servers, where he pioneered the networked file
`
`system design that is the basis of today’s network-attached storage (“NAS”) model. In 1997,
`
`Mr. Boucher founded Alacritech.
`
`11.
`
` Mr. Boucher and other innovators at Alacritech (including Peter Craft, Clive
`
`Philbrick, Stephen Blightman, David Higgen, and Daryl Starr) foresaw the convergence of
`
`storage and networking and, as a result, the enormous processing demands that would be placed
`
`on host computer CPUs in order to move and store large quantities of data within a network,
`
`creating bottlenecks and reducing CPU processing power available for performing more
`
`substantive computing tasks. To solve this impending problem, the Alacritech team pioneered a
`
`series of fundamental network acceleration technologies, including but not limited to techniques
`
`for streamlining, bypassing and/or offloading aspects of conventional network protocol
`
`processing from host CPUs to “intelligent” network interface devices (sometimes called
`
`“NIDs”). These technologies are critical to modern network computing, dramatically increasing
`
`
`
`10
`
`INTEL EX. 1231.010
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 11 of 139 PageID #: 2243
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`the speed and efficiency with which data is transferred and stored, while reducing the associated
`
`processing burden imposed on host CPUs.
`
`12. Working with industry partners, Alacritech released a number of network and
`
`storage products related to the technologies it developed. For example, Alacritech produced a
`
`series of Scalable Network Accelerators (also referred to as TCP Offload Engine (TOE) Network
`
`Interface Cards (TNICs)) and the ANX 1500, a sophisticated Network File System (NFS)
`
`Throughput Acceleration Appliance for use with Network-Attached Storage (NAS) systems.
`
`Alacritech’s Asserted Patents
`
`13.
`
`Network computing is ubiquitous in contemporary society. It enables the
`
`dissemination of information and digital content to people around the world, and it is a critical
`
`component of the modern information economy. Many businesses have their own data centers
`
`(made up of large numbers of networked servers) that they use for the remote storage,
`
`management, processing, and/or distribution of their data. And a lucrative and rapidly-growing
`
`industry has developed to provide cloud computing services, which essentially allow businesses
`
`(and consumers) to offload their data to shared, third-party data centers.
`
`14.
`
`However, as growing volumes of data are moved across networks of increasing
`
`complexity and bandwidth, more and more of the processing power of the servers (and/or other
`
`computers) in a network is consumed by simply moving and storing the data, greatly diminishing
`
`the ability of the servers to perform other more substantive tasks. In addition, bottlenecks
`
`develop when there is insufficient processing power available to transfer data, and the data
`
`cannot be moved as quickly or efficiently as desired. The Alacritech team foresaw these
`
`problems years ago and, to address them, they developed and patented a collection of innovative
`
`network acceleration techniques that dramatically speed up the transfer and storage of data, and
`
`
`
`11
`
`INTEL EX. 1231.011
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 12 of 139 PageID #: 2244
`
`decrease the corresponding processing demands on servers. Alacritech holds 71 United States
`
`patents covering its groundbreaking inventions.
`
`15.
`
` Conventionally, computers connected over a network rely on a multi-layered
`
`software architecture to transfer and store data. The architecture (also called a protocol stack) is
`
`generally based on one or more specifications and/or protocols, such as TCP/IP (a protocol suite
`
`including the Transmission Control Protocol (“TCP”) and Internet Protocol (“IP”)). Depending
`
`on the specifications and/or protocols at issue, the architecture may include up to seven different
`
`layers described by the Open Systems Interconnection (OSI) model (listed, in order, from highest
`
`to lowest): the application layer, the presentation layer, the session layer, the transport layer, the
`
`network layer, the data link layer, and the physical layer. Each software layer performs different
`
`functions associated with transferring and storing data.
`
`16.
`
`In order to prepare data for transmission over a network, a sending computer must
`
`process the data through each layer of the protocol stack (working from highest to lowest). At
`
`each layer, the sending computer must perform further processing on the data resulting from
`
`processing by the previous layer, such as preparing and attaching a new header containing
`
`associated metadata. In the transport layer, the sending computer must also divide the data up
`
`into units (e.g., packets) that are small enough to be transmitted over the network medium.
`
`Likewise, a receiving computer must process incoming data through each layer of the same
`
`protocol stack (working from lowest to highest) before it can be used by host applications on the
`
`receiving computer. At each layer, the receiving computer must perform further processing on
`
`the data resulting from processing by the previous layer, such as removing and processing an
`
`additional header and, in the transport layer, combining multiple units of data together in
`
`
`
`12
`
`INTEL EX. 1231.012
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 13 of 139 PageID #: 2245
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`memory. In both the sending and receiving operations, the computer may move and/or make a
`
`new copy of the data each time another layer is processed.
`
`17.
`
`This conventional approach for transferring and storing data within a network,
`
`while functional, is also slow and highly inefficient. Too much of the processing power of a
`
`computer’s CPU is wasted performing brute-force, layer-by-layer processing. Recognizing these
`
`inefficiencies early on, the Alacritech team developed sophisticated solutions that greatly
`
`improve upon the conventional approach. Central to these solutions is Alacritech’s pioneering
`
`use of dedicated NIDs to efficiently handle optimal portions of the processing associated with
`
`sending, receiving, and storing data, particularly for complicated multi-layer protocol suites that
`
`use variable-length units of data with multiple headers, such as TCP/IP.
`
`18.
`
`Others in the industry attempted solutions that involved offloading essentially all
`
`processing associated with data communications to a NID, completely bypassing the host CPU,
`
`but they were unable to develop effective solutions that were suitable for TCP/IP and other more
`
`complicated protocol suites involving maintenance of state and variable-length data units with
`
`multiple headers, situations in which it is important that the host CPU remains involved in the
`
`processing. Still others in the industry attempted solutions involving offload of discrete TCP/IP
`
`processing tasks to a NID, but they were only able to offload very limited tasks, such as
`
`checksum processing, that did not significantly reduce the processing burden on the host CPU.
`
`19.
`
`Only Alacritech solved the problem of how to efficiently offload large portions of
`
`communications processing to NIDs implementing TCP/IP and other more complicated protocol
`
`suites. By offloading processing tasks to a dedicated NID in accordance with the solutions
`
`provided by the Asserted Patents, transfer of data between devices is accelerated and the host
`
`CPUs retain dramatically more processing power to perform other more substantive tasks,
`
`
`
`13
`
`INTEL EX. 1231.013
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 14 of 139 PageID #: 2246
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`without sacrificing the flexibility and control necessary to implement a complicated protocol
`
`suite such as TCP/IP. Some of the innovative solutions and techniques developed by Alacritech
`
`and claimed by the Asserted Patents are discussed below.
`
`20.
`
`Some of the Asserted Patents provide solutions that increase efficiency of
`
`network computing by using multiple paths to process received data, whereby an intelligent NID
`
`uses criteria (e.g., provided by the host CPU) to determine whether incoming data should be
`
`processed directly by the NID (e.g., using a “fast-path”), or whether it should be passed to and
`
`processed by the host CPU in the conventional manner (e.g., using a “slow-path”). This
`
`substantially reduces the burden on the host CPU, while retaining its flexibility and control for
`
`handling exceptions and other complicated processing tasks. And, because the NID is
`
`specifically designed to perform these operations (usually in hardware), it can perform them
`
`more efficiently and more quickly than a host CPU.
`
`21.
`
`Alacritech also pioneered techniques that allow NIDs to transfer and store data
`
`more quickly and efficiently. For example, some of the Asserted Patents provide solutions
`
`through which NIDs transfer data to and from host memory associated with upper layer (e.g.,
`
`application layer) software, without unit-by-unit lower-layer processing by the host CPU and
`
`without excessive intermediate copying of data in a series of intermediate buffers and/or caches.
`
`In this way, data can be transferred to the network or the host memory directly by the NID,
`
`without substantial processing by the host CPU or excessive intermediate copying, resulting in
`
`much faster and more efficient transfer and storage of data.
`
`22.
`
`As another example, some of the Asserted Patents provide solutions for more
`
`efficiently preparing and sending data over a network. For example, the NID uses information
`
`(e.g., provided by the host CPU) to divide data up into smaller units for transmission, and to
`
`
`
`14
`
`INTEL EX. 1231.014
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 15 of 139 PageID #: 2247
`
`generate and attach multiple lower-layer headers to the units of data. Moreover, it does so in
`
`essentially a single operation, without the brute-force, layer-by-layer processing (and associated
`
`copying) required to carry out the same tasks under the conventional approach described above.
`
`These solutions greatly reduce processing by the host CPU associated with sending data, and
`
`they allow the NID to prepare and transmit data more efficiently.
`
`23.
`
`Similarly, some of the Asserted Patents provide solutions for more efficiently
`
`processing data received from a network. For example, the NID removes and processes the
`
`lower-layer headers from related units of data, without the brute-force processing of those
`
`headers required under the conventional approach described above. In addition, the NID may
`
`combine processed data units into a single payload of data that it delivers to host memory. These
`
`solutions greatly reduce processing by the host CPU associated with receiving and storing data,
`
`and they allow the NID to receive and process data more efficiently.
`
`24.
`
`The Asserted Patents are a product of Alacritech’s extensive research and
`
`development, reflecting groundbreaking innovations that are found throughout modern networks,
`
`especially large-scale and/or high-end networks such as those used in data centers.
`
`25.
`
`The technologies covered by Alacritech’s Asserted Patents are critical to
`
`fundamental network and/or storage acceleration techniques, including Large Segment Offload
`
`(“LSO”) (also called Large Send Offload or Generic Segmentation Offload), Receive Side
`
`Coalescing (“RSC”) (also called Receive Segment Coalescing, Large Receive Offload, or
`
`Generic Receive Offload), and TCP Offload Engine (“TOE”). They are also essential to many
`
`network and/or storage protocols that incorporate Remote Direct Memory Access (“RDMA”),
`
`such as the InfiniBand protocol, the RDMA over Converged Ethernet (“RoCE”) protocol, the
`
`Internet Wide Area RDMA Protocol (“iWARP”), the Internet Small Computer System Interface
`
`
`
`15
`
`INTEL EX. 1231.015
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 16 of 139 PageID #: 2248
`
`(“iSCSI”) Extensions for RDMA (“iSER”) protocol, and the Server Message Block (“SMB”)
`
`Direct protocol.
`
`26. Without
`
`the benefit of Alacritech’s groundbreaking
`
`inventions, modern
`
`computing networks (especially large-scale and/or high-performance networks) would be
`
`significantly slower and less efficient (and, therefore, more expensive and less useful) than they
`
`are today.
`
`Intel’s Infringing Technologies
`
`27.
`
`Intel uses the Alacritech’s patented technologies that Alacritech asserted against
`
`Dell and the other Defendants in this consolidated action which Intel identified as the basis of its
`
`intervention across many different parts of its business, including in the network adapters,
`
`network controllers, and other network products that it makes, uses and/or sells, and in the
`
`associated consulting and support services that it provides to its customers. Intel’s use of these
`
`technologies infringes the Asserted Patents directly, and also induces and contributes to
`
`infringement of the Asserted Patents by its customers.
`
`28.
`
`Intel makes, uses, sells, and/or provides technical support for a variety of network
`
`products that infringe the Asserted Patents, including network controllers (e.g., the Intel Ethernet
`
`controller XL710 family), network adapters (e.g., the Intel Ethernet converged network adapter
`
`X540), and other network interface devices. See, e.g., “Intel Ethernet Controllers,” available at
`
`http://www.intel.com/content/www/us/en/ethernet-products/controllers/overview.html.
`
`29.
`
`A large and growing portion of Intel’s revenue is tied to the infringing network
`
`products and services described above. Without the benefit of Alacritech’s patented
`
`technologies, the infringing network products and services Intel provides would cost
`
`
`
`16
`
`INTEL EX. 1231.016
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 17 of 139 PageID #: 2249
`
`substantially more and/or suffer a significant degradation in performance, hurting Intel’s
`
`business as a result.
`
`COUNT I
`
`INFRINGEMENT OF U.S. PATENT NO. 7,124,205
`
`30.
`
`Alacritech re-alleges and incorporates by reference each of the allegations of the
`
`paragraphs set forth above as though fully set forth herein.
`
`31.
`
`Alacritech is the current exclusive owner and assignee of all right, title, and
`
`interest in and to U.S. Patent No. 7,124,205 (the “‘205 patent”), titled “Network Interface Device
`
`that Fast-Path Processes Solicited Session Layer Read Commands,” duly and legally issued by
`
`the United States Patent and Trademark Office on October 17, 2006, including the right to bring
`
`this suit for injunctive relief and damages. A true and correct copy of the ‘205 patent is attached
`
`hereto as Exhibit A.
`
`32.
`
`33.
`
`The ‘205 patent is valid and enforceable.
`
`Intel has directly infringed and is currently directly infringing the ‘205 patent by
`
`making, using, selling, offering for sale, and/or importing into the United States, without
`
`authority, products, methods, equipment, and/or services that practice one or more claims of the
`
`‘205 patent in connection with infringing RSC functionality, including but not limited to the Intel
`
`82599EB 10 Gigabit Ethernet Controller; Intel 82599EN 10 Gigabit Ethernet Controller; Intel
`
`82599ES 10 Gigabit Ethernet Controller; Intel Ethernet Controller X540-AT2; Intel Ethernet
`
`Controller X540-BT2; Intel Ethernet Controller X550-AT; Intel Ethernet Controller X550-AT2;
`
`Intel Ethernet Controller X550-BT2; Intel Ethernet Controller X710-AM2; Intel Ethernet
`
`Controller X710-BM2; Intel Ethernet Controller XL710-AM1; Intel Ethernet Controller XL710-
`
`AM2; Intel Ethernet Controller XL710-BM1; Intel Ethernet Controller XL710-BM2; Intel
`
`Network Daughter Card X520-DA2 /1350-T2; Intel Network Daughter Card X540-T2 /1350-T2;
`
`
`
`17
`
`INTEL EX. 1231.017
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 18 of 139 PageID #: 2250
`
`Intel Ethernet Converged Network Adapter X520-DA2; Intel Ethernet Converged Network
`
`Adapter X520-LR1; Intel Ethernet Converged Network Adapter X520-QDA1; Intel Ethernet
`
`Converged Network Adapter X520-SR1; Intel Ethernet Converged Network Adapter X520-SR2;
`
`Intel Ethernet Converged Network Adapter X540-T1; Intel Ethernet Converged Network
`
`Adapter X540-T2; Intel Ethernet Converged Network Adapter X550-T1; Intel Ethernet
`
`Converged Network Adapter X550-T2; Intel Ethernet Converged Network Adapter X710-DA2;
`
`Intel Ethernet Converged Network Adapter X710-DA4; Intel Ethernet Converged Network
`
`Adapter X710-DA4 FH; Intel Ethernet Converged Network Adapter XL710-QDA1; Intel
`
`Ethernet Converged Network Adapter XL710-QDA2; Intel Ethernet Server Adapter I340-F4;
`
`Intel Ethernet Server Adapter I340-T2; Intel Ethernet Server Adapter I340-T4; Intel Ethernet
`
`Server Adapter X520-DA1 for Open Compute Project; Intel Ethernet Server Adapter X520-
`
`DA2; Intel Ethernet Server Adapter X520-DA2 for Open Compute Project; Intel Ethernet Server
`
`Adapter XL710-QDA1 for Open Compute Project; Intel Ethernet Server Adapter XL710-QDA2
`
`for Open Compute Project; Intel Ethernet Server Bypass Adapter X520-LR2; Intel Ethernet
`
`Server Bypass Adapter X520-SR2; Intel Ethernet Server Bypass Adapter X540-T2; Intel
`
`Ethernet Connection X557-AT; Intel Ethernet Connection X557-AT2; Intel Ethernet Connection
`
`X557-AT4; any other activities, products and/or services involving the products identified above;
`
`and any other activities, products and/or services that practice and/or support similarly infringing
`
`RSC functionality (collectively, “the ‘205 Accused Products”). The ‘205 Accused Products are
`
`non-limiting examples that were identified based on publicly available information, and
`
`Alacritech reserves the right to identify additional infringing activities, products and services,
`
`including, for example, on the basis of information obtained during discovery.
`
`
`
`18
`
`INTEL EX. 1231.018
`
`

`

`Case 2:16-cv-00693-JRG-RSP Document 94 Filed 12/13/16 Page 19 of 139 PageID #: 2251
`
`34.
`
`As just one non-limiting example, set forth below (with claim language in italics)
`
`is a description of Intel’s infringement of exemplary claim 35 of the ‘205 patent in connection
`
`with the Intel 82599EB 10 Gigabit Ethernet Controller. This description is based on publicly
`
`available information. Alacritech reserves the right to modify this description, including, for
`
`example, on the basis of information about the ‘205 Accused Products that it obtains during
`
`discovery.
`
`35 A host bus adapter that is adapted for sending an ISCSI solicited read request and for
`
`receiving a response in return, the host bus adapter also being adapted for coupling to a host
`
`computer that has a protocol stack, the protocol stack having an ISCSI layer, the host bus
`
`adapter being adapted for processing the response such that a data portion of the response is
`
`placed into a memory on the host compu

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