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`T E C ff N I C A L Brltf
`
`Table of Contents
`
`• Introduction
`• Goals of Gigabit Ethernet
`• !hes of Gigabit Ethernet
`• Gigabit Ethernet History and Momentum
`
`• Miarating to rn·gabit Ethernet
`
`• Protocol Architecll!.rSl
`• Cabling Types and Distances
`• Flow Control
`• Technology Advances
`• Next Generation NICs and Switches
`• Conclusion
`
`Flow Control
`The flow control mechanism for Ethernet networks is different for full-duplex and
`half-duplex transmission types. The next section discusses these two transmission
`schemes, and the flow control mechanisms for each.
`
`Full-Duplex Transmission
`Using full-duplex transmission, ·signals travel in both directions on the same
`connection, at the same time. Simultaneous bi-directional transmission allows the
`aggregate data rate of an Ethernet network to be doubled. For example, a 1 OMbps
`Ethernet network can achieve an aggregate 20Mbps data rate, a 1 OOMbps Fast
`Ethernet network can achieve an aggregate 200Mbps, and a lOOOMbps Gigabit
`Ethernet network can achieve and aggregate 2Gbps data rate.
`
`Full-duplex transmission is available for point-to-point connections onJy. Using
`full-duplex transmission, the issue of collisions on the network is completely
`eliminated and the CSMNCD access control mechanism does not need to be
`invoked. Full-duplex can be used between a single workstation and a switch port,
`between two switch ports, or between two workstations. Full-duplex cannot be used
`for shared port connections, such as a repeater or hub port connecting to multiple
`workstations. Figure 1 O shows a full-duplex, point-to-point network.
`
`INTEL EX. 1221.001
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`Figure I 0. Full.duplex, point.to-point Ethernet segments
`
`An optional flow control mechanism being defined by IEEE 802.Jx, is available for
`full-duplex transmission and works in a way similar to XON/X:OFF flow control. A
`receiving station at one end of the point-to-point connection can send a packet to the
`sending station at the opposite end of the connection instructing the sending station
`to stop sending packets for a specified period of time. The sending station ceases to
`transmit packets until the period of time has passed, or until it receives a new packet
`from the receiving station with a time of zero, indicating that it i's okay to resume
`transmission.
`
`Full-duplex Ethernet is being standardized by the IEEE 802.3x committee. The
`full-duplex standard is not specific to any particular speed for Ethernet. It can be
`used for Ethernet, Fast Ethernet, and Gigabit Ethernet.
`
`Half-duplex Transmission
`Using half-duplex transmission, signals travel in both directions on the wire, but not
`simultaneously. The original 802.3 standard specifies half-duplex transmission.
`
`To gain access to the network in a half-duplex environment, Ethernet has
`traditionally employed Carrier Sense Muitiple Access with Collision Detection
`(CSMA/CD) as the standard access method. Using CSMA/CD, a station waits for a
`clear channel. When it detects clear channel, it begins to send frames onto the wire.
`If-two stations start sending data at the same time, a collision occurs. Each station
`must detect the collision, abort the transmission, and wait for a random interval of
`time before attempting to tra.nsmit data on the network again.
`
`Half-duplex transmission is most commonly used on shared Ethernet segments.
`Unlike poinHo-point connections, shared segments have two or more stations
`sharing a single port. Figure 11 shows a half~duplex, shared segment.
`
`INTEL EX. 1221.002
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`Figure I 1. Half-duplex, shared Ethernet segment
`
`Most switches manufactured today allow the user to select half-duplex or full"duplex
`on a port by port basis. This allows you to migrate your network from shared
`segments to poinHo-point full-duplex segments over time. A switch port can be
`shared by front-ending the port with a repeater or hub. Figure 12 shows a network
`with both shared and dedicated switch ports.
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`Figure 12. Ethernet network with full-duplex and half-duplex ports
`
`Carrier Extension
`ln order to abide by the rules of the CSMA/CD access method .• all stations sharing
`an Ethernet segment must be able to hear and detect a collision that has occurred on
`the network. More specifically, a station must hear the collision for the frame it is
`sending before it has completed transmitting the entire frame. The amount of time it
`takes for a station to send the frame the full length of the wire and have the jam
`signal resulting frorn a collision travel back to tlie station is known as the slot-time.
`
`With very small (64 byte) frames travelling at speeds of 1 ,000 Mbps, rhe standard
`slot time used in the original IEEE 802.3 Ethernet specification is not long enoush
`to accommodate a I 00 meter cable run. The small frames are transmitted too
`quickly, and the sending station is finished transmitting the frame before it is aware
`of any collision that might have occurred at the other end of the segment.
`
`In order to account for the problems of simply scaling CSMNCD, and allow for
`minimum 64-byte frame sizes for compatibility across Ethernet devices, half-duplex
`Gigabit Ethernet implements a longer slot tlme using a technique called carrier
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`INTEL EX. 1221.003
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`extension. The frame size is not changed. but the time consumed on the wire is
`extended. ·Figure J.J shows a standard Ethernet frame and how extension is used,
`when necessary, to guarantee at least a 5 t 2-byte slot titne.
`
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`Return to TOP of pase
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`INTEL EX. 1221.004
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`T E C ff N I C A L ,Brief
`
`Table of Contents
`
`• Introductiqn
`• Goals of Gigabit Ethernet
`• Uses of Gigabit Ethernet
`• Gjgabit Ethernet History and Momentum
`• Migrating to Gigabit Ethernet
`• Protocol Architecture
`• Cablin~ Types and Distances
`• Flow Control
`• Technology Advances
`• Next Generation NICs and Switches
`• Conclusion
`
`Technology Advances
`.
`We have seen that workstations using the PC! bus have more than enough power to
`accommodate gigabit-speed network interface cards (NlCs). Although the PCI bus
`is ready for Gigabit Ethernet NICs, traditional NIC technology is not suitable for
`Gigabit Ethernet speeds. The problem is that as network speeds accelerate past the
`speed of the CPU, utilization of the CPU can reach I 00%.
`
`Technology innovators are faced with two compelling questions:
`
`• Which processes require the bulk of the CPU time?
`• How can we redu_ce or even eliminate the CPU-intensive processes, thereby
`enabling the host to co.ncentrate on application processing?
`
`In t ei·ms of network interaction. there are two processes that use a great deal of host
`CPU time:
`
`• Interacting with protocol layers-adding protocol headers, removing protocol
`headers, generating checksums, and so on
`• Moving data within the memory system
`
`Minimizing the involvement of the host CPU in both of these categories is a
`requirement for scaling Ethernet NI Cs to gigabit speeds. While it is not possible to
`c.0111pletely eliminate protocol interaction and the need to move data within the
`
`INTEL EX. 1221.005
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`memory system, it is essential to minimize the impact of each in order to run at
`gigabit speeds.
`
`At Alteon Networks, we are leveraging years of experience in the gigabit networking
`arena to produce intelligent network adapters that will match the performance of
`Gigabit Ethernet. To run at gigabit speeds, we are taking large strides in NIC
`development. shifting the balance of processing power and time away from the host
`CPU and to the intelligent NIC itself.
`
`To fully appreciate this technological leap, we will briefly examine first and second
`generation Ethernet NIC technology. Then we will explore the Alteon Gigabit
`Ethernet solution.
`
`First Generation Ethernet Adapters
`Originally designed fo.r the ISA bus, first generation Ethernet adapters are
`uninteJJigent cards designed with rudimentary functionality. All of the processing is
`handled exclusively by the host CPU. Figure I 4 shows the processing sequence for
`data being transmitted by a first generation NIC.
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`Figure 14. Data reception using first generation NIC
`
`The process of transmitting and receiving data using a first generation NIC requires
`each packet to be copied multiple times and requires multiple interrupts to be issued
`for notification along the way. Data reception using a first generation NJC is
`described in Table 3.
`
`Table 3., Steps in· Data Reception using First Generation NIC
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`INTEL EX. 1221.006
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`Data Ste~s
`l. The NIC passes the data, as it
`A.. The NIC notifies the stack
`arrives. ta the protocol stack entit:y that it has transferred the data by
`on the host using a pre-allocated
`issuing an interrupt.
`buffer.
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`2. The protocol stack performs a I
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`checksum on the data.
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`3. The protocol stack moves the
`data to the application memory.
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`B. The· protocol stack informs
`the application that data has
`arrived.
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`First generation Ethernet adapters not only rely exclusively on the host CPU, they
`also require multiple data copies and interrupts to get the job done. Clearly, this
`· technology is slow and cumbersome, and cannot scale to higher speed networks.
`
`Second Generation Ethernet Adapters
`With the advent of the faster applications th,1t needed more CPU power, second
`generation Ethernet adapter manufacturers recognized the need·to limit the·amount
`of host CPU time required to move data around the network. Ir( response, they.
`changed the proce.ssing sequence of the NlC by implementing a concept known as
`"look ahead" buffers, as shown in Figure 15.
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`Figure 15. Data transfer using second generation NlC
`
`Data reception using a second generation Ethernet NIC is described in Table 4.
`
`Table 4. Steps in Data Reception using Second Generation NIC
`
`INTEL EX. 1221.007
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`Control Ste~s
`I. The NIC moves the first 64
`A. The NIC notifies the stack
`bytes of th~ packet to the protocol ~hat it has moved 64 bytes of data
`stack through a pre-allocated
`by issuing an interrupt.
`buffer. The first 64 bytes includes
`the header information and some
`data.
`
`B. The protocol stack analyzes
`~he headers and tells the NJC
`where in application memory to
`put the remaining data from the
`oacket.
`
`2. The protocol stack moves any
`data from the initial 64 bytes
`(minus the header) to the
`I
`aoolication memory.
`3. The NIC moves the rest of the C. The NIC tells the stack that it
`data into application memory. If has finished moving the rest of
`the data packet into application
`application memory is not
`accessible, then an intermediate
`memory by issuing an interrupt.
`buffer is used and the data is
`'
`copied to the application memory
`by the host in Step 4.
`4. The protocol stack performs a D. The protocol stack informs
`the application that data has
`checksum on the packet in the
`application memory space.
`arrived.
`
`I
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`Transferring only the first 64 bytes of information to the protocol stack, instead of
`the entire packet, represents a good stepping stone to minimizing data copies and
`alleviating a small portion of host CPU time. Unfortunately, this method creates a
`new problem~an increased number of interrupts required among the three processing
`entities.
`
`The increased number of interrupts needed by NI Cs using look ahead buffers
`compromises the ability of these cards to scale to gigabit speeds. As network speeds
`outpace the speed of the CPU, NI Cs will request many more interrupts per second.
`Eventually. the CPU will be unable to keep up with the number of interrupts being
`issued and will end up dropping packets.
`
`Return to TOP of P-age
`
`INTEL EX. 1221.008
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`

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`T E C ff N I C A L .Brief
`
`Table of Contents
`
`• Introduction
`• Goals of Gigabit Ethernet
`• Uses of Gigabit Ethernet
`• Gigabit Ethernet History and Momentum
`• Migrating to Gigabit Ethernet
`• Protocol Architectur~
`• Cabling Types and Distances
`• Flow Control
`• Technology Advances
`• Next Generation NICs and Switches
`• Conclusion
`
`Next Generation NICs and Switches
`Clearly. a new methodology for moving data between the NIC, protocol stack, and
`application memory is needed to support Gigabit Ethernet speeds. Alteon Networks
`is pioneering the next generation of Ethernet NTCs in the gigabit arena.
`
`Using an intelligent adapter with an onboard RlSC-based processor specially
`designed for embedded application processing, Alteon's Gigabit Ethernenechnology
`not only reduces the number of times data is copied among processing entities, it
`allows a single interrupt to be issued for multiple data packets-radically altering the
`ratio of interrupts to packets, and eliminating the scalability problems inherent in
`older adapter designs.
`
`Alteon 1s technology advantages center around the following concepts:
`
`• Off-loading TCP/IP checksum
`• Interrupt coalescing
`• Scatter/gather
`• Buffer alignment for virtual page swapping
`• Adaptive DMA on the PCI bus
`.
`• Overall reduction in host buffer copying
`
`Figure 16 illustrates the concepts listed above, and illustrates how data is received by
`the Alteon Gigabit Ethernet NIC and transferred to application memory space.
`
`INTEL EX. 1221.009
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`
`Data reception using an AJteon third generation Ethernet NIC is described in Table
`5.
`
`Table 5. Steps in Data Reception using Alteon1s Third Generation NJC
`
`Data Steps
`
`J. The NIC extracts the header informatlon from the first packeti and puts it into a
`buffer space provided by the host operating system.
`
`2. The NIC puts the packet data lnto a separate buffer space provided by the
`operating system. While doing Steps 1 and 2, the NIC perfonns a .checksum on the
`data.
`
`Repeating Data Steps 1, 2, and 3 ·' the NIC puts as many packets as it can into the
`buffer until one of the following occurs:
`
`• It runs low on buffer spnce
`• The interrupt timer expires
`
`Alteon Gigabit Ethernet adapters have an interrupt timer that determines when to
`interrupt a host CPU. This allows a single interrupt to be issued for multiple data
`packets that are sent into the operating system buffer space. It also allows for
`1'adaptive 11 interrupts; that is,· the NIC can alter the number of interrupts issued per
`second based on network usage.
`
`The NIC card is said to be at idle during any period of time with no work to be
`performed that extends past the interrupt period . The next time an event occurs that
`requires the attention of the host, the NIC does not wait for the interrupt timer to
`expire. lnstead, it begins to act on the data immediately. This is another example of
`adaptive interrupts.
`
`In a busy environment, issuing a smaller number of interrupts over a regularly spaced
`time intervat greatly improves network performance. In a light environment, it is
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`2 of 5
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`INTEL EX. 1221.010
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`preferable to issue interrupts more frequently to reduce latency. Alteon adapters
`allow you to configure the optimum number of intern.1pts for heavy loads on your
`network, while it dynamically evaluates network activity to determine which method
`is most appropriate for normal tratftc loads.
`
`Control Step A: The NIC issues a single interrupt • on a timed basis, telling the
`protocol stack how tnany packets it has copied to the buffer.
`
`Data Step 3: The protocol stack is responsible for ensuring that the data arrives in
`the application memory buffer. This happens in one of two ways:
`
`• If the application memory is also aligned on a page boundary, the protocol
`stack and the application memory swap pointers to the data-eliminating the
`need for the data to be directly copied to the application memory. Swapping
`memory pointers is possible because of the groundwork that was laid in Data
`Step 2.
`• If the application memory is not aligned on a page boundary, the data is
`copied to the application memory by the protocol stack, and
`
`Control Step B: The protocol stack informs the memory that data has arrived.
`
`Using groundbreaking concepts such as those listed above, Alteon Networks is
`clearly distinguishing itself as the leader in Gigabit Ethernet technology. Many years
`of experience in gigabit networking have allowed us to lead the market with a
`complete ASIC, NJC, and driver solution for moving data at gigabit speeds.
`
`Ethernet Switches
`
`• Networks are changing quickly to improve the speed and simplicity of data
`access and enable new applications
`• I 01I00 adapters in desktop workstations are providing the bandwidth required
`by graphic-intensive applications, faster CPUs and faster buses
`_
`• Fast Ethernet switching has become the standard switching technology for
`organizations that have Ethernet on the desktop
`• Intranet servers are being expanded to deliver corporate information, training,
`and on-line documentation, leveraging rapidly improving browser technology
`and data access protocols
`• Multimedia to the desktop is now coming of age with new protocols such as
`RTP and RSVP for users accessing streaming voice/video traffic
`
`All of these changes will drive the demand for faster connections to centralized
`servers as well as faster connections between switches. I 0/100/1000 switches will
`provide an east way to integrate existing Ethernet and Fast Ethernet with Gigabit
`Ethernet connections. These switches will be used to connect servers to today's
`networks and can be used in a backbone to interconnect Fast Ethernet switches. The
`all-gigabit switches provide the ultimate ''backbone-in-a-box" for Ethernet networks
`in a building or campus environment.
`
`INTEL EX. 1221.011
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`Figure 17 illustrates Alteort Gigabit Ethernet switches added to an existing Ethemet
`and Fast Ethernet network.
`
`Specialized ASICs to meet the Performance Demands of Gigabit Ethernet
`
`The majority of initial Gigabit Ethernet products will have full duplex Gigabit
`Ethernet ports. This is an aggregate of 2 Gigabits/second of traffic over each Gigabit
`Ethernet connection. Tn lab tests, using minimum 64 byte frames, each Gigabit
`Ethernet port will be able to send and receive a total of nearly 3 million packets per
`second! These performance levels will clearly overwhelm most intenetworking
`switches and routers shipping today.
`
`The Alteon switch architecture is based on intelligent ASICs. Each ASIC includes
`l~ardware OMA engines, a 32 bit RISC processor and a complete Ethernet MAC.
`These highly integrated ASICs are used to provide the high performance, low cost,
`and reliability required for today's switched networks. The RISC processor is
`involved in higher-level functions, including
`
`packet tracing, accumulating statistics, and other management tasks. Note that every
`ASIC has an embedded processor to handle these functions, eliminating the
`bottleneck of a central CPU.
`
`Dedicated switching hardware in each Alteon ASIC is used to handle forwarding,
`learning, and filtering. Virtual LANs, often used to improve security or to reduce
`network traffic, are configurable by port number, MAC address, Ethertype, etc.
`VLAN tagging and frame priorities are supported in the hardware, with final support
`pending resolution of standards. Spanning Tree support is used for easy installation
`into existing networks.
`
`Seamless Integration with Ethernet and FAst Ethernet
`
`Gigabit Ethernet utilizes the same frame format as Ethernet and Fast Ethernet,
`making it easy to forwal'd traffic between dissimilar networks. Using the same frame
`format avoids the cost, complexity, and performance penalty found when translating
`between Ethernet and ATM or another network technology. More importantly, this
`
`INTEL EX. 1221.012
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`allows Gigabit Ethernet connections to be added only wh.ere the performance is
`needed, maintaining the enterprise's investment in existing NlCs, switches, and
`routers.
`
`Alteon switches are completely interoperable with Ethernet and Fast Ethernet. A
`dynamic buffering scheme is used when forwarding traffic between network
`connections. f nput and output buffers are dynamically allocated to adapt to changing
`traffic conditions, minimizing latency and improving overall throughput. And, I n
`order to deliver the maximum performance to all networks and servers, any port on
`an Alteon switch can run full duplex.
`
`Stnndard Ethernet Management
`
`Alteon switches are also designed to fit into standard management environments to
`leverage the investment in training and equipment. Full RMON and SNMP support
`is included to be compatible with standard network management stations. A private
`Alteon M fB will be included to deliver product specific configuration and statistics.
`Remote management and configuration can even be done through a web browser
`from a standard desktop workstation.
`
`Return to TOP of page
`
`INTEL EX. 1221.013
`
`

`

`h1tp:ll\11WW.nltcon.1:onVtcchbrl l.htm
`
`T E C H N I C A L Brief
`
`Table of Contents
`
`• Intrqduction
`• Goals of Gigabit Ethernet
`• Uses of Gigabit Ethernet
`• Gigabit Ethernet History and Momentum
`• Migrating to Gigabit Ethernet
`• Protocol Architecture
`• Cabling Types and Distances
`• Flow Control
`• Technology Advances
`• Next Generation NICs and Switches
`• Conclusion
`
`Conclusion
`Network speeds are on the rise. Workstation technology has advanced to support
`gigabit data transfer. Multimedia protocols are in final stages of standardization.
`Corporations are insisting on leveraging the billions of dollars already spent on
`networking equipment.
`·
`
`Ethernet is here to stay, at a variety of speeds and for a variety of purposes. Gigabit
`Ethernet technology, while retaining complete interoperability with all of its Ethernet
`predecessors, is the natural extension in the ever persistent need for speed.
`
`Based on a combination of Fibre Channel standards at the lowest layers and standard
`Ethernet above, Gigabit Ethernet provides ultra high-speed backbone connections,
`high-powered server connections, and, eventually, cost-effective workstation
`connections on the corporate network.
`
`By combining time-proven, existing, and widely-implemented Ethernet technology
`with an innovative approach to NIC data transfer, Alteon Networks is leading the
`industry to market with technology to meet the needs of the future in its
`soon-to-be-released Gigabit Ethernet switches, NICs, and repeaters.
`
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`
`INTEL EX. 1221.014
`
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