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`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________
`
`INTEL CORP. and
`CAVIUM, INC.,
`
`Petitioners,
`
`v.
`
`ALACRITECH INC.,
`
`Patent Owner.
`________________
`
`Case IPR2017-013921
`U.S. Patent 7,337,241
`________________
`
`CORRECTED PATENT OWNER’S RESPONSE
`PURSUANT TO 35 U.S.C. § 313 AND 37 C.F.R. § 42.107
`
`
`1 Cavium, who filed a Petition in Case IPR2017-01728, has been joined as
`
`a petitioner in this proceeding.
`
`
`
`

`

`
`
`I.
`
`II.
`
`
`
` Case No. IPR2017-01392
`U.S. Patent No. 7,337,241
`
`TABLE OF CONTENTS
`
`Page
`
`INTRODUCTION .................................................................................1
`
`BACKGROUND OF THE RELEVANT TECHNOLOGY .................2
`
`III. LEVEL OF ORDINARY SKILL IN THE ART ...................................8
`
`IV. OVERVIEW OF THE ’241 PATENT ..................................................8
`
`A.
`
`B.
`
`The ’241 Patent Specification .....................................................8
`
`The ’241 Patent Claims ............................................................ 13
`
`V.
`
`PROSECUTION HISTORY OF THE ’241 PATENT ...................... 15
`
`VI. OVERVIEW OF THE ASSERTED PRIOR ART ............................. 16
`
`A. U.S. Patent No. 5,768,618 (“Erickson”) .................................. 17
`
`B.
`
`C.
`
`Tanenbaum, Computer Networks, 3rd ed. (1996)
`(“Tanenbaum”) ......................................................................... 19
`
`“Gigabit Ethernet Technical Brief: Achieving End-to-
`End Performance” (“Alteon”) .................................................. 20
`
`D. Dr. Min Testified He Had “No Opinion” on the Prior Art ...... 21
`
`VII. CLAIM CONSTRUCTION ............................................................... 22
`
`A.
`
`B.
`
`“[first/second] mechanism” (claims 1-5, 7, 8, 17, 20, 23) ....... 23
`
`“without an interrupt dividing” (claims 1, 18, 22) ................... 25
`
`VIII. PETITIONER FAILED TO PROVE THAT ALTEON
`QUALIFIES AS A “PRINTED PUBLICATION” OR IS
`PRIOR ART ....................................................................................... 27
`
`IX. ERICKSON, TANENBAUM, AND ALTEON DO NOT
`RENDER CLAIMS 1-8 OBVIOUS ................................................... 32
`
`A.
`
`B.
`
`The Combination Does Not Show or Suggest Validation
`of Network and Transport Layer Headers “Without An
`Interrupt Dividing the Processing” of the Layer Headers
`(Claim 1) .................................................................................. 32
`
`The Combination Does Not Show or Suggest Sending the
`Data From Each Packet to a Destination in Memory
`Without Sending Any of the Headers (Claim 1) ...................... 37
`
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`U.S. Patent No. 7,337,241
`The Combination Does Not Show or Suggest Processing
`MAC Layer Headers Without an Interrupt Dividing the
`Processing (Claim 2) ................................................................ 40
`
`The Combination Does Not Show or Suggest
`Additionally Processing an Upper Layer Header by a
`Second Mechanism (Claim 3) .................................................. 41
`
`The Combination Does Not Show or Suggest Sorting The
`Packets By Classifying Each as Having an IP and TCP
`Header (Claim 6) ...................................................................... 42
`
`There Is No Motivation to Combine Erickson,
`Tanenbaum, and Alteon ............................................................ 42
`
`C.
`
`D.
`
`E.
`
`F.
`
`X.
`
`ERICKSON AND TANENBAUM DO NOT RENDER CLAIMS
`9-17, 19-21, AND 24 OBVIOUS ....................................................... 46
`
`A.
`
`B.
`
`C.
`
`The Combination Does Not Show or Suggest Prepending
`the MAC, Network, and Transport Layer Headers at One
`Time as a Sequence of Bits (Claim 9)...................................... 47
`
`The Combination Does Not Show or Suggest Prepending
`Each Packet Header Without an Interrupt Dividing the
`Prepending of the MAC, IP, and TCP Headers (Claim
`17) ............................................................................................. 50
`
`The Combination Does Not Show or Suggest Dividing
`the Data Into Multiple Segments and Prepending a
`Packer Header to Each of the Segments by a Second
`Processor/Mechanism (Claims 9 and 17) ................................ 52
`
`D.
`
`There Is No Motivation to Combine Erickson and
`Tanenbaum ............................................................................... 54
`
`XI. ERICKSON, TANENBAUM, AND ALTEON DO NOT
`RENDER CLAIMS 18, 22, AND 23 OBVIOUS .............................. 56
`
`XII. THE STRONG EVIDENCE OF SECONDARY
`CONSIDERATIONS WEIGHS AGAINST OBVIOUSNESS ......... 56
`
`XIII. THE PETITION FAILS TO DISCLOSE ALL REAL
`PARTIES-IN-INTEREST .................................................................. 63
`
`XIV. ALACRITECH RESERVES ITS RIGHTS UNDER THE
`PENDING OIL STATES CASE AT THE UNITED STATES
`SUPREME COURT ........................................................................... 65
`
`
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`ii
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`U.S. Patent No. 7,337,241
`XV. CONCLUSION .................................................................................. 66
`
`
`
`
`
`iii
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` Case No. IPR2017-01392
`U.S. Patent No. 7,337,241
`
`TABLE OF AUTHORITIES
`
`Page
`
`Cases
`
`Bruckelmyer v. Ground Heaters, Inc.,
` 445 F.3d 1374 (Fed. Cir. 2006) .......................................................... 28, 31
`
`CCS Fitness, Inc. v. Brunswick Corp. 288, F.3d 1359,
` 1366 (Fed. Cir. 2002) .............................................................................. 22
`
`Dynamic Drinkware, LLC v. Nat’l Graphics, Inc.,
` 800 F.3d 1375 (Fed. Cir. 2015) ................................................................ 27
`
`In re Cronyn,
` 890 F.2d 1158 (Fed. Cir. 1989) ................................................................ 31
`
`Intelligent Bio-Systems, Inc. v. Illumina Cambridge Ltd.,
` 821 F.3d 1359 (Fed. Cir. 2016) ................................................................ 31
`
`Nautilus, Inc. v. Biosig Instruments, Inc.,
` 134 S. Ct. 2120 (2014) ............................................................................. 26
`
`Oil States Energy Servs. LLC v. Greene’s Energy Group, LLC,
` Case No. 16-712, certiorari granted (U.S. Jun. 12, 2017) ...................... 65
`
`Pfizer v. Biogen, Case IPR2017-001166 at 11 (PTAB Nov. 13, 2017) ....... 27
`
`Statutory Authorities
`
`35 U.S.C. § 112(6) .................................................................................. 23, 24
`
`35 U.S.C. § 312(a)(2) .................................................................................... 63
`
`35 U.S.C. § 316(e) .................................................................................... 1, 27
`
`Rules and Regulations
`
`37 C.F.R. § 42.6(e) ....................................................................................... 69
`
`37 C.F.R. §§ 42.22, 42.23 ............................................................................. 66
`
`
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`Case No. IPR2017-01392
`U.S. Patent No. 7,337,241
`US. Patent No. 7,337,241
`37 C.F.R. § 42.24 .......................................................................................... 68
`37 CPR. § 42.24 .......................................................................................... 68
`
`
`
`37 C.F.R. § 42.24(b)(2) ................................................................................. 68
`37 CPR. § 42.24(b)(2) ................................................................................. 68
`
`37 C.F.R. § 42.100(b) ................................................................................... 22
`37 CPR. § 42.100(b) ................................................................................... 22
`
`37 CFR § 42.8(b)(1) ..................................................................................... 63
`37 CFR § 42.8(b)(1) ..................................................................................... 63
`
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`
`
`Ex. 2002
`
`Ex. 2003
`
`Ex. 2004
`
`Ex. 2005
`
`Ex. 2007
`
`Ex. 2008
`
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`U.S. Patent No. 7,337,241
`
`PATENT OWNER’S LIST OF EXHIBITS
`
`Intel Corporation’s Motion to Intervene, Case No. 2:16-
`cv-00693-JRG-RSP, Dkt. 71 (E.D. Tex., Oct. 31, 2016)
`
`Declaration of Christopher Kyriacou, Case No. 2:16-cv-
`00693-JRG-RSP, Dkt. 71-5 (E.D. Tex., Oct. 31, 2016)
`
`Jonathan Corbet; Alessandro Rubini; Greg Kroah-
`Hartman (2005), Linux Device Drivers, 3rd edition,
`Chapter 10, “Interrupt Handling”
`
`Defendant Dell Inc.’s First Supplemental Responses to
`Plaintiff’s Second Set of Common Interrogatories to
`Defendants and Intervenors (No. 11)
`
`Declaration of Garland Stephens, Case No. 2:16-cv-
`00693-JRG-RSP, Dkt. 71-2 (E.D. Tex., Oct. 31, 2016)
`
`Excerpts of Declaration of Mr. Mark R. Lanning
`Regarding Claim Construction, Case No. 2:16-cv-00693-
`JRG-RSP, Dkt. 303-5 (E.D. Tex. Jul. 6, 2017)
`
`Ex. 2009
`
`Cavium’s Motion to Intervene, Case No. 2:16-cv-00693-
`JRG-RSP, Dkt. 109 (E.D. Tex., Jan. 13. 2017)
`
`Ex. 2010
`
`Not Used
`
`Ex. 2026
`
`Declaration of Kevin Almeroth, Ph.D. in Support of
`Patent Owner’s Response to the Petition
`
`Ex. 2027
`
`Curriculum Vitae of Kevin Almeroth, Ph.D.
`
`Ex. 2028
`
`Ex. 2029
`
`Ex. 2030
`
`Transcript from the Deposition of Robert Horst, Ph.D.
`dated January 25, 2018
`
`Transcript from the Deposition of Robert Horst, Ph.D.
`dated January 26, 2018
`
`Memorandum Order and Opinion on Claim
`Construction, Case No. 2:16-cv-00693-RWS-RSP,
`Docket 362 (Filed September 21, 2017)
`
`
`
`vi
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` Case No. IPR2017-01392
`U.S. Patent No. 7,337,241
`
`Ex. 2031
`
`The Architecture of a Gb/s Multimedia Protocol Adapter
`
`Ex. 2032
`
`A Fast Track Architecture for UDP/IP and TCP/IP
`
`Ex. 2033
`
`A Communication Architecture for High-speed
`Networking
`
`Ex. 2034
`
`Server Network Scalability and TCP Offload
`
`Ex. 2035
`
`Alacritech and NetXen Join Forces to Deliver Solutions
`for Microsoft TCP Chimney Offload Technology
`
`Ex. 2036
`
`QLogic Licenses Alacritech
`
`Ex. 2037
`
`Neterion Licenses Alacritech’s Patents
`
`Ex. 2038
`
`Alacritech Licenses
`
`Ex. 2039
`
`Ex. 2040
`
`An Evaluation of an Attempt at Offloading TCP/IP
`Protocol Processing onto an i960RN-based iNIC
`
`Alacritech, Pioneer In Network Acceleration, Unveils
`Appliance To Alleviate Enterprise Storage Woes
`
`Ex. 2041
`
`TCP offload is a dumb idea whose time has come
`
`Ex. 2042
`
`TCP/IP Headers (https://nmap.org/book/tcpip-ref.html)
`
`Ex. 2043
`
`TCP/IP message processing
`(http://www.thegeekstuff.com/2011/11/tcp-ip-
`fundamentals/)
`
`Ex. 2044
`
`Not Used
`
`Ex. 2300
`
`Horst Paper
`
`Ex. 2301
`
`Listing of Challenged Claims
`
`
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`vii
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`

`
`
`I.
`
`INTRODUCTION
`
`
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` Case No. IPR2017-01392
`U.S. Patent No. 7,337,241
`
`Patent Owner Alacritech Inc. respectfully submits this Patent Owner
`
`Response. Petitioner Intel Corporation filed the Petition for Inter Partes Review of
`
`claims 1-24 (“challenged claims”) of U.S. Patent No. 7,337,241, and the Board
`
`instituted proceedings on November 30, 2017 on Grounds 1-3
`
`For the reasons below, Intel has failed to meet its “burden of proving a
`
`proposition of unpatentability by a preponderance of the evidence.” 35 U.S.C. §
`
`316(e). First, Petitioner has not established that Alteon was publicly accessible
`
`prior to the October 14, 1997 priority date of the ’241 Patent and hence qualifies as
`
`a “printed publication” or prior art to the ’241 Patent. Second, Intel has failed to
`
`prove the existence of numerous limitations of the challenged claims in the cited
`
`references, alone or in combination with each other, including the claimed header
`
`validation, interrupt, and dividing into segments limitations. Third, Intel also
`
`failed to prove that a person of ordinary skill in the art (“POSITA”) would
`
`combine the cited prior art with any expectation of successfully arriving at the
`
`claimed subject matter, particularly in view of the strong teaching away and
`
`evidence of secondary considerations of non-obviousness present in this case.2
`
`
`2 Alacritech also respectfully reserves its rights under the Oil States case pending
`
`before the United States Supreme Court, as set forth in Section XIV of this
`
`Response.
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`1
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`U.S. Patent No. 7,337,241
`II. BACKGROUND OF THE RELEVANT TECHNOLOGY
`
`
`
`Both in 1997 and today, sending and receiving information over the Internet
`
`involves the use of many different protocols that set out the rules for how devices
`
`on the Internet can communicate with one another. (Ex. 2026, ¶ 59.) Multiple
`
`conceptual models exist for characterizing the interactions between these protocols
`
`in the context of the Internet and other telecommunication or computing systems.
`
`The Open Systems Interconnection model (or “OSI model”) is one well known
`
`example, describing a seven layer stack where a particular layer serves the layer
`
`above it and is served by the layers below it. Id. The seven layers of the OSI
`
`model are:
`
`Layer 7: Application Layer
`
`Layer 6: Presentation Layer
`
`Layer 5: Session Layer
`
`Layer 4: Transport Layer
`
`Layer 3: Network Layer
`
`Layer 2: Data Link Layer
`
`Layer 1: Physical Layer
`
`with layer 1 (the Physical Layer) being the lowest layer in the model. Id.
`
`
`
`The Internet Protocol (or “IP”) is an example of a well-known network
`
`(layer 3) protocol. (Id., ¶ 61.) IPv4 was published as RFC 760 in January 1980
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`2
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`U.S. Patent No. 7,337,241
`while its successor IPv6 was published as RFC 2460 in December 1998. Id. The
`
`
`
`IP protocol describes a set of rules for dividing a message into multiple parts
`
`(called “IP packets”) and then transmitting those packets from an IP sender to an
`
`IP destination across multiple routers or other links in a computer network. Each
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`packet of information includes an IP address for its destination, analogous to
`
`sending a letter through the mail by placing the letter inside an envelope that has
`
`the recipient’s postal address printed on it. Id. The format of an IP header is
`
`depicted below:
`
`
`
`
`
`3
`
`

`

`
`
`(Id.; Ex. 2042)3
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`U.S. Patent No. 7,337,241
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`
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`The Transmission Control Protocol, referred to as “TCP,” is one of the main
`
`protocols used to send and receive information over the Internet. (Ex. 2026, ¶ 62.)
`
`TCP is well known in the computer networking industry—one early TCP rule set
`
`was published as a Request for Comment (or “RFC”) by the Internet Engineering
`
`Task Force (“IETF”) in September 1981 (RFC 793). That rule set was based on an
`
`even earlier rule set published in December 1974 as RFC 675. TCP is an example
`
`of a transport (layer 4) protocol in the OSI model. Id. TCP is responsible for
`
`adding reliability and ordering to the stream of network information—for example,
`
`the packets of information sent using IP as the network-layer protocol may not
`
`arrive at the destination in the same order intended by the sender of the message.
`
`Id. TCP sets rules for breaking up and transmitting the message so that the
`
`recipient is able to reliably receive and reassemble the message. Another common
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`analogy from the physical world is the example of sending a multi-page letter
`
`through the mail by separately numbering each page and mailing it in its own
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`envelope. IP, like the postal service, will route the envelope-like packets to the
`
`destination, but TCP (like the numbering of the individual pages) sets the rules to
`
`
`3 This figure accurately depicts an IP header as of October 1997, as supported by
`
`the testimony of Dr. Almeroth. (Ex. 2026 at ¶ 61.)
`
`
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`4
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`U.S. Patent No. 7,337,241
`allow the recipient to verify that all of the pages have been received and to
`
`
`
`reassemble the pages in the right order. Id.
`
`
`
`TCP describes, for example, how two devices on the Internet may establish a
`
`connection over which TCP data packets may be communicated between them.
`
`(Ex. 2026, ¶ 63.) By way of a negotiation process known as a three-way
`
`handshake, such a connection can be established between two nodes, and once that
`
`connection establishment phase completes, data transfer can begin. Typically, a
`
`TCP connection is managed by a device operating system so that applications such
`
`as a web browser or a web server like a CDN caching server can pass data to the
`
`operating system’s TCP protocol “stack,” and the operating system will manage
`
`transmission of that data to the receiver and will pass received data from the other
`
`device up to the application layer. Id. The format of a TCP header is depicted
`
`below:
`
`
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`5
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`U.S. Patent No. 7,337,241
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`
`
`(Id.; Ex. 2042.4)
`
`
`
`Transmitting a message requires processing each of the layers in that
`
`protocol stack sequentially so that the message can then be transmitted over the
`
`data medium. The receiving computer is also required to process those same
`
`layers in reverse until the message is handed off to the appropriate program (e.g., a
`
`web server). (Ex. 2026, ¶ 64.) One example of processing a message using
`
`TCP/IP is depicted below:
`
`
`4 This figure accurately depicts an TCP header as of October 1997, as supported
`
`by the testimony of Dr. Almeroth. (Ex. 2026 at ¶ 63.)
`
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`6
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`(Id.; Ex. 2043.5)
`
`
`
`
`
`
`
`Much of this processing is typically handled by the CPU. (Ex. 2026, ¶ 65.)
`
`Thus, sending and receiving data over a network can negatively impact the CPU’s
`
`ability to perform other functions, particularly as the volume of data sent or
`
`received increases. Id. For the purposes of this case, the manner by which the
`
`CPU handles the required protocol processing—i.e., the specific software steps it
`
`
`5 This figure accurately depicts an example of processing a message using TCP/IP
`
`as of October 1997, as supported by the testimony of Dr. Almeroth. (Ex. 2026 at ¶
`
`64.)
`
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`7
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`U.S. Patent No. 7,337,241
`takes to perform the needed TCP and IP processing—is immaterial. Id. At most, it
`
`
`
`is sufficient that the CPU does perform or is capable of performing that processing,
`
`whether through software included as part of the operating system or through some
`
`other means. Id.
`
`III. LEVEL OF ORDINARY SKILL IN THE ART
`
`
`
`Patent Owner’s proposed level of ordinary skill for the ’241 Patent is a
`
`Bachelor’s degree in Computer Science, Computer Engineering, or the equivalent,
`
`and several years’ experience in the fields of computer networking and/or
`
`networking protocols. (Ex. 2026, ¶¶ 30-35.) Any differences between Petitioner’s
`
`proposed level of ordinary skill and that proposed by Patent Owner would not have
`
`any bearing on the analysis presented in this Response. Indeed, the cited
`
`references fail to disclose the limitations, nor would it have been obvious to
`
`combine the references, for the reasons presented below under either party’s
`
`proposed level of ordinary skill in the art.
`
`IV. OVERVIEW OF THE ’241 PATENT
`
`A. The ’241 Patent Specification
`
`The ’241 Patent, titled “Fast-Path Apparatus for Receiving Data
`
`Corresponding to a TCP Connection,” describes a novel system for accelerating
`
`network processing. An intelligent network interface card (INIC) communicates
`
`with a host computer. The INIC provides “a fast-path that avoids protocol
`
`processing for most large multi-packet messages, greatly accelerating data
`
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`8
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`U.S. Patent No. 7,337,241
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`communication.” (Ex. 1001, Abstract.)
`
`As explained in the background of the ’241 Patent, when a conventional
`
`network interface card prepares to send data from a first host to a second host,
`
`“some control data is added at each layer of the first host regarding the protocol of
`
`that layer, the control data being indistinguishable from the original (payload) data
`
`for all lower layers of that host.” (Id., 3:67-4:3.) This process of adding a layer
`
`header to the data from the preceding layer is sometimes referred to as
`
`“encapsulation” because the data and layer header is treated as the data for the
`
`immediately following layer, which, in turn, adds its own layer header to the data
`
`from the preceding layer. (Ex. 2026, ¶¶ 68-69.) Each layer is generally not aware
`
`of which portion of the data from the preceding layer constitutes the layer header
`
`or the user data; as such, each layer treats the data it receives from the preceding
`
`layer as some generic payload. (Id.)
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`
`
`(Ex. 1008, Stevens, 1008.034, Figure 1.4 (adapted from Petition, 18).)
`
`On the receiving side, the receiving host generally performs the reverse of
`
`the sending process, beginning with receiving the bits from the network. Headers
`
`are removed, one at a time, and the received data is processed, in order, from the
`
`lowest (physical) layer to the highest (application) layer before transmission to a
`
`destination within the receiving host (e.g., to the operating system space where the
`
`received data may be used by an application running on the receiving host). (Ex.
`
`1001, 4:20-26.) Each layer of the receiving host recognizes and manipulates only
`
`the headers associated with that layer, since to that layer the higher layer header
`
`data is included with and indistinguishable from the payload data. “Multiple
`
`interrupts, valuable central processing unit (CPU) processing time and repeated
`
`data copies may also be necessary for the receiving host to place the data in an
`
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`U.S. Patent No. 7,337,241
`appropriate form at its intended destination.” (Id., 4:30-33.)
`
`
`
`Because the processing of each layer typically involves a copy and data
`
`manipulation operation (for example a checksum generation or validation
`
`operation), the host CPU must be “interrupted” at least one time per layer in order
`
`to process the data and construct (transmit side) or deconstruct (receive side) the
`
`packet. An interrupt is a signal to the processor emitted by hardware or software
`
`indicating an event that needs immediate attention. (Ex. 2026, ¶ 70.) An interrupt
`
`alerts the processor to a high-priority condition requiring the interruption of the
`
`current code the processor is executing. (Id.) When the host CPU is interrupted, it
`
`generally must stop all other tasks it is currently working on, including tasks
`
`completely unrelated to the network processing. Frequent interrupts to the host
`
`CPU can be very disruptive to the host system generally and cause system
`
`instability and degraded system performance. (Ex. 2026, ¶¶ 71-73.)
`
`The invention of the ’241 Patent includes a “fast-path” where the host CPU
`
`is relieved of certain TCP/IP processing, which is instead performed by the INIC.
`
`The fast-path “bypasses conventional protocol processing of headers that
`
`accompany the data” and “employs a specialized microprocessor designed for
`
`processing network communication, avoiding the delays and pitfalls of
`
`conventional software layer processing, such as repeated copying and interrupts to
`
`the CPU.” (Ex. 1001, 5:22-28; ).
`
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`11
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`The fast-path is shown in Figure 24 of the ’241 Patent, which is reproduced
`
`
`
`below. In this embodiment, the INIC performs at least the IP and TCP layer
`
`processing, freeing up the CPU on the host (“client”) computer to do other tasks.
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`The fast-path also reduces or eliminates the number of interrupts sent to the CPU
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`on the host/client. The more traditional “slow-path” is also shown, where the
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`host/client is responsible for the IP and TCP layer processing. In the slow-path,
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`the CPU on the host/client is interrupted at least one time at each layer of
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`processing.
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`
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`(Ex. 1001.026, Fig. 24.)
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`The results of the claimed invention include more efficient network
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`processing and “a huge reduction in interrupts.” (Id., 11:37-42.) For fast-path
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`communications, only one interrupt occurs at the beginning and end of an entire
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`upper-layer message transaction, and “there are no interrupts for the sending or
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`receiving of each lower layer portion or packet of that transaction.” (Id., 11:42-
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`
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`46.)
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`This result is accomplished through several important innovations, including
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`the novel and nonobvious positioning of the fast-path at an upper layer, the use of
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`full transfer sizes between the network processor and the host, and reduced
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`generation of interrupts to the host. As explained in the ’241 Patent:
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`Both the input and output fast-paths attain a huge reduction in
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`interrupts by functioning at an upper layer level, i.e., session level or
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`higher, and interactions between the network microprocessor and the
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`host occur using the full transfer sizes which that upper layer wishes
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`to make. For fast-path communications, an interrupt only occurs (at
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`the most) at the beginning and end of an entire upper-layer message
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`transaction, and there are no interrupts for the sending or receiving
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`of each lower layer portion or packet of that transaction.
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`
`(Ex. 1001, 11:37-46.)
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`The claimed arrangement allows for enhanced network and system
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`performance, a stark reduction or elimination of interrupts seen by the host CPU,
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`faster data throughput, increased system stability, and an overall better user
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`experience. (Ex. 2026, ¶¶ 74-78)
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`B.
`
`The ’241 Patent Claims6
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`Claim 1 recites “processing the packets by a first mechanism, so that for
`
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`6 See Exhibit 2301.
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`each packet the network layer header and the transport layer header are validated
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`
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`without an interrupt dividing the processing of the network layer header and the
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`transport layer header” and “sending, by the first mechanism, the data from each
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`packet of the first type to a destination in memory allocated to an application
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`without sending any of the media access control layer headers, network layer
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`headers or transport layer headers to the destination.” By preparing packets for
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`transmission using an INIC instead of the host CPU, interrupts to the host CPU can
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`be reduced or eliminated altogether, and the data portion of received packets can
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`be sent directly to a destination in memory without sending the various MAC,
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`network, and transport layer headers.
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`Independent claim 9 recites that data obtained from a source in memory
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`allocated by a first processor is “divid[ed]…into multiple segments” and a packet
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`header is prepended to each segment by a second processor. Additionally, “the
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`network layer header and the transport layer header are prepended at one time as a
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`sequence of bits during the prepending of each packet header.” By preparing
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`packets for transmission using an INIC instead of the host CPU, multiple headers
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`can be prepended at one time instead of interrupting the host CPU between each
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`header operation.
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`Independent claim 17 recites “dividing, by a second mechanism, the block of
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`data into multiple segments” and “prepending, by the second mechanism, an
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`outbound packet header to each of the segments . . . wherein the prepending of
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`
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`each outbound packet header occurs without an interrupt dividing the prepending
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`of the outbound media access control layer header, the outbound (IP) header and
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`the outbound TCP header.”
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`These claimed features are not found in any of the prior art, alone or in
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`combination with each other, cited by Petitioner.
`
`V.
`
`PROSECUTION HISTORY OF THE ’241 PATENT
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`The ’241 Patent issued on February 26, 2008. It was filed on September 27,
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`2002 as Application No. 10/260,878 as a continuation of Application No.
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`10/092,967 filed March 6, 2002, which in turn claims the benefit of Provisional
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`Application No. 60/061,809, filed on Oct. 14, 1997.7
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`The ’241 Patent was subject to a thorough examination by Examiners Eric J.
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`Kuiper and Jerry B. Dennison, who allowed the application on July 30, 2007 after
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`two rounds of claim amendments and arguments. (Ex. 1002, 597-602.) In
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`connection with claim 1, the applicants explained that the prior art of record did
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`not “teach any processing of a network layer header or a transport layer header, let
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`alone ‘processing the packets by a first mechanism, so that for each packet the
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`network layer header and the transport layer header are validated without an
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`interrupt dividing the processing of the network layer header and the transport
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`
`7 See Ex. 1001, 1:8-2:23 for a listing of other related applications.
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`layer header.’” (Id., 333-334 (emphasis added).)
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`Similar arguments were made with response to independent claims 9 and 17.
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`(Id., 341-43, 345-46.) In connection with claim 9, the applicants argued that the
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`prior art of record did not show or suggest “wherein the prepending of each packet
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`header occurs without an interrupt dividing the prepending….” (Id., 342
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`(emphasis added).)8 In connection with claim 17, the applicants argued that the
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`prior art of record did not show or suggest “the processing and validating of these
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`headers all occurring without interrupts between each layer.” (Id., 346 (emphasis
`
`added).)
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`Accordingly, on July 30, 2007, the Examiner issued a Notice of Allowance
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`granting claims 1-24 of the ’241 Patent. (Id., 597-602.) An Issue Notification was
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`then mailed on February 6, 2008. (Id., 627.)
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`VI. OVERVIEW OF THE ASSERTED PRIOR ART
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`Intel relies on the Erickson, Tanenbaum, and Alteon references. The
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`following sections summarize these references and underscore their respective
`
`
`8 In response to the second Office Action, the interrupt language was replaced
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`with language requiring “the network layer header and the transport layer header
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`are prepended at one time as a sequence of bits during the prepending….” (Ex.
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`1002, 567-68 (emphasis added).) The patent applicants argued that the prior art of
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`record did not show this claimed feature. (Id., 574-75.)
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`shortcomings with respect to the challenged claims.
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`A. U.S. Patent No. 5,768,618 (“Erickson”)
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`Although Petitioner alleges “Erickson was not cited to or by the Examiner
`
`during prosecution of the 241 Patent” (Petition, 35 n.4), Erickson appears on the
`
`face of the ’241 Patent under “References Cited” and was initialed by the
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`Examiner in an Information Disclosure Statement (IDS) dated December 20, 2007.
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`(Ex. 1002, 623.) Erickson was therefore already considered by the Examiner
`
`during the prosecution of the ’241 Patent, which was found to be allowable over
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`Erickson.
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`Erickson discloses an input/output (I/O) device connected to a computer to
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`facilitate fast I/O data transfers. (Ex. 1005, Abstract.) An address space for the
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`I/O device is created in the virtual memory of the computer, wherein the address
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`space comprises virtual registers that are used to directly control the I/O device.
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`Control registers and/or memory of the I/O device are mapped into the virtual
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`address space, and the virtual address space is backed by control registers and/or
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`memory on the I/O device. When the I/O device detects writes to the address
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`space, a pre-defined sequence of actions can be triggered in the I/O device by
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`programming specified values into the data written into the mapped virtual address
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`space. (Id.)
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`Figure 7 of Erickson shows a UDP datagram header “template” that resides
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`in the I/O adapter’s memory. (Id., 7:39-46.) A user provides the starting address
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`
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`and length for the user data in its virtual address space, and then “spanks” a GO