US 7,496,689 B2
`(10) Patent No.:
`a2) United States Patent
`Sharpetal.
`(45) Date of Patent:
`Feb. 24, 2009
`
`
`US007496689B2
`
`(56)
`
`wo
`
`(54) TCP/IP OFFLOAD DEVICE
`
`(75) Tnventors: Colin C. Sharp, Santa Cruz, CA (US);
`Clive M.Philbrick, San Jose, CA (US);
`Daryl D.Starr, Milpitas, CA (US);
`Stephen E. J. Blightman, San Jose, CA
`(US)
`(73) Assignee: Alacritech, Inc., San Jose, CA (US)
`(*) Notice:
`Subjectto any escraimer. the termors
`rec Wshbyb "930.d. yusted under
`S.C.
`154(b)
`by
`ays:
`(21) Appl. No.: 10/420,364
`:
`Filed:
`
`
`
`(2006.01)
`(2006.01)
`(2006.01)
`3006.01
`(2006.01)
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,366,538 A
`12/1982 Johnson et al.
`............. 364/200
`(Continued)
`FOREIGN PATENT DOCUMENTS
`WO 98/19412
`5/1998
`(Continued)
`OTHER PUBLICATIONS
`Internet pages entitled “Hardware Assisted Protocol Processing”,
`(which Eugene Feinberisworking on), | page, printedNov. 25, 1998.
`(Continued)
`Primary Examiner—Ario Etienne
`Assistant Examiner—Philip J Chea
`p
`(74) Attorney, Agent, or Firm—Mark Lauer; Silicon Edge
`Apr. 22, 2003
`(22)
`Law
`G
`LLP
`awe
`Prior Publication Data
`(65)
`
`
`US 2004/0062245 Al—Apr. 1, 2004 (57) ABSTRACT
`,
`A TCP/IP offload network interface device (NID) is inte-
`Related U.S. Application Data
`grated with a processing device that executes a stack. The
`(60) Provisional application No. 60/374,788, filed on Apr.
`TCP/IP offload NID caneither be a full TCP/IP offload device
`22. 2002
`—
`or a partial TCP/IP offload device. Commontypesofpackets
`; are processed by the NID inafast-path such that the stack is,
`
`Int. Cl.
`(51)
`offloaded ofTCP andIP protocol processing tasks. A hash is
`GO6F 15/173
`made from the packet header and is pushed onto a queue. The
`GO6F 15/16
`hash is later popped off the queue andis used to identify an
`GO6F 12/00
`associated TCB number from a hash table. A mechanism
`HOAL 15/00
`caches hash buckets in SRAM andstores other hash buckets
`in DRAM. An “IN SRAM CAM”is used to determine
`whether the TCBassociated with the identified TCB number
`is cached in SRAM or whetherit must be moved from DRAM
`into the SRAM cache. A lock table and a “lock table CAM”
`mechanism is disclosed that facilitates multiple processors
`working on the protocol processing of a single packet.
`
`(52) US. Ch cece 709/250; 709/238; 711/108;
`370/463
`
`(58) Field of Classification Search ................. 709/238,
`709/250; 711/108; 370/463; 375/219
`See application file for complete search history.
`
`21 Claims, 72 Drawing Sheets
`
`|
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`PROCESSOR THAT
`IMPLEMENTS
`PROTOCOL STACK
`
`INTEL Ex. 1258.001
`
`INTEL Ex. 1258.001
`
`

`

`US 7,496,689 B2
`
`Page 2
`
`U.S. PATENT DOCUMENTS
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`4,589,063 A
`4,700,185 A
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`
`
`
`INTEL Ex. 1258.002
`
`INTEL Ex. 1258.002
`
`

`

`US 7,496,689 B2
`
`Page 3
`
`FOREIGN PATENT DOCUMENTS
`
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`. 709/230
`iReady article entitled “About Us Introduction”, Internet pages
`
`
`.
`7,191,318 B2
`3/2007 Tripathy et al.
`. 712/225
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`.
`7,237,036 B2
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`. 709/245
`25, 1998.
`
`....
`. 712/210
`7,254,696 B2
`8/2007 Mittal etal.
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`
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`iReady News Archivearticle entitled “Seiko Instruments Inc. (SID
`2001/0013059 Al
`8/2001 Dawsonetal. ..
`. 709/217
`Introduces World’s First Internet-Ready Intelligent LCD Modules
`
`2001/0014892 Al
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`..
`. 707/200
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`2001/0014954 Al
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`12/2001 Bilic etal.
`...
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`2002/0073223 Al
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`2003/0165160 Al
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`Adaptec article entitled “AEA-7110C-a DuraSAN product”, 11
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`
`
`wee 713/168
`2004/0059926 Al
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`.
`2004/0213290 Al
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`Oct. 1, 2001.
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`iSCSI HBAarticle entitled “FCE-3210/6410 32 and 64-bit PCI-to-
`Fibre Channel HBA”, 6 pages, printed Oct. 1, 2001.
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`2001.
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`ing, vol. 6, No. 6, Dec. 1998, 17 pages.
`
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`
`WO
`WO
`WO
`
`11/1998
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`
`INTEL Ex. 1258.003
`
`INTEL Ex. 1258.003
`
`

`

`US 7,496,689 B2
`Page 4
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`ConsumerDevices Internet-Ready Based on iReady Design”, Santa
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`pages.
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`tions”, by Lynne Jolitz, printed Jun. 14, 2000, 4 pages.
`“File System Design For An NFS File Server Appliance”, Article by
`D. Hitz, et al., 13 pages.
`Adaptec Press Release article entitled “Adaptec Announces
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`
`Adaptec article entitled “EtherStorage Frequently Asked Questions”,
`5 pages, printed Jul. 19, 2000.
`Adaptec article entitled “EtherStorage White Paper’, 7 pages, printed
`Jul. 19, 2000.
`CIBC World Markets article entitled “Computers; Storage”, by J.
`Berlinoet al., 9 pages, dated Aug. 7, 2000.
`Merrill Lynch article entitled “Storage Futures”, by S. Milunovich,
`22 pages, dated May 10, 2000.
`CBS Market Watcharticle entitled “Montreal Start-Up Battles Data
`Storage Bottleneck”, by S. Taylor, dated Mar. 5, 2000, 2 pages,
`printed Mar. 7, 2000.
`Internet-draft article entitled “SCSI/TCP (SCSI over TCP)”, by J.
`Satran et al., 38 pages, dated Feb. 2000, printed May 19, 2000.
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`Acceleration Solution for Windows NT Server, printed Jun. 5, 1997,
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`tecture, twelve-slide presentation, printed Aug. 19, 1998, 13 pages.
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`dated Aug. 10, 1998, printed Nov. 25, 1998, 3 pages.
`Internet pages entitled “Smart Ethernet Network Interface Cards”,
`which Berend Ozceri is developing, printed Nov. 25, 1998, 2 pages.
`Internet pages of Xaqti corporation entitled “GigaPower Protocol
`Processor Product Review,” printed Nov. 25, 1999, 4 pages.
`U.S. Appl. No. 60/283,896, Titled: CRC Calculations for Out of
`Order PUDs, filed Apr. 12, 2003, Inventor: Amit Oren, Assignee:
`Siliquent Technologies Ltd.
`Internet pages entitled “DART: Fast Application Level Networking
`via Data-Copy Avoidance,” by Robert J. Walsh, printed Jun. 3, 1999,
`25 pages.
`Andrew S. Tanenbaum, Computer Networks, Third Edition, 1996,
`ISBN 0-13-349945-6.
`
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`tecture for Server Systems”, by P. Druschel and G. Banga,14 pages.
`Internet RFC/STD/FYI/BCP Archives
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`eration”, copyright Wind River Systems, 2001, 2 pages.
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`Adapters”, Copyright Intel Corporation, 1999, 8 pages.
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`ference on Local Computer Networks, 18 pages, Sep. 30-Oct. 3,
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`Engine Chipset”, from Hot Chips II], 16 pages, Aug. 26-27, 1991.
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`(10 pages).
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`tecture, 4 pages, printed Feb. 19, 2001.
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`system Architecture for Server Systems”, by Peter Druschel and
`Gaurav Banga, 14 pages.
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`from 15th Conference on Local Computer Networks, 5 pages, Sep.
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`Engine (ROPE)for a multiple-layer bypass architecture,” Protocols
`for High Speed Networks, pp. 224-239, 1995.
`
`* cited by examiner
`
`INTEL Ex. 1258.004
`
`INTEL Ex. 1258.004
`
`

`

`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 1 of 72
`
`US 7,496,689 B2
`
`==
`
`|
`
`I J
`
`1
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`po------7-7 ¢
`|
`SYSTEM
`T OTTE |
`i
`|
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`115
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`|
`HASH
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`114.
`TABLE
`BUCKETS
`||
`CAM
`
`105
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`INSRAM 17
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`104
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`8
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`INTERFACE
`DEVICE
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`22
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`PROCESSOR THAT
`IMPLEMENTS
`PROTOCOL STACK
`
`FIG. 1
`
`INTEL Ex. 1258.005
`
`INTEL Ex. 1258.005
`
`

`

`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 2 of 72
`
`US 7,496,689 B2
`
`WYOWHSNI
`
`(SSIMLNAze)
`
`"90ud
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`zo,4830|diisaavebyov\joearto
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`
`dolousdious
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`(91)(ze)
`
`INTEL Ex. 1258.006
`
`INTEL Ex. 1258.006
`
`
`
`
`
`

`

`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 3 of 72
`
`US 7,496,689 B2
`
`START
`
`rc 200
`OBTAIN AVAILABLE "PROCESSOR CONTEXT"
`
`201
`
`POP RECEIVE DESCRIPTOR AND HASH OFF THE RECEIVE DESCRIPTOR
`
`QUEUE CHECK ATTENTION BIT, IF SET THEN GO TO SLOW-PATH(END)
`
`203
`
`
`
`¥
`IF ATTENTION BIT IS NOT SET, THEN START THE DMA OF
`
`THE HEADER FROM DRAM TO SRAM
`¥
`
`BITS[13:2}] OF THE HASH ARE THE HASH BUCKET NUMBER, CHECK THE
`CORRESPONDING HASH BUCKET STATUS BYTE TO SEE IF THE BUCKETIS IN
`
`SRAM (CACHE)
`v
`IF THE BUCKETIS IN CACHE, THEN WAIT FOR THE HEADER DMA TO
`
`COMPLETE
`
`r~ 204
`
`rn 205
`
`IF THE BUCKETIS NOT IN CACHE, THEN IDENTIFY A FREE HASH SLOT FROM
`Q_FREEHASHSLOTS AND DMA THE HASH BUCKET FROM DRAMINTO THE
`FREE SLOT IN SRAM, SET THE HASH BUCKET STATUS BYTE TO POINT TO THE
`NOW OCCUPIED SLOT
`
`206
`
`SEARCH THE HASH BUCKET(IN SRAM) FOR THE TCB NUMBER,USE BITS[1:0]
`OF THE HASH TO DETERMINE THE FIRST HASH ENTRY TO CHECK, CHECK
`
`CONSECUTIVE HASH ENTRIES IN THE BUCKET FROM THERE
`
`207
`
`208
`
`IF A MATCH IS NOT FOUND IN THE BUCKET, THEN GO TO SLOW-PATH(END)
`
`IF A MATCH IS FOUND IN THE BUCKET, THEN GET THE TCB NUMBER FROM
`THE HASH BUCKET ENTRY
`
`
`v
`210
`ATTEMPT TO LOCK THE INDICATED TCB BY SETTING THE TCB'S LOCK BIT
`
`209
`
`[
`
`FIG. 3A
`
`INTEL Ex. 1258.007
`
`INTEL Ex. 1258.007
`
`

`

`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 4 of 72
`
`US 7,496,689 B2
`
`
`
`
`
`
`
`
`
`
`
`212
`
`214
`
`IF THE TCB IS LOCKED AS INDICATED BY THE LOCKBIT, THEN INSERT THE
`RUNNING PROCESSOR CONTEXTINTO THE TCB LOCK TABLE AND SUSPEND.
`WHEN THE TCB IS UNLOCKED BY THE CURRENT OWNER,A TCB LOCK TABLE
`CAM AND THE LOCK TABLE ARE USED TO IDENTIFY THE NEXT WAITING
`PROCESSOR CONTEXT. THIS PROCESSOR CONTEXTIS RESTARTED.
`
`
`
`
`
`ONCE THE PROCESSOR CONTEXT HAS LOCKED THE MATCHED TCB, THEN
`SEARCH THE INSRAM CAM FOR THE TCB SLOT NUMBER. IF THE TCB SLOT
`
`
`NUMBER IS IN THE INSRAM CAM, THEN THIS TCB 1S IN THE TCB SRAM
`
`CACHE.
`213 _
`
`
`
`IF THE TCB SLOT NUMBER IS FOUND IN THE INSRAM CAM, THEN DO FAST-
`
` PATH RECEIVE PROCESSING (END)
`
`
`
`IF THE TCB SLOT NUMBER IS NOT FOUND IN THE INSRAM CAM, THEN
`
`IDENTIFY ALRU SLOT IN THE TCB SRAM CACHE AND DMA THE TCB FROM
`DRAM INTO THE LRU SLOT
`
`
`PUT THE TCB SLOT NUMBER INTO THE SRAM CAM
`
`
`
`
`DO FAST-PATH RECEIVE. PROCESSING (END)
`
`FIG. 3B
`
`KEY TO FIG. 3
`
`FIG.3A
`
`FIG.3B
`
`FIG.3
`
`INTEL Ex. 1258.008
`
`INTEL Ex. 1258.008
`
`

`

`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 5 of 72
`
`US 7,496,689 B2
`
`300
`~~ Le
`COMPUTER
`396
`
`NETWORK
`
`
`
`NETWORK
`INTERFACE
`
`
`
`
`
`CPU EXECUTES
`INSTRUCTIONS
`THAT IMPLEMENT
`PROTOCOL STACK
`
`30300
`
`301
`
`
` NETWORK
`
`
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`INTERFACE
`
`DEVICE
`
`
`
`CPU EXECUTES
`INSTRUCTIONS
`THAT IMPLEMENT
`PROTOCOL STACK
`
`p-—-—----~~-~~~-~--~~--—
`COMPUTER
`
`301
`
`
`
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`NETWORK
`CPU EXECUTES
`
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`INTERFACE
`INSTRUCTIONS
`
`DEVICE
`THAT IMPLEMENT
`|
`|
`PROTOCOL STACK
`
`
`LOCAL BUS
`
`| |
`
`HOST BUS |
`
`INTEL Ex. 1258.009
`
`I|
`
`NETWORK
`
`
`
`
`
`INTEL Ex. 1258.009
`
`

`

`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 6 of 72
`
`US 7,496,689 B2
`
`
`
`HOST BUS
`510
`
`HOST
`
`
`
`
`I
`CPU EXECUTES
`BRIDGE
`
`INSTRUCTIONS
`501
`|
`
`THAT IMPLEMENT
`|
`|
`
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`NETWORK |;|PROTOCOL STACK
`
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`ty
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`|
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`|
`|
`PROTOCOL
`DEVICE
`
`|
`801
`STACK
`
`|
`NETWORK
`
`BRIDGE
`
`
`INTEL Ex. 1258.010
`
`INTEL Ex. 1258.010
`
`

`

`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 7 of 72
`
`US 7,496,689 B2
`
`rocco tro oe ee eeee eeeH
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`Reg File
`
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`
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`
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`
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`
`FLASH
`
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`
`INTEL Ex. 1258.011
`
`INTEL Ex. 1258.011
`
`

`

`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 8 of 72
`
`US 7,496,689 B2
`
`Datapath Bandwidth
`
`(125MB/s/1000Basc) x 2 (full duplex) x 1 connections
`
`Average frame size
`Frame rate = 250MB/s / 512B
`
`Overhead / frame = (256B context read * 25%) + (96B header read) +
`(192B context write * 25%) + (64B misc.)
`
`Total bandwidth = (512B in) + (512B out) + (272B Cpu)
`
`Dram Bandwidth required = (1296B/frame) x (488,280 frames/s)
`
`Dram Bandwidth @ 150MHz = (64 bytes / 126.6ns)
`
`PCI Bandwidth required
`
`PC] Bandwidth available @ 33 MHz, 64b, average
`
`PCI Bandwidth available @ 66 MHz, 64b, average
`
`=
`
`=
`
`=
`
`=
`
`=
`
`=
`
`=
`
`=
`
`=
`
`=
`
`250 MB/s
`
`512B
`
`488,280 frames/s
`
`272B / frame
`
`1296B / frame
`
`632.8MB/s
`
`505MB/s
`
`250MB/s
`
`200MB/s
`
`450MB/s
`
`FIG. 11
`
`Cpu Bandwidth
`
`Required instructions / frame (per Clive)
`
`Ack frames per receive
`
`Average instructions/Rev = 250 + (220 * .5)
`Receive frame interval = 512B / 125MB/s
`
`=
`
`-
`
`=
`=
`
`Instructions / frame @ 100MHz = (4.27us/frame) / (1 5ns/instruction) =
`
`250 instructions/rcv
`
`220 instructions/ack
`
`i)
`
`360 instructions/frame
`
`4.267 us
`
`284 instructions/frame
`
`FIG. 12
`
`INTEL Ex. 1258.012
`
`INTEL Ex. 1258.012
`
`

`

`
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`Cillarenett]|tet]||SBRSSEBREEEPreSSSSeseasagsssSeSeeces
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`
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`
`1
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`
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`
`FIG. 13/1
`—
`
`
`
`
`
`
`
`PCL INTD_L
`
`_____/
`
`INTEL Ex. 1258.013
`
`I I I l
`
`PCLADI9
`
`PCL AD22
`
`PCL_AD30
`PCL AD31
`
`PCLAD33
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`PCI_AD43
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`
`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 9 of 72
`
`US 7,496,689 B2
`
`PIN ASSIGNMENTS
`BALL
`
` BALL|SIGNAL DESCRIPTION
`
`Y19
`
`a I
`
`—
`
`
`
`INTEL Ex. 1258.013
`
`

`

`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 10 of 72
`
`US 7,496,689 B2
`
`BALL|SIGNAL DESCRIPTION
`
`
`
`
`
`
`
`
`
`
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`
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`
`
`Hi7
`
`
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`
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`UL0
`
`
`
`
`
`
`
`
`
`
`
`
`[D9|EXTPWREN
`All
`
`
`
`
`CLK_SEL_0
`CLKSELI
`PWR_GOOD
`AUX_PWR_GOOD
`NAND_OUT
`
`
`
`
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`M10
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`PLL_VSS
`
`
`|Bb|TSTisd|D6|VDDiCid
`
`
`
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`
`
`
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`
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`
`
`FIG. 13/2
`
`INTEL Ex. 1258.014
`
`INTEL Ex. 1258.014
`
`

`

`U.S. Patent
`
`
`
`
`
` —Ase}—fealealejen|alesfeatealaleafesloolefeafoeiast]stoolsaie)elaRioocl|RoelRinjoolaialosaiagininiaiaie
`
`
`
`
`
`
`
`
`
`Feb. 24, 2009
`
`==“A
`
`AL DESCRIPTION
`
`A_TXC
`A_CRS
`
`NKA_STAT
`A_TXD0
`A_TXD1
`
`A_TXD3
`
`A_TXER
`
`DIO
`
`M_DATA_0
`M_DATA_1
`M_DATA.2
`M_DATA_3
`M_DATA_4
`M_DATA_5
`M_DATA_6
`M_DATA_7
`M_ADDR_0
`M_ADDR_1
`M_ADDR
`M_ADDR_3
`M_ADDR_4
`M_ADDR_5
`M_ADDR_6
`
`M_ADDR_8
`M_ADDR_9
`M_ADDR_10
`M_ADDR_11
`M_ADDR_12
`
`M_ADDR_14
`M_ADDR_15
`RAM_CLK
`M_CKE
`
`M_RAS_L
`M_CAS_L
`
`Sheet 11 of 72
`
`
`
` —_pszSacEAESESepSessagesCASalaSicaaelq
`
`US 7,496,689 B2
`
`SIGNAL DESCRIPTION
`RAM_WE_L
`RAM_DQM
`EEPROM_SDI
`EEPROM_SDO
`EEPROM_CS
`EEPROM_CLK
`FSH_CD_L
`
`DIQSPOPOPY)OPOWOIOYRLYOJOOTO]LEOOPOYOWOPOPOOOWOOOJOJOEO
`
`
`
`FIG. 13/3
`
`INTEL Ex. 1258.015
`
`INTEL Ex. 1258.015
`
`
`
`
`

`

`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 12 of 72
`
`US 7,496,689 B2
`
`ONiFETCHffArf (OAD
`=EfLOAD *
`CLK
`TTT
`lalCtl
`
`
`ASh ALU|FLAG i4 ite
`
`cul
`
`ee
`
`
`T-
`
`Istacn) Addr
`pc
`BASED
`
`
`Dis crx|REGS|ccs|REGs REG|Addr BASE aa
`
`
`
`DECODER[rsaMores
`SoBemmee
`FILE7imto__FLAG a San|DEBUG
`
`CTX ttcf SEL acu
`
`PC|STACK} Addr
`
`FIG. 14
`
`INTEL Ex. 1258.016
`
`INTEL Ex. 1258.016
`
`

`

`U.S. Patent
`
`Feb. 24, 2009
`
`Sheet 13 of 72
`
`US 7,496,689 B2
`
`INSTRUCTION-WORD FORMAT
`
`
`
`Jct 1,0=TstSel,0b0000000, 0b00, AluOp, OpdASel, OpdBSel, Literal
`
`
`
`
`
`
`
`Jef
`0b0000000,
`0b00,
`AluOp,
`OpdASel,
`OpdBSel,
`I'bl
`TstSel,
`Literal
`Jmp
`0b0000000
`0b01,
`AluOp,
`OpdASel,
`OpdBSel,
`1p0—sFigSel,
`—_Literal
`Jsr
`0b0000000
`0b10,
`AluOp,
`OpdASel,
`OpdBSel,
`1'bO
`FigSel,
`Literal
`
`Rts FigSel,—_Literal0b0000000 0b11, AluOp, OpdASel, OpdBSel, I'b1
`
`
`
`
`
`
`Rtt
`0b0000000
`0b01,
`AluOp,
`OpdASel,
`OpdBSel,
`Itbl
`TstSel,
`Literal
`Rtf
`0b0000000
`0b10,
`AluOp,
`OpdASel,
`OpdBSel,
`1b1
` TstSel,
`Literal
`Cont
`0b0000000
`0b] 1,
`AluOp,
`OpdASel,
`OpdBSel,
`I'bO
`FigSel,
`Literal
`Map
`MapAddr
`Obxx,
`Obxxxxx,
`ObXxxxxxxxx,
` Obxxxxxxxxx,
`I'bx
`Ohxx,
`Ohxxxx
`
`FIG. 15
`
`SEQUENCER BEHAVIOR
`PgmCtrl
`= {Instruction bits 48:47, Instruction bit 23};
`DbgAddr
`= DbgAddr + (Execute & DbgMa);
`InstrFetchAddr
`= DbgMd ? DbgAddr:InstrAddr;
`Pc
`= InstrAddr + (Execute & ~DbgMd);}
`
`if (MapEn & (MapAddr != 0b0000000)){
`InstrAddr = 0h8000 |(MapAddr << 3) | Pc[2:0]; }
`else if (PgmCtrl == Jct && TstSel)
`InstrAddr = Pe:(AluDst==Pc) ? AluOut:Literal;
`else if (PgmCtrl == Icf && ~TstSel)
`InstrAddr = Pc:(AluDst==Pc) ? AluOut:Literal;
`else if (PgmCtrl == Jmp)
`InstrAddr = (AluDst==Pc) ? AluOut:Literal;
`else if (PgmCtrl == Jsr) {
`InstrAddr = (AluDst==Pc) ? AluOut:Literal;
`Stack{StackPtr] = NextPc;
`StackPtr = StackPtr + 1; }
`{
`else if (PgmCtr] == Rtt && TstSel)
`InstrAddr = Stack[StackPtr - 1] ;
`StackPtr = StackPtr -1 ; }
`else if (PgmCtrl == Rtf && ~TstSel) {
`InstrAddr = Stack{StackPtr — 1];
`StackPtr = StackPtr -1 ; }
`else if (PgmCtrl == Rts) {
`InstrAddr = Stack[S