United States Patent [19]
`Cohen
`
`[111
`[45]
`
`Patent Number:
`Date of Patent:
`
`4,701,843
`Oct. 21], 1987
`
`[54]
`
`[75]
`[73]
`[21]
`[22]
`[511
`[52]
`[58]
`
`[56]
`
`REFRESH SYSTEM FOR A PAGE
`ADDRESSABLE MEMORY
`Inventor:
`Morris Cohen, San Diego, Calif.
`Assignee:
`NCR Corporation, Dayton, Ohio
`Appl. No.: 718.764
`Filed:
`Apr. 1, 1985
`
`Int. Cl.‘ ............................................ .. G06F 12/16
`US. Cl. ................................... .. 364/200; 365/222
`Field of Search
`364/200 MS File, 900 MS File;
`365/222, 235
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,846,765 [1/1974 De Vries ....................... .. 365/222 X
`4,106,108 8/1978 Cislaghi et all
`364/200
`4,172,282 10/1979 Aichelmann et al. .
`.. 365/222
`4,238.842 12/1980 Aichelmann
`4,328,566 5/1982 Thaler ............................... .. 365/222
`
`FOREIGN PATENT DOCUMENTS
`2095442 9/1982 United Kingdom
`365/222
`Primary Examiner—Raulfe B. Zache
`
`Assistant Examiner-Florin Munteanu
`Attorney, Agent, or Firm-Wilbert Hawk. Jr.; Edward
`Dugas; Floyd A. Gonzalez
`[5 7]
`ABSTRACT
`A computer memory including a memory subsystem
`controller having a circuit for providing a plurality of
`block select signals and a raw address. A plurality of
`memory blocks is provided, with one of the memory
`blocks being provided for each of the block select sig
`' nals from the memory subsystem controller. Each of the
`memory blocks includes random access memory
`(RAM) devices for storing data, and a refresh circuit for
`refreshing its associated RAM devices independent of
`the refreshing of the RAM devices of the other blocks.
`The refreshing of the refresh circuit occurs, if possible,
`when its associated memory block is not selected by its
`corresponding block select signal from the memory
`subsystem controller. A re-establishing circuit is in
`cluded in each memory block which receives a row
`address from the memory subsystem controller and
`re-establishes the received row address in its RAM
`devices after they have been refreshed.
`
`11 Claims, 14 Drawing Figures
`
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`Page 1 of 17
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`SAMSUNG EXHIBIT 1092
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`

`

`U. S. Patent Oct. 20,1987
`
`Sheetl 0f8
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`4,701,843
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`Page 2 of 17
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`SAMSUNG EXHIBIT 1092
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`

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`U. S. Patent Oct. 20,1987
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`Sheet2 of8
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`Page 3 of 17
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`SAMSUNG EXHIBIT 1092
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`

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`U. S. Patent Oct. 20, 1987
`
`Sheet3 0f8
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`4,701,843
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`Page 4 of 17
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`SAMSUNG EXHIBIT 1092
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`

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`U. S. Patent Qct. 20,1987
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`Sheet 4 of 8
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`SAMSUNG EXHIBIT 1092
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`

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`U. S. Patent Oct. 20,1987
`
`SheetS of8
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`4,701,843
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`Page 6 of 17
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`SAMSUNG EXHIBIT 1092
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`U. S. Patent Oct. 20,1987
`
`Sheet 6 of 8
`
`4,701,843
`
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`Page 7 of 17
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`SAMSUNG EXHIBIT 1092
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`U. S. Patent Oct. 20,1987
`
`Sheet 7 of 8
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`4,701,843
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`Page 8 of 17
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`Page 8 of 17
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`SAMSUNG EXHIBIT 1092
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`

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`U. S. Patent Oct. 20,1987
`
`Sheet 8 of 8
`
`4,701,843
`
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`SAMSUNG EXHIBIT 1092
`Page 9 of 17
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`Page 9 of 17
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`SAMSUNG EXHIBIT 1092
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`

`

`1
`
`REFRESH SYSTEM FOR A PAGE ADDRESSABLE
`MEMORY
`
`5
`
`10
`
`BACKGROUND OF THE INVENTION
`The present invention relates to memory devices
`usable in data processing systems, and more particularly
`to an apparatus for enhancing the operation of random
`access memory (RAM) devices.
`Data processing systems having a main memory
`made up of a plurality of RAM memory devices ar
`ranged into blocks are known. Each block is selected by
`select lines such that only the block of interest is se
`lected during a memory operation.
`Also known are memory refresh schemes in which
`the memory row of the RAM devices is refreshed with
`each memory read, with each memory access, and auto
`matically at the end of a set period of time. Many RAM
`devices require external means for generating and mul
`tiplexing row addresses for refreshing. Some RAM
`devices incorporate a row address counter and a multi
`plexer for refreshing, but require an external refresh
`timing signal. Refresh counters which generate the row
`address to be refreshed during each time interval are
`also known.
`RAM devices which operate in a “page mode" in
`which sequential accesses to the device may be made in
`the same row are also known. In the page mode opera
`tion, the original row address strobed into the device at
`the beginning of the page mode operation is held in the
`device and only new column addresses are strobed into
`the device, allowing for faster operation.
`US. Patents of interest are: 4,292,676 issued Sept. 29,
`198] to Heniz; 4,296,480 issued Oct. 20, I981 to Baton,
`Jr. et al.; 4,328,566 issued May 4, 1982 to Thaler;
`4,333,167 issued Jan. l, 1982 to McElroy; 4,347,589
`issued Aug. 31, 1982 to Proebsting; 4,4l5,992 issued
`Nov. 15 1983 to Adlhock; and 4,486,860 issued Dec. 4,
`1984 to Takemae et al.
`
`4,701,843
`2
`mines whether a long cycle or a short cycle is required
`for the current memory cycle.
`The disclosed apparatus also includes a refresh circuit
`which enhances the operation of memory subsystems
`consisting of blocks which include RAM devices that
`require refresh cycles. This refresh circuit refreshes all
`blocks that are not being used at the beginning of a
`refresh window of time and prevents blocks that are
`being used at the beginning of a refresh window of time
`from being refreshed until they are no longer being
`used. If, however, any blocks are continuously used
`throughout the refresh window, the memory operation
`is interrupted and these blocks are refreshed at that time
`so that no data is lost.
`Since the likelihood is great that adjacent operations
`in a block will address the same row, and a refresh
`operation destroys the last row status in RAM devices
`with page mode, Intel's Ripplemode, static column, or
`similar operating modes, the disclosed apparatus in
`cludes a re-established circuit which re-establishes in
`the memory devices the last row whose address is in the
`last row register associated with that block. The re
`established operation occurs immediately after the re
`fresh operation, unless the block is selected before the
`end of the block’s refresh operation. If the block is so
`selected, then a normal long cycle is taken, thereby
`strobing in the row that is addressed by the present
`operation. If a block is in a re-establishment operation
`and is selected before a critical time, then the apparatus
`converts the re-establishment operation into a normal
`long cycle.
`It is thus a primary object of the present invention to
`provide an apparatus which enhances the operation of
`memory subsystems.
`It is also an object of the present invention to provide
`an apparatus which refreshes blocks of memory when
`they are not otherwise being used.
`It is also an object of the present invention to provide
`an apparatus which permits blocks of memory to oper
`ate in a short cycle if the present row address is the same
`as the last row address strobed into the selected block of
`memory.
`It is also an object of the present invention to provide
`an apparatus which re-cstablishes the last row address in
`each block of memory after that block is refreshed.
`It is also an object of the present invention to provide
`an apparatus which converts the re-establish operation
`into a memory operation if the block is selected while it
`is being refreshed or during the early part of the re
`establishment operation.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 discloses a block diagram of a data processing
`system of the present invention;
`FIG. 2 is a block diagram of a memory block of FIG.
`
`25
`
`45
`
`SUMMARY OF THE INVENTION
`In a speci?c embodiment, a computer memory is
`provided which includes means for providing a plural
`ity of block select signals. A plurality of memory blocks
`is provided, with one of the memory blocks being pro
`vided for each of the block select signals from the mem
`ory subsystem controller. Each of the memory blocks
`includes random access memory (RAM) devices for
`storing data, and a refresh circuit for refreshing its asw
`50
`ciated RAM devices independent of the refreshing of
`the RAM devices of the other blocks. The refreshing of
`the refresh circuit occurs when its associated memory
`block is not selected by its corresponding block select
`signal from the memory subsystem controller.
`The present invention is directed to an apparatus for
`enhancing the operation of memory subsystems consist
`ing of blocks which incorporate RAM devices with
`page mode, Intel’s Ripplemode, static column, or simi
`lar operating modes, all of which are referred to herein
`as a same row operating mode. The present invention
`includes a last row register associated with each block
`for storing the address of the last row strobed into the
`RAM devices of that block. It also includes a compari
`son circuit associated with each block which compares
`the row address for a current memory operation with
`the address in the last row register, and the result of the
`comparison associated with the selected block deter
`
`60
`
`1;
`
`FIG. 3 is a wave form diagram of the various signals
`of one of the memory chips of the memory block of
`FIG. 2;
`FIG. 4 is a block diagram of a RAS control circuit of
`a block control circuit of FIG. 2;
`FIG. 5 is a changed row indicating circuit of the
`block control circuit;
`FIG. 6 is a multiplexer control circuit of the block
`control circuit;
`FIG. 7 is a load register circuit of the block control
`circuit;
`
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`4,701, 843
`
`3
`FIG. 8 is a RAS/ signal control circuit of the block
`control circuit;
`FIG. 9 is a WE/ signal control circuit of the block
`control circuit;
`FIG. 10 is a CAS/ signal control circuit of the block
`control circuit;
`FIG. 11 is a END OF CYCLE signal control circuit
`of the block control circuit;
`FIG. 12 is a refresh control circuit of the block con
`trol circuit;
`FIG. 13 is a CAS-WE INHIBIT signal control cir
`cuit of the block control circuit; and
`FIG. 14 is a re-establish circuit of the block control
`circuit.
`
`4
`The data bus 18 of FIG. 1 is a multi-conductor data bus
`designated SYSTEM DATA in FIG. 2.
`The multiplexer 30 multiplexes addresses from the
`refresh row address bus 34, the system column address
`bus 36, or the last row register 26 dependent upon multi
`plexer select control signals transmitted over the con
`trol bus 50 from the block control circuit 24, as will be
`explained. A load conductor 52, from the block control
`circuit 24 to the last row register 26, controls loading
`the system row address from the bus 38 into the register
`26. The compare circuit 28 compares the address on the
`system row address bus 38 with the address in the last
`row register 26, and outputs a COMPARE/ signal over
`conductor 54 to the block control circuit 24. The COM
`PARE/ signal is high when the addresses are not equal,
`and low when the addresses are equal.
`Column address strobe (CASI), row address strobe
`(RAS/) and write enable (WE/) signals are transmitted
`over a control bus 58 from the block control circuit 24
`to the memory chips 32, as will be explained, to control
`the various memory operations of the chips 32. The
`various memory integrated circuit chips in 32 are ar
`ranged to supply or store all of the bits of, for instance,
`a word or an instruction stored in the chips 32 at the
`address supplied from address buses 36 and 38, as con
`trolled by control signals from control bus 58, in a well
`known fashion which will not be further explained
`herein.
`The clock 22 outputs four non-overlapped time
`pulses T1-T4 over time bus 60 to each of the memory
`blocks 14. Time delay circuits 61, 62, 63 and 64 are
`connected to the T1 conductor of time bus 60 to pro
`vide delayed time pulses RA, RB, W and C, respec
`tively. ‘RA marks the beginning of the charging of the
`RAS/ line before a memory operation, RB marks the
`ending of the RAS/ line charging, C marks the drop of
`the CAS/ signal to indicate to the memory chips 32 that
`a column address is being submitted, and W marks the
`drop of the WE/ signal to indicate to the memory chips
`32 that a write operation is to occur. The exact values of
`the time delays of circuits 61-64 depend on the design
`requirements of the memory chips which are used.
`In one preferred embodiment of the invention, the
`memory chips 32 are Intel 51C256-l5 dynamic random
`access memory (RAM) devices described in advance
`information available from Intel Corporation of Santa
`Clara, Calif. In that embodiment, Tl-T4 each have a
`non-overlapped waveform, each have a rise time of
`three nanoseconds, a high duration of ?ve nanoseconds,
`a fall time of three nanoseconds, and a low duration of
`54 nanoseconds for a total of 65 nanoseconds. RA has a
`waveform which has a high for a duration of from 10
`nanoseconds after the rise of T1 to 30 nanoseconds after
`the rise of T1. Similarly, RB is high from 25 nanosec
`onds to 45 nanoseconds after the rise of T]; C is high
`from 10 nanoseconds to 50 nanoseconds after the rise of
`T1; and W is high from ?ve nanoseconds to 50 nanosec
`onds after the rise of T1. It will be understood that if
`other memory chips are used, the timing of the various
`time pulses will vary depending upon the design of the
`chips used. The RA, RB, C and W timing pulses are also
`supplied to each of the memory blocks 14 over time bus
`
`A signal REFRESH WINDOW on the refresh win
`dow conductor 40 includes a train of pulses having a
`width which, when ended, leave sufficient time to re
`fresh the memory chips 32 without losing data. As will
`be explained, the block control circuit 24 includes cir
`
`35
`
`40
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`FIG. 1 is a block diagram of a data processing system
`of the present invention having a memory 12 which
`includes a memory subsystem controller 10 and a plural
`ity of blocks 14. A memory bus 11 provides the means
`for connecting the memory 12 to a processor, [/0 con
`troller, or other unit that can initiate a memory opera
`tion. An address and control bus 16 is connected be
`tween the memory subsystem controller 10 and each of
`the memory blocks 14 for transmitting address and
`control signals for controlling memory operations. A
`data bus 18 is also connected between the memory sub
`system controller 10 and each of the memory blocks 14
`for transmitting data as speci?ed by the address and
`control signals.
`As mentioned, the memory 12 is divided into conve
`nient sized blocks 14 (shown in FIG. 1 as four blocks
`designated BLOCK l-BLOCK 4. Each block 14 has its
`own block select line 20 between each individual block
`14 and the memory subsystem controller 10. When a
`memory operation such as a read or write is to occur,
`the memory subsystem controller 10 places the proper
`address and control signals on bus 16 to all of the blocks
`14, and the desired block is selected by activating the
`appropriate block select line 20.
`Among the advantages of this con?guration, is the
`fact that only the memory block actually needed for a
`desired memory operation is active, while the rest are
`idle. If the memory blocks 14 are made up of volatile
`memory elements which must be periodically refreshed,
`the refresh operations may be conducted on those mem
`ory blocks 14 which are idle without affect on the data
`processing system. A free running clock 22 is provided,
`and is connected to each memory block 14 by a time bus
`60 for providing time pulses to each memory block 14,
`as will be explained.
`FIG. 2 is a block diagram of one of the memory
`blocks 14 shown in FIG. 1 along with the clock 22 of
`55
`FIG. 1. Each memory block 14 includes a block control
`circuit 24, whose elements will be discussed later, a last
`row register 26, a compare circuit 28, a multiplexer 30
`designated MUX, and a plurality of memory integrated
`circuit chips 32. A refresh row address bus 34, a system
`column address bus 36, a system row address bus 38, a
`refresh window conductor 40, a refresh start conductor
`42, a system write conductor 44, and an end of cycle
`conductor 46, all included in the address and control
`bus 16 of FIG. 1, are connected as shown to the mem
`ory block 14. The block select conductor 20 of FIG. 1,
`designated in FIG. 2 as BLOCK N SELECT, is pro
`vided for the particular memory block 14 of FIG. 2.
`
`65
`
`45
`
`50
`
`60
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`Page 11 of 17
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`

`4,701,843
`5
`cuitry to refresh the memory chips 32, to the extent
`possible, during the REFRESH WINDOW when the
`memory block 14 is not selected. but if the memory
`block 14 remains selected during the entire refresh win
`dow, the memory chips 32 will be refreshed immedi
`ately after the end of the REFRESH WINDOW dura
`tion and before data is lost.
`At this point the operation of the memory chips 32
`will be reviewed. FIG. 3 is a waveform diagram of the
`various signals of one of the memory chips 32 for per
`forming a memory write operation. Waveform 61 is the
`waveform of the RAS/ signal to select a ROW address
`for the memory chip. In many memory operations it is
`necessary to precharge the RAS/ line before a memory
`operation occurs. As shown in FIG. 3, RA designates
`when the RAS/ signal goes high to start precharging,
`and RB designates when the RAS/ signal goes low to
`indicate that the address on the address terminals of the
`memory chip is a row address. The time between RA
`and RB is thus the precharge time. It will be noted that
`20
`after the RAS/ signal goes down at RB, it stays low
`during the rest of the memory operation.
`Waveform 62 is the waveform of the CAS/ signal for
`selecting a column address for the memory chip. The
`CAS/ signal goes low at C to indicate to the memory
`25
`chip that the address on the address terminals of the
`memory chip is a column address. Waveforms 63 and 64
`indicate an envelop for the signals on the address termi
`nals of the memory chip. It will be noted that the row
`address 65 is placed on the address terminals of the
`memory'chip before the RAS/ signal goes low, and is
`held for a sufficient time to insure that the row address
`is properly accepted by the memory chip. The column
`address 66 is then placed on the address terminals of the
`memory chip before the drop of the CAS/ signal at C,
`and is held for a sufficient time to insure that the column
`address is properly accepted by the memory chip.
`Waveform 67 is the waveform of the WE/ signal. The
`WE/ signal goes low at W to indicate to the memory
`chip that a write operation is to occur. Waveforms 68
`and 69 indicate an envelop for the signals on the data-in
`terminal of the memory chip. Since FIG. 3 illustrates a
`write operation, the data to be written in the memory
`chip at the addressed location is placed on the data-in
`terminal. In this case the data-out signal shown at 70
`45
`stays at a high impedance level. If the memory opera~
`tion is a read, the WE/ signal is held high, and the data
`stored in the memory chip at the addressed location
`appears on the data-out terminal.
`-
`The preferred memory chips 32 of the memory block
`14 of FIG. 2 are capable of two modes of operation, a
`short cycle mode wherein consecutive operations are
`con?ned to the same row, and a long cycle mode
`wherein consecutive operations occur in different rows.
`In the preferred Intel 5lC256-l5 RAM devices, the
`short cycle mode is referred to by the Intel trademark
`Ripplemode. In Ripplemode, the RAS/signal is held
`low, the desired column address is placed on the address
`terminals of the memory chip, and the CAS/ signal is
`made low. If the WE/ signal is held high, a read occurs,
`or if the WE/ signal is made low, at the correct time, a
`write occurs at the indicated column of the selected
`row. Another memory operation in the same row may
`then be made by continuing to hold the RAS/ signal
`low, and strobing in a new column address with the
`CAS/ signal.
`The block control circuit 24 which generates the
`various memory control signals to operate the memory
`
`6
`operations of the memory chips 32 in an efficient man
`ner, will now be described.
`FIGS. 4-13 show the various elements of the block
`control circuit 24 of FIG. 2. FIG. 4 is a block diagram
`of a RAS control circuit which controls the operation
`of the block control circuit 24 during many of the mem
`ory operations of the associated block memory 14. The
`output of the RAS control circuit has four cycles, each
`having its own output signal of RAS PHASE 1, RAS
`PHASE 2, RAS PHASE 3, and RAS HOME, respec
`tively. RAS PHASE 1, RAS PHASE 2 and RAS
`PHASE 3 each have a total duration of the T1-T4
`timing pulses described in connection with FIG. 2.
`Referring to FIG. 4, an AND gate 71 has its output
`connected to the clock input of a two-bit counter 72.
`One input ofAND gate 71 is connected to a RAS CON
`TROL conductor, to be discussed, and the other input
`is connected to a T1 conductor 73 which comes from
`the time bus 60 of FIG. 2. The outputs of the two-bit
`counter 72 is connected to the inputs of a two-to-four
`converter 74. The first output 75 of the converter 74
`supplies the RAS HOME signal, and the second, third
`and fourth outputs 76-78 supply the RAS PHASE 1
`through RAS PHASE 3 signals, respectively. Inverter
`79 inverts the RAS HOME signal to a RAS HOME/
`signal. It will be understood that while the RAS CON
`TROL signal is high, each T1 pulse on 73 will cause the
`two-bit counter to increment its count. This will in turn
`cause the outputs 75-78 to sequentially go high, starting
`first with RAS HOME, and then RAS PHASE 1, and
`so forth.
`RAS PHASE 3 is received by the reset input of a
`?ip/?op 80 whose set input is connected to an OR gate
`82. The inputs of the OR gate 82 receive the signals
`REFRESH, RE-ESTABLISH and CHANGE ROW,
`to be discussed later. The output 81 of ?ip/?op 80 is
`connected to one input of an AND gate 84, and the
`negation output 83 of ?ip/?op 80 is connected to one
`input of an AND gate 86. The other input of AND gate
`84 receives the RAS HOME signal from output 75. The
`AND gate 86 also receives the RAS HOME signal from
`75, and the T4 signal on conductor 88 of the time bus 60
`of FIG. 2. The output of AND gate 84 is connected to
`the set input of ?ip/flop 90, whose output 91 provides
`the RAS CONTROL signal previously mentioned. The
`negation output 83 of ?ip/?op 80 is connected to the
`reset input of the ?ip/?op 90 through AND gate 86.
`It will thus be understood that when the RAS control
`circuit of FIG. 4 is in the RAS HOME state, the RAS
`HOME signal will be high. When any of the RE
`FRESH, RE-ESTABLISH or CHANGE ROW sig
`nals go high, flip/?op 90 will be set, causing the RAS
`CONTROL signal to go high. The next T1 pulse will
`turn on AND gate 71, thus incrementing the count of
`the counter 72, and changing the state of the RAS con
`trol circuit to RAS PHASE 1. The RAS control circuit
`will increment through the RAS cycle until the RAS
`PHASE 3 state is reached. A high RAS PHASE 3
`signal will reset flip/flop 80. When the RAS HOME
`state is reached, a high T4 signal turns on AND gate 86,
`resetting ?ip/?op 90 and causing the RAS CONTROL
`signal to go low. This prevents AND gate 71 from
`turning on with T1, thereby holding the RAS HOME
`signal high until the arrival of a high REFRESH, RE
`ESTABLISH or CHANGE ROW signal at AND gate
`82. It will thus be understood, that the end of the RAS
`cycle is the RAS HOME state of the RAS control cir
`cuit of FIG. 4.
`
`55
`
`65
`
`30
`
`35
`
`Page 12 of 17
`
`SAMSUNG EXHIBIT 1092
`
`

`

`7
`It will be understood that when a read or write opera
`tion in a particular memory block 14 is to take place, the
`BLOCK N SELECT signal for that particular memory
`block will go high. If the operation is to be a write
`operation, the SYSTEM WRITE signal on conductor
`44 (FIG. 2) will also go high.
`The operation of a memory block for writing in a
`non-selected row will now be described. When any
`subsystem connected to the memory bus 11 of FIG. I is
`to write data into a memory block 14, the system row
`address is placed on bus 38, the system column address
`on bus 36, the signal on the proper BLOCK N SE
`LECT line 20 is raised, and the SYSTEM WRITE
`signal on line 44 is raised (see FIG. 2). The compare
`circuit 28 compares the address on bus 38 with the last
`row address in register 26, and, in this case, ?nds they
`are not the same and raises the COMPARE/ signal on
`conductor 54.
`Turning now to FIG. 5, the RAS HOME signal from
`the RAS control circuit of FIG. 4, the COMPARE/
`20
`signal on conductor 54 of FIG. 2, and the BLOCK N
`SELECT signal on conductor 20 of FIG. 2 are all re
`ceived by the inputs of an AND gate 92. The output of
`AND gate 92 is connected to one of the inputs of an OR
`gate 94, whose output is connected to the set input of a
`25
`flip/ flop 95. The output 96 of ?ip/?op 95 provides the
`CHANGE ROW signal, and its negation output 97
`provides the CHANGE ROW/ signal. The reset input
`of ?ip/?op 95 is connected to the RAS PHASE 3 out
`put 78 of FIG. 4. It can thus be seen that when the RAS
`30
`control circuit is in its RAS HOME state, the block is
`selected, and the row address is different than the last
`row address, then CHANGE ROW will go high and
`CHANGE ROW/ will go low. The high CHANGE
`ROW signal will start the RAS cycle as desc'ribed in
`connection with FIG. 4.
`Referring to FIG. 6, the CHANGE ROW signal
`from output 96 of ?ip/?op 95 of FIG. 5 is received by
`the input of an OR gate 100, whose output is connected
`to one of the inputs of an AND gate 102. The other
`40
`inputs of the AND gate 102 receive the RAS HOME/
`signal from inverter 79 of FIG. 4, and a REFRESH/
`signal. The output of AND gate 102 is connected to one
`conductor of the multiplexer control bus 50, and the
`other conductor receives a REFRESH signal. In all
`memory operations except a refresh operation, the RE
`FRESH signal is low, and the REFRESH/ signal is
`high, as will be explained. Thus, as soon as the RAS
`cycle goes to RAS PHASE 1, the RAS HOME/ signal
`will go high, turning on AND gate 102, making the
`multiplexer control code “01", directing the multiplexer
`30 to multiplex addresses from the last row register 26
`to the memory chips 32 (see FIG. 2).
`Referring now to FIG. 7, BLOCK N SELECT on
`conductor 20 of FIG. 2, and RAS PHASE 2 on output
`77 of FIG. 4 are received by the inputs of an AND gate
`104, whose output is connected to control line 52 of
`FIG. 2, which controls the loading of the last row regis
`ter 26. Thus when the block has been selected, and the
`RAS cycle of the circuit of FIG. 4 reaches RAS
`PHASE 2, the row address on bus 38 is loaded into
`register 26. It will be remembered that the multiplexer
`control bus 50 carries a code of “01" (refer to FIG. 6)
`which multiplexes the address loaded into register 26 to
`the address terminals of the memory chips 32 of FIG. 2.
`It will thus be understood that at T1 of RAS PHASE 2,
`the system row address will be presented to the memory
`chips.
`
`45
`
`8
`Referring to FIG. 8, RAS PHASE 1 of output 76 of
`FIG. 4 and RA of delay circuit 61 of FIG. 2 are re
`ceived by the inputs of an AND gate 106. RAS PHASE
`2 of output 77 of FIG. 4 and RB of delay circuit 62 of
`FIG. 2 are received by the inputs of an AND gate 108.
`The output of AND gate 106 is connected to the set
`input of a flip/flop I10, and the output of AND gate 108
`is connected to its reset input. The output 111, of ?ip/
`?op 110, provides the RAS/ signal of the control sig
`nals transmitted over control bus 58 of FIG. 2, and the
`negation output 112 of the ?ip/?op 110 provides an
`RAS signal. It will be understood that at RA during the
`RAS PHASE 1 state of the RAS cycle, AND gate 106
`will be turned on, causing the RAS/ signal to go high
`(see RA of FIG. 3), while at RB, during RAS PHASE
`2 state of the RAS cycle, AND gate 108 will be turned
`on, causing the RAS/ signal to go low (see RB of FIG.
`3). It will be remembered that at the beginning (T1) of
`RAS PHASE 2, the system row address in the last row
`register will be presented to the address terminals of the
`memory chips. After a speci?ed delay after T] of RAS
`PHASE 2, as determined by delay circuit 62 of FIG. 2,
`the RAS/ signal will go low, strobing the new row
`address into the memory chips of the selected block.
`Returning to FIG. 5, when RAS PHASE 3 of the
`RAS cycle of the circuit of FIG. 4 is reached, flip/flop
`95 will be reset, causing CHANGE ROW to go low and
`CHANGE ROW/ to go high. Referring to FIG. 6,
`CHANGE ROW/ going high will turn off OR gate .
`100, which in turn will turn off AND gate 102, and
`change the multiplexer control code to “00". This will
`cause the multiplexer 30 of FIG. 2 to multiplex the
`system column address on bus 36 to the address termi
`nals of the memory chips 32.
`Referring to FIG. 9, the SYSTEM WRITE signal on
`conductor 44 of FIG. 2, the BLOCK N SELECT signal
`on conductor 20 of FIG. 2, a CAS-WE INHIBIT signal
`to be explained later, the RAS HOME signal of output
`75 of FIG. 4, and the W signal from time delay circuit
`64 of FIG. 2 are all received by a respective input of a
`NAND gate 114. The output of NAND gate 114 pro
`vides the WE/ signal transmitted by control bus 58 of
`FIG. 2. As will be explained, the CAS-WE INHIBIT
`signal will be high in this operation. It will then be
`understood that at W during the RAS HOME state,
`which has been explained as being the last cycle of a
`RAS cycle, when the block is selected and a write is to
`occur, the WE/ signal will go low (see W of FIG. 3).
`Referring to FIG. 10, the RAS HOME signal of
`output 75 of FIG. 4, the C signal of time delay circuit 63
`of FIG. 2, the BLOCK N SELECT signal on conduc
`tor 20 of FIG. 2, and the CAS-WE INHIBIT signal are
`all received by a respective input of a NAND gate 116.
`The output of NAND gate 116 provides the CAS/
`signal transmitted by control bus 58 of FIG. 2. Thus, at
`time C after T1 of the RAS HOME state when the
`block is selected, the CAS/ signal will go low (see C of
`FIG. 3), strobing in the column address as previously
`described.
`Referring now to FIG. 11, the RAS HOME signal of
`output 75 of FIG. 4, the BLOCK N SELECT signal on
`conductor 20 of FIG. 2, the CAS-WE INHIBIT signal,
`and the T4 signal from clock 22 of FIG. 2 are all re
`ceived by a respective input of an AND gate 118. The
`output of AND gate 118 provides the END OF
`CYC