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`mm.“ HIGH-SPEED MODEM
`S: THEY RE NOT JUST FOR DATA ANYMORE .
`may”
`Innovative modem technologies pump data, fax, and voice-mail at blazing
`speeds. Just how do they get those 114 kbits on that 3-kHz line?
`“$353 MEMORY-CHIP STACKS SEND DENSITY SKYWARD . . . 69
`"E Vertical integration ofsilicon allows packaging ofextremely dense system
`memoryjn tiny volumes.
`
`. . 47
`
`. 77
`.
`applmnm BUILD A POWERFUL HOST-ESP INTERFACE .
`Dual-port memory combines the ease and cost of FIFOs with the datapath
`capability of custom hardware.
`HR
`DEBUGGING SYSTEMS: GETTING THE PIECES TO WORK TOGETHER . . . 87
`Fixing errors in embedded systems calls for teamwork—and tools.
`xx—
`DEBUGGING: ENTERPRISE INSTRUMENTATION .
`. .93
`Locating real~time bugs in embedded systems is especially tricky while
`integrating hardware and software.
`
`. 101
`.
`EBUGGING FOR REAL TIME: HARD CHOICES .
`Because every tool has an effect on the system, knowing your tools is the best
`defense.
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`s
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`1
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`"WWI INTEGRATED CONTROLLER SUITS LASER PRINTERS . . . 153
`lmwmm ICincludes DRAM/ROM control, DMA, parallel port, interrupt controller,
`counter-timer, configurable [/0 bus, and programmable I/0 lines.
`
`\ s
`
`zrwNic amen (USPS 172-080; ISSN 00184872) is published twice monthly except for 8 lame: in Ma and 8 issues in October by
`Milton Publishin Inc.f 1100 Superior Aye" Cleveland. OH 44114-2543. Paid rates fora oneyearsubscri
`n aremfollowa $105 US.
`$1850nmda, 21 Mexm.$256 nlernatmnalSucond—c as:
`[agepaidatCleveland.Ofl andaddllionalmaihn offices. Editorial end
`advertisin a dresses: ammonia owes. 611 Route #46 est. Hasbrouck Hei his, NJ 07604. Tel: lion: [3TH39343080. Facsimile
`ammonia. Printed InUSA. Titleregistered in US. Fuel“ 0tfige.(‘apyrl M.
`1994 byPenton Pub hin Inc.Allrl ht: reserved.
`he contents of this publication may notbc reproduced ln whole orin art w:
`_
`_
`outthe consentof the oopyrig n owner.
`subscriber
`chan
`ofaddress and subscription inqouirm, call (216) 8967000. Mm your subscription requests In: Panton Publishing Subscription
`figs»; PO. Box96782,Chicago, 1L6 693.
`MASTER: Pleasesend changeofaddrcss tokmlcuimcw. PeMonPublishing Inc.. 1100SuperiorAve, Cleveland,OH 44114-2543.
`,
`ELECTRONIC DESlGN
`AUGUSI'22,1994
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`COVER FEATURE
`
`VERTICAL INTEGRATION OF SILICON
`. ALLOWS PACKAGING OF EXTREMELY DENSE
`SYSTEM MEMORY IN TINY VOLUMES.
`
`MEMORY-CHIP STACKS
`SEND DENSITY SKYWARD
`
`DAVID MALINIAK
`
`
`
`any aspects of board de-
`sign, such as timing, ther-
`mal issues, and manufac-
`turability, require innova-
`tive thinking. But
`if
`there’s one aspect of board
`design that’s relatively predictable, it's the
`layout, which is done in the X and Y dimen-
`sions. Chips are, almost without exception,
`placed side by side in some arrangement,
`even if the board is doublesided or flexible.
`This constant of board design, however, is
`the great limiter of a board’s packaging den-
`sity. And nowhere is this limitation more glar-
`ing than in the layout of system memory,
`where row upon row of DRAMs sprawl
`across vast expanses of pc board like some
`silicon suburban development
`But the push is on to shrink systems, and
`the traditional layout concepts are becoming
`an extravagance. Over the years, there have
`been a number of attempts at exploiting the
`third dimension in board layout. Chips have
`been stood on their edges and sandwiched to-
`gether and there have been attempts atstack-
`ing them vertically. But until now, such
`schemes have been either too expensive or
`the yields have been poor. In some cases, the
`density achieved wasn’t worth the effort.
`With the development of its technology for
`vertical integration of memory wafers, wafer
`segments, and individual die, Cubic Memory
`Inc. (CMI), Scotts Valley, Calif., has shat-
`tered the density barrier (Fig. 1). Instead of
`the 40-to'80-Mbyte/in.’ storage densities pos-
`sible with conventional packaging—using 16-
`Mbit memories in small-outline J-lead pack-
`ages ($0.13) or two-sided thin small-outline
`packages (TSOPs)—CMI claims the ability to
`achieve densities of a gigabyte or more per
`cubic inch.
`
`Stacking memory 105 vertically has other
`benefits besides the density gains. The close
`physical proximity of the chips significantly
`reduces the system delay associated with in-
`terconnect capacitance and pc-board trace
`length. Speed is increased while power re-
`quirements and operating temperatures are
`reduced compared with horizontal layouts.
`CMI has leveraged its chip-stacking tech-
`nology into an initial pair of product families.
`ELECTRONIC DESIGNm
`AUGUST 22, 1994
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`SAMSUNG EXHIBIT 1058
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`
`MEMORY-CHIP STACKS
`
`the
`takes advantage of
`One
`PCMCIA-card format for adding
`workstation-quantity memory to
`Pentium-based portables,
`=
`i
`.
`while the other works with-
`in the DRAM SIMM format.
`Both merely hintat the tech-
`nology’s potential, which is
`not necessarily limited to
`stacking of memory alone.
`There are actually three
`separate technologies for
`vertical integration, each of a
`which is suitable for differ-
`ent applications. The three
`processes are referred to as
`the large-hole process, the
`small-hole process, and the
`Vertical Interconnect Pro-
`cess (VIP). Common to each
`process is a vertical silicon
`interconnect and a patented
`compliant
`interconnect
`scheme.
`The first two processes,
`known as the large- and
`small-hole processes, use a
`patented, pyramid-shaped
`via through the silicon (Fig.
`2). The small opening on the
`top of the pyramid pene
`trntcs on the circuit side and
`the large opening comes
`through the back side of the
`silicon, where the intercon-
`nect makes contact with a
`number of circuit elements
`on the silicon immediately
`below. This interconnect
`method takes up no space,
`as all pins [an out under the
`silicon stack instead of tak-
`ing up large areas around
`the perimeter of the active
`silicon, as is done with con-
`ventional packaging. In ad-
`dition,
`this method allows
`the individual circuit ele-
`ments to be easily isolated
`for testing up until the final
`stack assembly.
`The VIP process is a less
`expensive extension of the
`small-hole process and does
`not require the pyramid-
`shaped via through the sili-
`con. Instead. gold intercon»
`nect traces and vertical-in-
`terconnect pads are deposit-
`ed over insulating layers of
`polyimide. The gold traces
`
`
`non-oxidizing metal surface for the
`layer-to-layer interconnections.
`e wafers, segments of wa-
`fers, or individual die can be
`i
`-'_' stacked. In addition, multi-
`5' pie silicon technologies can
`. be mixed in the same stack
`'
`(Fig. 3). Other components
`.3 can be placed on top of the
`. silicon stack as well.
`For the small-hole and
`VIP processes, standard
`wafers can be used without
`11 need for any custom silicon.
`Individual chips can be se-
`lected by the control circuit-
`ry. The vertical chip-to-chip
`distance is variable from
`0.003 to 0.010 in., depending
`. on the application and densi-
`'
`ty required.
`The vertically integrated
`’; stacks are attached directly
`to pc boards. Tests on whole
`" wafers and wafer segments
`.: have shown a 15% reduction
`in power consumption and a
`20°C lower continuous oper-
`ating temperature when
`compared to identical cir-
`cuits operating in conven-
`tional plastic packages.
`Originally, the large-hole
`process was developed to al-
`low stacking of complete 6-
`in. DRAM Wafers. The pyra-
`mid-shaped holes are filled
`with a mesh of fine gold-
`plated wire. The wires form
`a mushroom shape on the
`circuit side of the wafer, and
`the other ends of the wire
`are compressed and con-
`tained in the pyramid base.
`When the wire-filled base of
`the pyramid of one wafer is
`brought into contact with
`the top of another wafer, the
`mushroom-shaped “fuzz
`button” is captured by the
`base of the pyramid. All of
`the wires are then contained
`and a compressive gold-to-
`gold contact is formed be-
`tween the circuit elements
`of both wafers. The result is
`a very reliable, fully compli—
`ant, reworkable intercon-
`nect that supports intercon-
`nections in both the horizon-
`tal and vertical directions.
`
`INSTEAD OF THE 4M0-80Mhyte/in.’ storage densities
`possible with conventional packaging (using iiiMhit memories in
`80.15 or two-sided TSOPs), Cubic Memory Inc. (CM!) claims the
`ability to achieve densities of a gigabyte or more per cubic inch.
`
`
`
`2. BOTH THE small- and lugehole processes use a pyramid-
`shspcd via through the silicon to make the vertical
`interconnections. The small opening on the top of the pyramid
`penetrates on the circuit side and the large opening comes through
`the back side of the silicon, where the interconnect makes contact
`with a number of circuit elements on the silicon immediately below.
`DESIGN
`me1.sch0Nic
`AUGUST 22, 1994
`
`SAMSUNG EXHIBIT 1058
`Page 4 of 7
`
`interconnection
`provide horizontal
`of the die on a single layer or seg-
`ment, and the gold pads provide a
`
` Whol
`
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`M‘-_..._._.
`
`-__.——~——
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`m
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`MEMORY-CHIP STACKS
`
`The “fuzz-button” inter-
`connect does, however, re-
`quire a custom mask set.
`And the holes are large by
`semiconductor standards:
`150 pm at the top and 1000
`pm at the base. This inter-
`connect technology is still
`used in some applications.
`The small-hole process
`was developed as a refines
`ment of the large-hole,
`“fuzz-buttOn” technology to
`allow interconnects on stan-
`dard
`semiconductor-die
`bonding pads without the
`need for a specialized struc-
`tu re. In this method, off-the
`shelf memory wafers can be
`used without the need for the semi-
`conductor manufacturer to run a
`
`
`on bottom) so that the verti-
`cal
`interconnect is accom-
`plished within a bond-pad
`area and on conventional
`bond-pad pitches.
`'I‘he small-hole process in-
`corporates one level of dis-
`cretionary wiring for every
`layer of silicon in the stack.
`Each die also has the neces-
`sary
`control
`signals
`brought out so that the con-
`trol circuitry can address
`each chip uniquely.
`Silver-filled epoxies are
`used for the compliant con-
`ductive material. These
`proven materials are the
`same ones that have been
`used for years by semiconductor
`manufacturers as a. die-attach medi-
`um. CMI has developed a proprietary
`application method for the dispens-
`
`
`
`3. WHOLE WAFERS, segments of waters, or individual
`die can be sucked. In addition, multiple silicon technologies can be
`mixed in the some stock. Other components can he placed on top of
`the silicon stock as well.
`
`
`
`2i
`
`.‘._V.'_-_:__-;_‘_-
`
`custom mask set. In this case, the hole-making pro-
`
`cess is similar to the fuzz-button pro-
`cess, but the dimensions change. The
`wafers are thinned and the holes are
`small enough (25 pm on top, 120 pm
`
`
`:Puumc MEMORY smcus'm wunu -
`
`
`
`anufacturers of lap-
`top/notebook comput-
`ers are forever facing
`the
`challenge
`of
`squeezing desktop performance
`into an easy-to—transport pack-
`age. In the RISC-workstation are
`na, the problem intensifies,
`be—
`cause many of the Unix-based ap-
`plications demand tremendous
`amounts of memory to execute
`quickly.
`Just such a problem was faced
`by designers of the SPARCbook
`III at Tadpole Technology pic,
`Cambridge, U.K.,
`explains
`George Grey. the group chief/ ex-
`ecutive officer. The need for an al-
`ternative to the standard DRAM
`
`Mbytes per SIMM by late 1994,
`and still keep the SIMM height to
`just I in.
`One of the first steps designers
`had to take to enhance the SIMMs
`was to expand the address range.
`They added one more address line
`and two additional row-address-
`strobe (RAS) lines by using sever-
`al pins that were previously no-
`connect pins on the SIMM. Some
`provides the four parity bits for
`of the key issues that designers
`each word.
`had to deal with, explains Dave
`After the stacks are assembled,
`Pedersen, VP. of engineering at
`they are mounted in the SIMM
`CMI, included the banking archi-
`substrate. The substrate actually
`tecture and capacitive loading ef-
`has a. hole the size of a stack cut
`fects in highly-configured sys-
`into it and the stack is then insert
`tems. Fortunately, because the
`ed into the substrate. The stack
`memory chips are mounted on top
`protrudes out of one side of the
`of each other, there are no pack-
`single~in-line memory module
`substrate by the amount of the
`age loading effects. Also, typical—
`(SIMM), which peaks in capacity
`difference in their thicknesses. In
`ly, only one bank of memory is
`at 32 Mby tes, led Tadpole to team
`the case of the 128-Mbyte stacks,
`turned on at a time. which mini-
`with Cubic Memory Inc. (GM!) to
`which stand 0.160 in. tall, they pro-
`mizes thermal problems.
`develop higher-density SIMMs.
`trude 0.098 in. from the 0.062-in.-
`Once the interface was defined,
`By taking advantage of CMI’s
`thick substrate. That’s less than
`vertical
`interconnect process
`the memory structure was imple-
`the height of a thin small-outline
`mented using “stacks” of memo-
`(VIP), designers at Tadpole and
`package. When coated with the
`CMI defined an extension to the
`ry layers. The memory stacks con-
`sealing epoxy, the mechanical du-
`standard DRAM SIMM that will
`sist of eight-segment layers (each
`rability of the SIMMs is as good as
`segment can be thought of as a 2-
`initially provide 64 Mbytes of stor-
`Mword bank of-DRAM). The VIP
`previous-generation SIMMs that
`age (organized as 16 Mwords by
`were populated with surface-
`scheme employs pyramid-shaped
`36 bits, which includes byte-parity
`mounted components.
`recesses on the outer edge of the
`hits). Furthermore, CMI expects
`3 Y DA VE B URSKY
`
`
`chips. Then, when the chips are.
`to double the capacity to 128
`
`DE
`SIGN
`[He L r c T R o N l c
`AUGUS’1‘22, 1994
`
`
`
`stacked, the contact edges are ex-
`posed so that conductive epoxy
`easily fills the recesses and real-
`izes the connections.
`Each segment layer in the mem-
`ory stack consists of a monolithic
`piece of silicon that contains four
`2-Mword—by-8-bit DRAMs, thus
`forming a 32—bit-wide memory
`block. Complementing the 32-bit
`wide stack is a second stack that
`
`SAMSUNG EXHIBIT 1058
`Page 5 of 7
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`,0"
`
`MEMORY~CHIP STAGKS
`
`my, _‘._“‘
`
`
`
`
`ing and application of these epoxies
`ductivity to enhance dissipation of
`for connection in both the horizontal
`heat from the stack.
`and vertical dimensions.
`To leverage its chip—stacking tech-
`Taking the process a step further,
`nology into products that are usable
`the VIP process makes
`high-volume automation a
`part of the manufacturing
`cycle. It’s also the lowest-
`cost method, because it uses
`a subset of the steps used in
`the small-hole process and
`does not require the pyra-
`mid-shaped hole through
`the silicon. The VIP process
`is suitable for stacking die
`and wafer segments that do
`not have a large number of
`interconnects to outside log-
`ic. It is not suitable, howev-
`er, for stacking whole wa-
`fers.
`
`Silver-filled epoxy
`
`Edd lure
`Md
`
`Carling min
`
`EMF mde sammlr
`
`Silicon base plalo
`
`PCB allacii
`
`Pt huanl
`
`today, CMI is offering two forms of
`memory modules for expansion of
`portable—system memory. One is the
`3DMemory family of 88-pin JEDEC
`memory modules in capaci-
`ties of 16, 32, 64, and 128
`Mbytes. These are targeted
`for use in portables with a
`Type I PCMCIA slot, and
`are especially meant for
`Pentium-based portables
`that are expected to be able
`to address 64 Mbytes of sys-
`tem memory or more by this
`fall’s Comdex show.
`In this implementation of
`the technology, a glimmer
`of its potential impact comes
`into focus. For manufactur-
`ers using conventional tech-
`nologies, volumetric space
`requirements limit portable
`add-in memory cards to one
`double-sided pc board using
`'l‘SOP packages. Typically,
`only 16 to 18 10s will fit into
`the available space, so to re-
`alize the maximum 16
`Mbytes of storage, the man-
`ufacturer must use costly
`16-Mbit DRAMs. Here’s
`where the vertical-integra-
`tion technology comes in.
`With it, memory cards are
`built. using the most cost-ef-
`fective DRAMs available.
`The 16-Mbyte card contains
`two stacks of four layers
`each. Each Z-Mbyte layer is
`made up of four 4-M’bit
`DRAM die. The 32-Mbyte
`, card increases the two
`.‘ stacks to eight layers each.
`1 This produces a 16-Mbit
`module with a 32-bit word.
`
`In the VIP process, gold
`traces and vertical-intercon—
`nect pads are deposited over
`insulating layers of polyi-
`mide. Then, the wafers are
`thinned and sawed into seg-
`ments. The segmentn’ edges
`are beveled to allow vertical
`
`interconnection (Fig. 4). The .
`gold traces provide horizon-
`tal interconnection of the die
`on a single layer or segment
`and provide layer- or seg—
`ment-specific memory-ad-
`dress decoding capability.
`Pins that are parallelable .
`are connected that way,
`which results in a reduction
`
`2
`
`l
`
`VIPP gold traces and bonding pads
`4.
`are deposited over insulating layers of polyimide. Then, the waters
`are thinned and their edges beveled to allow veriicol
`interconnection. The gold traces provide horlwntal
`interconnection of die on a single layer or segment and provide
`layer- or oegmentspccific memory-address decode capability.
`
`
`
`‘
`
`'
`
`.'
`
`of pin count per layer of
`about 4:1. If the resulting
`stack has ten layers,
`the
`overall reduction in pin .
`count is about 40:1. The gold 3
`bonding pads are exposed at i
`the sides of the segments ':
`thanks to the 45° bevel cut
`and are used for the layer-
`to-layer connections.
`A conductive silver-filled ‘
`epoxy is used for both physi- '
`cal and electrical connection
`of the layers. The same con-
`ductive epOxy is used to con-
`nect
`the stack to the pc
`board. The stack is then env
`‘ 5. IN BOTH THE 88-pin annc module and the SiMMo. tho
`:
`capsulated with a casting .
`‘ memory stocks are not mounted in the card's internal pe bond as
`l
`1 mil. Rather, they are "floated" indde holes that go through the
`'
`p
`l
`resin to provide protection I
`‘; board and attached “their-periphery by means ollnoom-stylelmln
`and mechanical durability.
`j_‘
`" ; consloilng of conductivequyJ‘hey arethen gloHop-
`The resin also provides
`some degree of thermal c0n~ “31 v encapsulated on the reverse ride In provide stability.
`MELECTRONIC nesrcn
`AUGUST 22. 1994
`
`V
`"
`
`
`
`Up to 128 Mbytes is easily
`accommodated within the
`PCMCIA Type I form fac-
`tor.
`
`For memory-card manu-
`facturers using convention-
`al packaging technologies,
`the volumetric'space re-
`quirements limit the cards
`to one double-sided pc board
`using TSOPs. Only 16 to 18
`memory chips fit into the
`available space, so to realize
`the maximum 16 Mbytes of
`storage, the manufacturer
`must use costly 16-Mbit
`
`\
`
`SAMSUNG EXHIBIT 1058
`Page 6 of 7
`
`
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`Page 6 of 7
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`SAMSUNG EXHIBIT 1058
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`

`

`MEMORY-CHIP STACKS
`
`
`
`DRAMs. In contrast, CMI’s vertical
`integration technique offers its in-
`herent density advantages and en-
`ables cards with capacities of 16
`Mbytes and more to be built using 4-
`or 16-Mbit DRAMs.
`An interesting note on the con-
`struction of the cards is that the
`memory stacks are not mounted to
`the card’s internal pc board as such.
`Rather,
`they are "floated" inside
`holes that go through the board and
`attached at their periphery by means
`of beam-style leads consisting of
`conductive epoxy. (Fig. 5).
`For adding system memory to
`workstations and servers, CMI is of-
`fering a line of 3DMemory 64- and
`128-Mbyte DRAM SIMMs. Previous-
`ly, the maximum density of standard
`, 72-pin SIMMs has been 32 Mbytes
`(see ‘Tutting memory stacks to
`work, "p. 57).
`The 64-Mbyte SIMMs are made
`from eight layers of 8-Mbyte wafer
`segments (each made from four 16-
`Mbit DRAM die) plus a four-layer
`stack of 16-Mbit die for parity. The
`128-Mbyte SIMMs will use 16 8-
`MByte layers, plus an eight-layer
`stack of 16-Mbit die for parity. The
`memory organization is 16 Mbytes
`by 36 bits for the 64-Mbyte SIMM
`and 32 Mbytes by 36 bits for the 128—
`Mbyte version. D
`~
`
`PRICE AND AVAILABILITY
`The 3DMemory 88-pin JEDEC memory
`modules will be sold to OEMs as well as
`through. the reseller channel to end users.
`The 16m”:er modules are scheduled to
`ship in September, and at loday‘smemmy
`pficus will have a suggested price of$995.
`The 32-. 64-, and 198-
`yle version: will be
`available during the fourth quarter and
`pricing is projected at 51.9.95, 53.995, and
`$7.995 each, respectively.
`The 3DMemorg 73-pin. SlMMs will ini-
`tially be cold only to OEMo. At today’s
`memory prices, the 64-Mbyte SIMM» will
`cost $8.999 in sample lots and $359.9 in
`quantities of 1000. The I38-Mbylc SIMM:
`will scllfor W999 (sum (as) and $71.99 (pro
`duction modalities).
`ample» are avail-
`oble wow and production quantities will
`be available during lhefbmth quarter.
`CubicMenwry Ina, Zflenis Way. Scales
`Valley, CA 95066; (408) 438-1887;]ax (409)
`438-1890.
`CIRCLE 512
`
`our
`eedy IMOS
`logic Is Bi News.
`But We’re
`oping
`ll Ollie
`
`It’s hard to keep the noise down on a
`development this big.
`But that’s exactly what we’ve done.
`Our new VHS (VHC comparable) series of
`LMOS logic not only offers high speed switching,
`but super-low noise besides.
`AC speed at HC levels, you might say.
`What’s more, its single-gate format makes for
`more board space. Along with increased design
`flexibility.
`So call us at 1-800—879-4963 to get in on
`a timely idea.
`Lightning-fast LMOS.
`Without the thunder.
`
`SPDQS-057A
`
`In Touch with Tomorrow
`TOSHIBA
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`@1993 Toshiba Amerlca Electronic Componenls. Inc
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`1)
`ELECTRONIC
`AUGUST 22. 1994
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`E s
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`I c NIB
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`SAMSUNG EXHIBIT 1058
`Page 7 of 7
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`Page 7 of 7
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`SAMSUNG EXHIBIT 1058
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