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`WARPAGE AND MECHANICAL STRENGTH STUDIES OF ULTRA THIN
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`150MM WAFERS.
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`Malcolm K. Grief, James A. Steele Jr.,
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`MOTOROLA 1N0,
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`COM 1, RF Semiconductor Division,
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`Phoenix, Arizona 85008.
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`surface. This presents a severe Challenge for
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`process and test equipment initially designed to
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`handle flat,
`full
`thickness wafers
`that must
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`perform processing steps on these
`ultra—thin
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`substrates [2].
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`and
`While experience exists
`in handling
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`processing
`silicon
`and
`compound
`thin
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`semiconductor wafer diameters of 100mm and
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`less [3] there is very little experience at handling
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`150mm wafers where wafer bow is much more
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`severe than for a smaller diameter wafer of
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`equivalent thickness.
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`strength is
`silicon wafer
`Maximizing the
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`important as it improves the ability of the thin
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`wafer to survive the mechanical and thermal stress
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`is
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`subjected to by handling and further
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`processing. Grind processes will induce damage
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`in the wafer backsurface that can lead to crack
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`propagation, growth and fracture. Grind only
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`processes can be optimized for increased strength
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`[4] however a silicon wet etch process is often
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`necessary to completely remove the damaged layer
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`and maximize die strength.
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`Figure 1. gives a general description of the
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`process steps required between thinning and final
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`testing on the wafer back surface for a typical high
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`power RF device.
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`1996 IEEE/CPMT Ini‘i Electronics Manufacturing Technology Symposium
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`Figure 1 .
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`Wafers with tape applied to their front surface
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`them from mechanical and chemical
`to protect
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`damage are thinned in the wafer thin operations.
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`The backgrind process utilizes a coarse grind
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`wheel for bulk material removal. This is followed
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`by a fine finishing wheel to reduce the depth of
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`damage induced by the coarse grind. A silicon wet
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`etch removes damaged silicon in a hydrofluoric/
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`0-7803—3642—9/96 $4.00 @1996 iEEE
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`AMSUNG EXHIBIT 1052
`l of 5
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`Backgrind
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`Silicon wet etch
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`Back metallization
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`l
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`Wafer anneal
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`Demand for die produced on ultra thin silicon
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`substrates requires improvement in wafer thinning
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`capability, manufacturing equipment
`substrate
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`handling and packing methodologies. Existing
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`methods typically consider substrates that are
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`nominally flat and relatively thick (254nm to
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`613nm). The challenge COM 1 faces on several
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`of its product lines, is that they require that the
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`150mm diameter substrate be thinned to below
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`150nm. Wafers at this thickness will tend to bow
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`and warp with unpredictable orientation. This is
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`due to the interaction between stresses from the
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`various frontside and backside dielectric and
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`conductive layers together with those induced by
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`the backside grinding and chemical thinning and
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`the reduced ability of the thin silicon substrate to
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`resist these forces. Existing schemes used for
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`smaller wafer diameters (< 100mm) have proven
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`incapable of successfully thinning, handling and
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`transferring these larger substrates to the assembly
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`resulting in high levels of wafer breakage.
`sites,
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`To enhance
`survivability during
`subsequent
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`handling and shipment of ultra-thin
`150mm
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`wafers,
`the understanding of warpage and die
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`strength becomes critical, which is the focus of
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`this paper.
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`1. Introduction
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`Semiconductor wafers are routinely thinned
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`prior to dicing to aid the sawing operation and to
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`allow the final assembled package thickness to be
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`minimized. For semiconductor devices required to
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`operate at high power
`levels, wafer
`thinning
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`improves the ability to dissipate heat by lowering
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`the die’s thermal resistance. The performance of
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`high power RF semiconductor devices can be
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`severely limited by poor thermal dissipation which
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`in turn has driven a demand for wafers thinner
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`than lSOttm [1].
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`final
`As
`thickness is decreased the wafer
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`progressively becomes less able to support
`its
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`own weight and to resist the stresses generated by
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`the process layers on the wafer frontside. The
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`result is a wafer that is no longer flat and tends to
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`bow and warp in a manner that can vary with the
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`means by which it is supported. A thin wafer
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`supported along its edges in a wafer cassette will
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`have a different form to that of one lying on a flat
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`Abstract
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`SAMSUNG EXHIBIT 1052
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`95% confidence the sample groups cannot be
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`considered different from each other [6].
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`Sample ID
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`Die strength variation with wafer »
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`thinning process.
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`Diestrength(normalised)
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`Figure 3.
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`Diestrength(normalised)
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`Figure 4.
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`Sample ID
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`Die strength variation with process
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`flow
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`Fig. 3 shows that coarse grinding of wafers
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`lead to low die strengths. Fine grinding yielded
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`better results however the highest die strengths for
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`both fine and coarse surfaces could only be
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`achieved with the inclusion of a wet etch. For
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`fine ground surfaces the 3 min. wet etch did not
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`yield an significant improvement over a 1 min.
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`etch.
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`Fig. 4. shows that
`the wafer receiving fine
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`grind only had the lowest overall die strength
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`while the three other wafers all hadphigher but
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`similar
`levels. The addition of
`the wet etch
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`increases the strength by removing the grind
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`nitric acid based mixture followed by stain
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`removal etches.
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`After the protective tape is removed the wafer
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`back surface is metallized by coating it with a
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`layer of sputtered gold. A thermal anneal is then
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`required
`to form a gold—silicon eutectic layer
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`completing the backside processing.
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`This paper describes efforts to characterize
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`both the strength and deformation of 150mm
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`substrates as a function of the wafer thin process
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`and subsequent processing. This is driven by the
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`need to make such processing manufacturable and
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`to understand how to further decrease the device
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`thickness to improve performance.
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`2. Die strength
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`2.1 Experimental and results
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`A series of 150mm silicon wafers were
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`prepared with differing grind, wet etch and
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`backmetal processing. All wafers had the same
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`final
`thickness. Die
`strengths were
`nominal
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`measured by sawing these wafers into standard
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`100x100 mil die. The top surface of the individual
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`die were then subjected to a compressive loading,
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`the die strength being the force at which the
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`sample fractured[5].
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`Wafers described in Figure 2. were prepared in
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`order to investigate the effects of grind finish, wet
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`etch time and back metallization on die strength.
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`1996 lEEE/CPMT Int'l Electronics Manufacturing Technology Symposium
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`Process
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`Coarse grind only
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`Coarse grind + 3 min. wet etch
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`Fine grind only
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`Fine grind + 1 min. wet etch
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`Fine grind +3 min. wet etch
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`Fine grind only
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`Fine grind + 3 min. wet etch
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`Fine grind + 3 min. wet etch +
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`Gold dep. + anneal
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`Fine rind + Gold de . + anneal
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`Backside processing description
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`EQ’TJmU0w>
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`l—d
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`Figure 2.
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`2.2 Discussion
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`Die strength for each wafer thin process are
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`shown in figs 3 and 4. The data is represented by
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`individual data points plus
`“means
`the
`the
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`diamond” which schematically represents
`the
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`mean (horizontal line) and standard error (upper
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`and lower apex of the diamond) of the sample.
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`Overlapping mean diamonds indicate that
`to a
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`4. Wafer bow
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`4.1 Experiments and results
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`Wafer bow was measured using two methods;
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`the first utilized the ability of a cassette to cassette
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`wafer
`transfer
`tool
`to measure the
`effective
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`thickness (t) of a bowed wafer by sensing the
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`highest and lowest points of its top and bottom
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`surfaces
`respectively (fig. 6). An alternative
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`technique used a non contact wafer thickness
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`measurement tool which places the bowed wafers
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`over an array of capacitive transducers. Each
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`sensor determines the distance from its surface to
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`the lower surface of the wafer (d) and uses the
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`data to map bow across the wafer (fig. 7).
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`Measurements made by the first method tended
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`to give higher bow as the wafer, supported by its
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`edges was subject
`to the additional deforming
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`effect of gravity. The second method provided
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`more support for the wafer with gravity tending to
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`flatten out the bow. Both methods gaVe useful
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`information pertinent
`to the manner
`in which
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`wafers were handled in process.
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`1996 IEEE/CPMT Int‘l Electronics Manufacturing Technology Symposium
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`induced layer of damaged and deformed silicon
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`however a similar effect has been produced by the
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`formation of the backside gold eutectic layer.
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`This suggests that the eutectic reaction between
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`the silicon and the gold backmetal consumes most
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`of the damaged silicon that contributes to the
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`weakening of the wafer.
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`3. Wet etch rate
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`3.1 Experiment and results
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`In order to understand the depth of damage
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`caused by the grind processes, wafers Were
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`ground with both our “coarse” and “smooth”
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`finish processes and wet etched for varying times.
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`The frontsides of the wafers were protected from
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`the etch by a silicon nitride film.
`20.0
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`Etchremoval(um)
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`1
`Coarse grind
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`17.5
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`15.0
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`12.5
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`10.0
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`7.5
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`5.0
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`0.0
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`Etch time (min)
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`2.5
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`3.0
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`3.5
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`Figure 5.
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`Silicon wet etch removal vs. etch
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`time
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`3.2 Discussion
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`The s10pe of the fitted lines in fig. 5 show that
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`between 0.5 and 3 min. both “coarse” and “fine”
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`samples had similar etch rates. During the initial
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`30 seconds of the etch however there has been an
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`accelerated removal rate. The thickness of silicon
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`removed during this phase is a measure of the
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`depth of damage being much greater for the coarse
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`ground sample as evidenced by the offset between
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`the two lines. This confirms the data obtained
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`from the die strength testing in that both coarse
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`and fine finishes were significantly strengthened
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`by wet etching but that etch times over 1 min. did
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`not confer additional improvement.
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`Figure 6.
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`Effective thickness measurement, t
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`Figure 7.
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`Capactive measurement of wafer
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`bow
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`SAMSUNG EXHIBIT 1052
`- 3 of 5
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`Waferwarp(um)
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`4.2 Discussion
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`
`
`
`the
`to
`how both
`understand
`In
`order
`
`
`
`
`
`cumulative
`film stress
`by wafer
`generated
`
`
`
`
`
`
`
`processing and the final wafer thickness affect the
`
`
`
`
`
`
`
`
`final wafer bow it is important to consider the
`
`
`
`
`
`theoretical nature of this interaction.
`
`
`
`
`
`
`plate
`Equation 1.
`follows
`from classical
`
`
`
`
`
`
`
`
`
`
`bending theory [7] and while it relies on a number
`
`
`
`
`
`
`
`
`
`
`
`of initial conditions [8] to be met it has been used
`
`
`
`
`
`
`successfully to measure thin film stresses[9].
`
`
`
`
`
`....(1)
`E
`o:
`h2
`
`6Rt(1-v)
`
`
`
`
`where,
`
`
`
`
`
`E/(l-V) = substrate biaxial modulus (Pa)
`
`
`
`
`
`= substrate thickness (m)
`h
`
`
`
`
`
`= film thickness (m)
`t
`
`
`
`
`
`
`
`R
`= radius of curvature of the wafer (m)
`
`
`
`
`G
`: film stress (Pa)
`
`
`
`
`
`
`
`The above equation shows that the cumulative
`
`
`
`
`
`
`
`
`film stress is inversely proportional to the induced
`
`
`
`
`
`
`
`
`radius of curvature of the wafer or directly
`
`
`
`
`
`
`
`
`
`proportional to the wafer bow as bow and radius
`
`
`
`
`
`
`
`
`of curvature are related geometrically to the wafer
`
`
`
`
`
`
`
`
`
`
`
`bow [8] and that the bow of the wafer is inversely
`
`
`
`
`
`
`
`proportional to the final substrate thickness. While
`
`
`
`
`
`
`
`this equation works best with single unpattemed
`
`
`
`
`
`
`
`
`
`
`films it can be used on product wafers where the
`
`
`
`
`
`
`cumulative
`effects
`of
`processing
`be
`can
`
`
`
`
`
`
`
`
`considered to have a single thickness T, and
`
`
`
`cumulative film stress, GT.
`
`
`
`
`
`
`
`It follows that Equation 1. can be simplified
`
`
`to show;
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Wafer bow 0: 1/ h2
`
`
`
`
`....(2)
`
`
`
`Wafer bow 0c GT
`....(3)
`
`
`
`
`
`
`
`
`
`
`Fig.
`9 shows how the bow of a fully
`
`
`
`
`
`processed RF bipolar wafers measured after grind
`
`
`
`
`
`
`
`
`
`varied with its final thickness. The data was fitted
`
`
`
`
`
`
`
`
`using equation (2) and highlights how wafer bow
`
`
`
`
`
`
`
`quickly becomes severe as wafer thickness are
`
`
`
`reduced below 150nm.
`
`
`
`
`
`
`
`
`The two unfitted data points represent the bow
`
`
`
`
`
`
`
`of thinned wafers measured after gold deposition.
`
`
`
`
`
`
`
`
`Both show how the additional
`film stress has
`
`
`
`
`
`substantially increased
`bow. Additional
`the
`
`
`
`
`
`
`
`measurements on gold coated wafers thinned to
`
`
`
`
`
`
`
`
`
`150nm and below were not made as the bow
`
`
`
`
`
`
`
`
`exceeded the cassette pitch size causing the wafers
`
`
`
`
`
`to wedge in the slot.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Post gold
`deposition
`
`/
`Post wafer
`thin
`
`
`
`200
`150 ‘
`wafer thickness (um)
`
`
`
`
`
`
`
`
`
`
`
`
`
`Figure 9.
`
`
`
`1996 IEEE/CPMT lnt’l Electronics Manufacturing Technology Symposium
`
`
`
`
`
`Wafer bow (effective thickness) as
`
`
`
`
`
`a function of wafer thickness.
`
`
`
`5. Manufacturability considerations
`
`
`
`
`
`
`
`Ultra thin wafers (<150um) exhibiting bow of
`
`
`
`
`
`3000+um have presented considerable challenges
`
`
`
`
`
`
`
`to our wafer processing and handling equipment.
`
`
`
`
`
`
`
`The extra effective volume that
`these wafers
`
`
`
`
`
`
`
`
`occupy mean that standard 25 slot wafer cassettes
`
`
`
`
`
`
`
`
`
`had to be replaced with larger pitch designs that
`
`
`
`
`
`
`
`allow more access between wafers. Materials have
`
`
`
`
`
`
`
`
`
`also been chosen that resist the tendency of their
`
`
`
`
`
`
`
`razor sharp edges produced by the thinning
`
`
`
`
`
`
`
`
`process to cut and wedge into the cassette.
`
`
`
`
`
`
`
`
`
`In almost all cases it was necessary to modify
`
`
`
`
`
`
`process equipment to successfully transfer thin
`
`
`
`
`
`
`wafers. Handling systems without
`vacuum to
`
`
`
`
`
`
`
`
`
`hold the wafer had their ‘end effector’ or wafer
`
`
`
`
`
`
`holder
`re-designed to offer more
`backside
`
`
`
`
`
`
`
`support, minimizing the addition effect gravity can
`
`
`
`
`
`
`
`
`
`
`play in increasing bow. The depth of the recess in
`
`
`
`
`
`
`
`
`
`the end effector was also increased to hold the
`
`
`
`
`
`
`
`wafer more securely.
`In some cases differing
`
`
`
`
`
`
`handler calibrations were necessary from those
`
`
`
`
`
`used on standard thickness wafers.
`
`
`
`
`
`
`Systems utilizing vacuum handling did allow
`
`
`
`
`
`
`
`
`
`the wafer to be flattened against the end effector
`
`
`
`
`
`
`thereby reducing its bow. Standard vacuum
`
`
`
`
`
`
`
`settings however were often insufficient to pull
`
`
`
`
`
`
`
`
`
`the wafer down and form a good seal against the
`
`
`
`
`
`
`
`end effector while higher
`levels of vacuum
`
`
`
`
`
`
`
`
`however were shown to locally deform the wafer
`
`
`
`
`
`
`
`around the vacuum orifices inducing damage of
`
`
`
`
`
`
`
`
`even fracture of the wafer. Even with optimal
`
`
`
`
`
`
`
`
`vacuum settings there was a finite number of
`
`
`
`Page 4 of 5
`
`SAMSUNG EXHIBIT 1052
`
`

`

`
`
`
`
`References
`
`
`
`
`
`
`
`times that a wafer could withstand repeated
`
`
`
`vacuum handling operations.
`
`
`
`
`
`Finally, package and shipping methodologies
`
`
`
`
`
`
`
`
`
`had to be totally redesigned to assure survival of
`
`
`
`
`
`
`
`
`
`
`the wafers sent to our customer base all over the
`
`world.
`
`
`6. Conclusion
`
`
`
`
`
`
`
`
`Ultra thin wafers (less than 150nm) are critical
`
`
`
`
`
`
`in meeting package
`thickness
`and
`thermal
`
`
`
`
`
`
`dissipation requirements
`for high power RF
`
`
`
`
`
`
`semiconductor devices. Ultra thin wafers pose
`
`
`
`
`
`
`new challenges for manufacturing. Die strength,
`
`
`
`
`
`
`
`which is critical
`for survivability, becomes a
`
`
`
`
`
`
`
`major concern. The damage induced into the
`
`
`
`
`
`
`
`silicon by backgrind must be
`removed to
`
`
`
`
`
`
`
`maximize the die strength. Wet etching through
`
`
`
`
`
`
`
`
`
`the depth of damage is an effective way for
`
`
`
`
`
`
`damage removal, whether the backgrind operation
`
`
`
`
`
`
`
`
`uses a course grind only or whether a coarse/fine
`
`
`
`
`
`
`
`
`grind combination was used. Once the depth of
`
`
`
`
`
`
`
`damage was removed, additional etch time does
`
`
`
`
`
`
`
`
`
`not result in a significant increase in die strength.
`
`
`
`
`
`
`The
`eutectic
`during
`reaction
`formed
`gold
`
`
`
`
`
`
`
`
`deposition and anneal is also an effective method
`
`
`
`
`
`for increasing the die strength.
`
`
`
`
`
`
`
`
`Though the wafer bow and direction can vary
`
`
`
`
`
`
`
`
`greatly in ultra thin wafers,
`the results indicate,
`
`
`
`
`
`
`
`
`for at least unpatterned wafers, that they follow
`
`
`
`
`
`
`
`
`
`classical plate bending theory in which the bow is
`
`
`
`
`
`
`
`
`inversely proportional to the square of the wafer
`
`
`
`
`
`
`and
`thickness
`directly
`proportional
`to
`the
`
`
`
`
`
`
`
`
`cumulative fllmlstress. With bows in excess of
`
`
`
`
`
`
`
`3000ttm for
`these ultra thin lSOum diameter
`
`
`
`
`
`
`wafers, puts considerable challenges to wafer
`
`
`
`
`
`processing and handling
`equipment.
`The
`
`
`
`
`
`
`
`challenges occur in many areas including cassette
`
`
`
`
`design/material selection, wafer support/vacuum
`
`
`
`
`
`
`handling, and pack/ship methodologies.
`It
`is
`
`
`
`
`
`
`
`obvious that producing ultra thin 150mm diameter
`
`
`
`
`
`
`poses some interesting and unusual challenges.
`
`1996 IEEE/CPMT lnt'l Electronics Manufacturing Technology Symposium
`
`[1]
`
`[2]
`
`[3]
`
`
`
`7. Acknowledgments
`
`
`
`
`
`
`
`The
`to thank David
`authors would like
`
`
`
`
`
`
`
`Holcombe, Dodge Jaillet and Marge Turner for
`
`
`
`
`
`
`
`their support in performing die strength testing
`
`
`
`
`
`
`
`
`and to" Tom Shaughnessy and Richard Earle for
`
`
`
`
`
`their Management support and encouragement.
`
`
`
`
`
`Norm Dye and Helge Granberg, “Radio
`
`
`
`Frequency Transistors”, Butterworth-
`
`
`Heinemann, 1993.
`
`
`
`
`S.LLugosi, R.W.Earle, “Handler
`
`
`
`
`Modifications for Ultra thin Wafers”,
`
`
`
`
`SEMICON West, July 1996.
`
`
`
`
`
`N.Goto et al.,”Mechanical Thinning of
`
`
`
`
`Compound Semiconductor Wafers by
`
`
`
`Grinding”, Sumitomo Electric Review,
`
`
`
`#33, January 1992.
`
`
`
`
`S.Lewis, “Backgrinding Wafers for
`
`
`
`Maximum Die Strength”, Semiconductor
`
`
`
`International, July 1992.
`
`
`
`
`
`B.Hudson, D.Perrin, “The effects of
`
`
`
`
`
`wafer processing on silicon die strength”,
`
`
`
`
`ISTFA 1990. International Symposium
`
`
`
`
`
`
`for Testing and Failure Analysis, 1990.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`JMP®, Copyright© SAS Institute.
`
`
`G.GStoney, Proc.R.Soc.London
`
`
`
`Ser.A82, 172 (1909).
`
`
`
`J.L.Kawski, J.Flood, “Cumulative thin
`
`
`
`
`
`Film Stresses from Wafer Fabrication
`
`
`
`
`
`
`Proceses and its Effects on Post
`
`
`
`
`Backgrind Wafer Shape”, 1993
`
`
`[BEE/SEMI Advanced Semiconductor
`
`
`Manufacturing Conference.
`
`
`
`wafer
`I.Blech,
`“Silicon
`D.Dang,
`
`
`
`deformation
`after backside
`grinding”,
`
`
`
`
`
`Solid State Technology, August 1994.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`AMSUNG EXHIBIT 1052
`5 of 5
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`Page 5 of 5
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`SAMSUNG EXHIBIT 1052
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`