UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTNIENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`PO. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
`
`FILING DATE
`
`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
`
`CONFIRMATION NO.
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`12/497,652
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`30232
`
`07/04/2009
`
`Glenn J. Leedy
`
`0907043 DSASL. US
`
`6944
`
`7590
`
`08/27/2014
`
`USEFUL ARTS IP
`MICHAEL J. URE
`10518 PHIL PLACE
`
`CUPERTINO, CA 95014
`
`EXAMINER
`JOY, IEREMYJ
`
`PAPER NLHVIBER
`
`MAIL DATE
`
`08/27/2014
`
`DELIVERY MODE
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`PAPER
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`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`
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`The time period for reply, if any, is set in the attached communication.
`
`PTOL—90A (Rev‘ 04/07)
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`Application No.
`Applicant(s)
`12/497,652
`LEEDY, GLENN J.
`
`
`
`Office Action Summary
`
`AIA (First Inventor to File)
`Art Unit
`Examiner
`SN?“
`2896
`JEREMY JOY
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`
`
`
`b)I:I Some** c)I:I None of the:
`a)I:I All
`1.I:I Certified copies of the priority documents have been received.
`2.|:I Certified copies of the priority documents have been received in Application No.
`3.|:| Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2( )).
`** See the attached detailed Office action for a list of the certified copies not received.
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING DATE OF
`THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`after SIX (6) MONTHS from the mailing date ofthis communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. §133).
`Any reply received by the Office later than three months after the mailing date of this communication, even iftimely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`In no event, however, may a reply be timely filed
`
`Status
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`1)IZ Responsive to communication(s) filed on 07/22/2014.
`[I A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2b)|:| This action is non-final.
`V This action is FINAL.
`An election was made by the applicant in response to a restriction requirement set forth during the interview on
`; the restriction requirement and election have been incorporated into this action.
`
`Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quay/e, 1985 CD. 11, 453 QC. 213.
`
`Disposition of Claims*
`
`5)IZ Claim(s) 1-12 17-22 26 and 35-99 is/are pending in the application.
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`
`6)I:I Claim(s) _ is/are allowed.
`BIZ Claim(s
`1—12 17—22 26 and 35—99 is/are rejected.
`8)I:I Claim(s) _ is/are objected to.
`
`9)I:I Claim(s) _ are subject to restriction and/or election requirement.
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`
`htt
`
`:waw.usoto. ow atents/init events/
`
`h/index.‘s or send an inquiry to PPl—tfeedbackebuspto.dbv.
`
`Application Papers
`
`10)|:| The specification is objected to by the Examiner.
`11)I:| The drawing(s) filed on
`is/are: a)I:I accepted or b)I:| objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12)I:| Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119( )-(d) or (f).
`Certified copies:
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`Attachment(s)
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`1) X Notice of References Cited (PTO-892)
`
`2) D Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mai| Date
`.
`U.S. Patent and Trademark Office
`DTOL-326 (Rev. 11-13)
`
`Office Action Summary
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`3) I] |nterview Summary (Fm—0.413)
`Paper No(s)/Mail Date.
`4 I] o h
`_
`I
`1 er.
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`.
`
`Part of Paper No./Mai| Date 20140821
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`Applicant's arguments filed 07/22/2014 have been fully considered but they are
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`not persuasive.
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`(i) In regards to the applicant’s arguments that the rejection is unjustifiably
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`speculative, the examiner respectfully disagrees. In particular, just because the
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`applicant alleges that the flexibility of Leedy's circuit layers are related to conformance,
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`does not mean that modifying Bert/n with the low stress dielectric of Leedy would not be
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`desired or lead to an improved device. The applicant defines that the flexibility of their
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`device is based on a thin wafer and the inclusion of a low stress dielectric layer.
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`Therefore including a low stress dielectric layer within the device as taught by Bert/n
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`would lead to a flexible device. Furthermore, Leedy specifically states that the inclusion
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`of low stress dielectrics in devices provide advantages to lower the cost and complexity
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`of circuit fabrication and will enhance the performance of the circuit operation. Lastly,
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`rather than using the oxidation process of forming the insulation layers which could
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`perhaps damage the device through the thermal processes, forming the dielectric as
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`taught by Leedy is shown to be an alternative method that would not require the thermal
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`process and would lead to a device that will have enhanced performance characteristics
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`Page 2
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`The present application is being examined under the pre-AIA first to invent
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`provisions.
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`Response to Arguments
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`as taught.
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`(ii) In response to applicant's argument that the examiner's conclusion of
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`obviousness is based upon improper hindsight reasoning, it must be recognized that
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`any judgment on obviousness is in a sense necessarily a reconstruction based upon
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`hindsight reasoning. But so long as it takes into account only knowledge which was
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`within the level of ordinary skill at the time the claimed invention was made, and does
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`not include knowledge gleaned only from the applicant's disclosure, such a
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`reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA
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`1971 ). In particular, as shown the rejection does most definitely identify motivation to
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`combine the references within the references themselves (see above). Furthermore, it is
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`common knowledge that insulation layers and more specifically silicon oxide layers
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`maybe be formed from other methods than oxidation. Leedy teaches and shows a valid
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`alternative as well as clearly lays out benefits for using said low stress silicon oxide
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`layer in a similar device.
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`rational that said low stress dielectrics as taught by Leedy would lead to a dielectric with
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`(iii) In regards to the applicant’s arguments that Bert/n does not teach forming
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`dielectric layer through oxidation the examiner respectfully disagrees. In particular,
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`Bert/n clearly teaches that the dielectric layers are formed by oxidation (Col. 4, lines 30-
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`40) and the applicant even admitted as such in the arguments filed on 04/05/2013
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`(Page 28). In said arguments, the applicant admitted that the oxide is formed of
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`thermally grown oxide which is known to be high stress and 5 to 10 times the level of
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`stress than the oxides taught in the applicant’s specification. Therefore, the examiner’s
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`much lower stress than the dielectric as taught by Bert/n is accurate. And the examiner
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`maintains that one would want a device with dielectrics of much lower stress for, at the
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`very least, the reasons mentioned above.
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`(iv) In regards to the applicant’s question on why a lower stress dielectric would
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`be desirable in Bertin, the examiner responds by asking: why would one of ordinary skill
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`and creativity in the art not look to known and available art to improve the device of
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`Bertin? Since Leedy provided the motivation to include low stress dielectric as
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`mentioned above why would one not look to said teachings of Leedy and modify the
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`device of Bertin to improve it?
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`respectfully disagrees. Leedy specifically states that using layers that are formed by the
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`(V) In regards to the applicant’s arguments that the CTE matching of Leedy is not
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`required in Bert/n, the examiner acknowledges that while this may be true it does not
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`mean that it wouldn’t be desirable. Leedy teaches that the CTE matching would help to
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`minimize the extrinsic overall stress of the circuit layers. Since, Bert/n teaches forming
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`circuit layers why would one having ordinary skill in the art not modify Bertin with the
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`teachings of Leedy to help minimize stress regardless of whether Bertin teaches free-
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`standing circuit membranes.
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`(vi) In regards to the applicant's arguments that using the technique of Leedy
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`rather than Berlin would not lower the cost or enhance the performance, the examiner
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`methods as taught in interconnect structures provide those advantages and that
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`dielectric layers formed by oxidation lead to strongly compressive films while dielectrics
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`formed by the method of Leedy have tensile stress that is low and lead to more flexible
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`layers that won't fracture. This is clearly more desirable and would enhance
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`performance and would lead to lower cost and flexibility. These benefits would be
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`desirable to one of ordinary skill in the art and not just Leedy.
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`quality of subsequent process steps such as deposition and bonding.
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`(vii) In regards to the applicant’s arguments that it would not have been obvious
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`to combine the teachings of Bertin and Kato as suggested, the examiner respectfully
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`disagrees. In particular, as stated Bertin already teaches etching said circuit layers to
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`expose the signal paths but fails to carry out an extra step of polishing surface after
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`etching. Kato is relied upon to teach the method of polishing and not relied upon to
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`teach polishing in a certain area such as a backside or frontside since Bertin already
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`teaches thinning the substrate in the desired area as claimed, but merely is relied upon
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`to teach that polishing is known and that it would be desirable to carry out as it would
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`provide a smooth flat surface for bonding. Such a surface is desirable for bonding or
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`forming additional elements in the art since a surface after rough etching can leave it
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`uneven and not preferable for subsequent process steps. This is yet another
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`modification that one of ordinary skill in the art would look to make as it can improve the
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`Claim Rejections - 35 USC § 103
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`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
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`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102 of this title, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
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`comprising at least one vertical interconnect extending from a the first surface thereof to
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`1.
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`Claims 1-12, 17-22, 26, and 35-89 are rejected under 35 U.S.C. 103(a) as being
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`unpatentable over Bert/n et al. (U.S. Patent No. 5,202,754, from hereinafter “Bertin”) in
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`View of Kato et al. (U.S. Patent No. 4.939.568, from hereinafter “Kato”) in view of Leedy
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`(U.S. Patent No. 5,354,695).
`
`Regarding Claim 1, Bert/n teaches a first circuit layer comprising a first
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`substrate, a first surface having interconnect contacts, and a second surface opposite
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`the first surface (Fig. 3, circuit layer 50, substrate 52, first/second surfaces 56/58 (not
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`necessarily respectively), interconnect contacts 68/82) and a second circuit layer
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`comprising a second substrate and a first surface and a second surface each having
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`interconnect contacts, wherein the second surface is opposite the first surface (Fig. 3,
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`circuit layer 50, substrate 52, first/second surfaces 56/58 (not necessarily respectively);
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`interconnect contacts 68/82); wherein at least one of the first and second circuit layers
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`comprises a substrate thereof that is a substantially flexible semiconductor substrate
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`made from a semiconductor wafer thinned by at least one of abrasion, etching and
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`parting (Fig. 2, y to y' in which substrate is thinned to 5-20um and thinning specifically
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`shown in Fig. 3f-sg), and wherein the at least one of the first and second circuit layers
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`an the-second surface thereof and formed within a via etched into the semiconductor
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`substrate to accommodate the vertical interconnect, the vertical interconnect comprising
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`a conductive center portion and an insulating portion surrounding the conductive center
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`portion and adjoining sides of the via (Fig 3, vertical interconnects 66, insulated by
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`silicon oxide), a third circuit layer comprising a third substrate and a first surface having
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`interconnect contacts; and a plurality of bonds forming signal paths between the
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`interconnect contacts of the surfaces of the second circuit layer and the interconnect
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`contacts of the first surfaces of the first and third circuit layers (Fig. 3, third substrate not
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`shown but the steps repeat as described; bonds are shown specifically in Fig. 3i
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`between interconnect contacts 68/82; Col. 3-5).
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`Bert/n fails to specifically teach the at least one of the first and second circuit
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`layers is subsequently polished to form a polished surface after thinning.
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`Karo teaches using CMP to polish a surface to expose signal paths on a second
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`surface (Fig. 4(g-i); substrate 1, conductive posts 4a/b; Col. 6, lines 5-16).
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`In view of the teachings of Kato, it would have been obvious to a person having
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`ordinary skill in the art at the time of the invention to modify the teachings of Bertin
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`above to include the polishing the surface using CMP because CMP is a well-known
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`method to expose contacts on a substrate as it will provide a smooth flat surface for
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`insulation portion of the vertical interconnects by thermal oxidation resulting in high
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`bonding as exemplified by Karo.
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`Bert/n also fails to specifically teach wherein at least one of the first and second
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`circuit layers is substantially flexible. In particular, since Bert/n teaches forming the
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`stress insulation layer, it fails to teach flexible circuit layers (Note: the flexible circuit
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`layer must possess a low stress dielectric in order for it to be flexible).
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`Leedy teaches an IC circuit structure comprising substantially flexible circuit
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`layers wherein each of the circuit layers comprise an insulating low stress dielectric that
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`insulates electrical elements and through-substrate conductors wherein said low stress
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`dielectric layers are formed by an alternative dielectric deposition (Fig. 3 and 8, Col. 9,
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`lines 15-49 and Col. 16, lines 38—56).
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`minimize the extrinsic overall stress of the circuit layers. Furthermore, Leedy teaches
`
`In view of the teachings of Leedy, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin to
`
`include that the insulating dielectric used in the IC structure and the circuit layers is a
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`low stress dielectric layer (by using the formation technique of Leedy rather than Bert/n)
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`such that the circuit layers, including the flexible substrate, will then too be flexible
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`circuit layers due to the inclusion of the low stress dielectric and the thinned
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`semiconductor wafer because low stress dielectrics are desirable to form flexible circuit
`
`layers such that they may be able to withstand external stresses and furthermore still
`
`include a dielectric that can insulate the conductors formed therein from each other and
`
`other elements. Furthermore, as shown by Leedy, depositing the dielectric materials
`
`through the deposition process as taught results in a dielectric layers that have much
`
`lower stress as compared to the high stress films formed through oxidation. Also, Leedy
`
`teaches that these low stress dielectrics may be formed to match the coefficient of
`
`thermal expansion of the semiconductor material of the substrate which will help to
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`that using the low stress dielectric provide advantages to lower the cost and complexity
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`of circuit fabrication and will enhance the performance of the circuit operation (Col. 6,
`
`lines 22-58).
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`Regarding Claim 2, Bertin teaches a first circuit layer comprising a first
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`substrate and having topside and bottomside surfaces, wherein the topside surface of
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`the first circuit layer has interconnect contacts surface (Fig. 3, circuit layer 50, substrate
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`silicon oxide), a third circuit layer comprising a third substrate having topside and
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`52, topside/bottomside surfaces 56/58 (not necessarily respectively), interconnect
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`contacts 68/82), and a second circuit layer comprising a second substrate and having
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`topside and bottomside surfaces, wherein the topside and the bottomside surfaces of
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`the second circuit layer have interconnect contacts surface (Fig. 3, circuit layer 50,
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`substrate 52, topside/bottomside surfaces 56/58 (not necessarily respectively),
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`interconnect contacts 68/82); wherein at least one of the first and second circuit layers
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`comprise a substantially flexible semiconductor substrate made from a semiconductor
`
`wafer thinned by at least one of abrasion, etching and parting (Fig. 2, y to y' in which
`
`substrate is thinned to 5-20um and thinning specifically shown in Fig. 3f-3g), and
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`wherein the at least one of the first and second circuit layers comprising at least one
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`vertical interconnect extending from the topside surface thereof to opposite the
`
`bottomside surface thereof and formed within a via etched into the semiconductor
`
`substrate to accommodate the vertical interconnect, the vertical interconnect comprising
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`a conductive center portion and an insulating portion surrounding the conductive center
`
`portion and adjoining sides of the via (Fig 3, vertical interconnects 66, insulated by
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`bottomside surfaces, wherein the bottomside surface of the third circuit laver has
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`interconnect contacts; a plurality of bonds between the bottomside surface of the
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`second circuit layer and the topside surface of the first circuit layer; conductive paths
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`formed between the interconnect contacts of the topside of the first substrate circuit
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`layer and the interconnect contacts of the bottomside of the second circuit layer, and
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`conductive paths formed between the interconnect contacts of the topside of the second
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`circuit layer and the interconnect contacts of the bottomside of the third circuit layer, the
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`conductive paths providing electrical connections between at least two of the first,
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`second and third circuit layers (Fig. 3, third substrate not shown but the steps repeat as
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`described; bonds and conductive paths (vias) are shown specifically in Fig. 3i between
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`interconnect contacts 68/82 and through-substrate interconnects 66; Col. 3-5).
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`Bert/n fails to specifically teach the at least one of the first and second circuit
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`layers is subsequently polished to form a polished surface after thinning.
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`circuit layers is substantially flexible. In particular, since Bert/n teaches forming the
`
`Kato teaches using CMP to polish a surface to expose signal paths on a second
`
`surface (Fig. 4(g-i); substrate 1, conductive posts 4a/b; Col. 6, lines 5-16).
`
`In view of the teachings of Karo, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin
`
`above to include the polishing the surface using CMP because CMP is a well-known
`
`method to expose contacts on a substrate as it will provide a smooth flat surface for
`
`bonding as exemplified by Kato.
`
`Bert/n also fails to specifically teach wherein at least one of the first and second
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`insulation portion of the vertical interconnects by thermal oxidation resulting in high
`
`stress insulation layer, it fails to teach flexible circuit layers (Note: the flexible circuit
`
`layer must possess a low stress dielectric in order for it to be flexible).
`
`Leedy teaches an IC circuit structure comprising substantially flexible circuit
`
`layers wherein each of the circuit layers comprise an insulating low stress dielectric that
`
`insulates electrical elements and through-substrate conductors wherein said low stress
`
`dielectric layers are formed by an alternative dielectric deposition (Fig. 3 and 8, Col. 9,
`
`lines 15-49 and Col. 16, lines 38-56).
`
`Application/Control Number: 12/497,652
`Art Unit: 2896
`
`of the semiconductor material of the substrate which will help to minimize the extrinsic
`
`In view of the teachings of Leedy, it would have been obvious to a person having
`
`ordinary skill in the art at the time of the invention to modify the teachings of Bertin to
`
`include that the insulating dielectric used in the IC structure and the circuit layers is a
`
`low stress dielectric layer (by using the formation technique of Leedy rather than Bert/n)
`
`such that the circuit layers including the flexible substrate will then too be flexible circuit
`
`layers due to the inclusion of the low stress dielectric and the thinned semiconductor
`
`wafer because low stress dielectrics are desirable to form flexible circuit layers such that
`
`they may be able to withstand external stresses and furthermore still include a dielectric
`
`that can insulate the conductors formed therein from each other and other elements.
`
`Furthermore, as shown by Leedy, depositing the dielectric materials through the
`
`deposition process as taught results in a dielectric layers that have much lower stress
`
`as compared to the high stress films formed through oxidation. Also, Leedy teaches that
`
`these low stress dielectrics may be formed to match the coefficient of thermal expansion
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`overall stress of the circuit layers. Furthermore, Leedy teaches that using the low stress
`
`dielectric provide advantages to lower the cost and complexity of circuit fabrication and
`
`will enhance the performance of the circuit operation (Col. 6, lines 22-58).
`
`Regarding Claim 3, Bertin a first circuit layer comprising a first substrate and
`
`having a first and a second surface, wherein said second surface is opposite to said first
`
`surface(Fig. 3, circuit layer 50, substrate 52, first/second surfaces 56/58 (not necessarily
`
`Application/Control Number: 12/497,652
`Art Unit: 2896
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`second surface, wherein said second surface is opposite to said first surface; a plurality
`
`respectively), interconnect contacts 68/82) and a second circuit layer comprising a
`
`second substrate and a first surface and a second surface each having interconnect
`
`contacts, wherein the second surface is opposite the first surface (Fig. 3, circuit layer
`
`50, substrate 52, first/second surfaces 56/58 (not necessarily respectively); interconnect
`
`contacts 68/82); wherein at least one of the first and second circuit layers comprises a
`
`substrate thereof that is a substantially flexible semiconductor substrate made from a
`
`semiconductor wafer thinned by at least one of abrasion, etching and parting (Fig. 2, y
`
`to y‘ in which substrate is thinned to 5-20um and thinning specifically shown in Fig. 3f-
`
`3g), and wherein the at least one of the first and second circuit layers comprising at
`
`least one vertical interconnect extending from a the first surface thereof to an the
`
`second surface thereof and formed within a via etched into the semiconductor substrate
`
`to accommodate the vertical interconnect, the vertical interconnect comprising a
`
`conductive center portion and an insulating portion surrounding the conductive center
`
`portion and adjoining sides of the via (Fig 3, vertical interconnects 66, insulated by
`
`silicon oxide); a third circuit layer comprising a third substrate and having a first and a
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`of bond formed contacts between the first surface of the first circuit layer and the first
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`surface of the second circuit layer and between the second surface of the second circuit
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`layer and the first surface of the third substrate circuit layer; wherein at least two of said
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`contacts are selected from a group consisting of: a conductive signal path; a conductive
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`contact; and a non-conductive contact (Fig. 3, third substrate not shown but the steps
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`repeat as described; bonds are shown specifically in Fig. 3i between interconnect
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`contacts 68/82; Col. 3-5).
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`Bert/n fails to specifically teach the at least one of the first and second circuit
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`layers is subsequently polished to form a polished surface after thinning.
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`Kato teaches using CMP to polish a surface to expose signal paths on a second
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`surface (Fig. 4(g-i); substrate 1, conductive posts 4a/b; Col. 6, lines 5-16).
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`In view of the teachings of Kato, it would have been obvious to a person having
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`layer must possess a low stress dielectric in order for it to be flexible).
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`ordinary skill in the art at the time of the invention to modify the teachings of Bertin
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`above to include the polishing the surface using CMP because CMP is a well-known
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`method to expose contacts on a substrate as it will provide a smooth flat surface for
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`bonding as exemplified by Karo.
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`Bert/n also fails to specifically teach wherein at least one of the first and second
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`circuit layers is substantially flexible. In particular, since Bert/n teaches forming the
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`insulation portion of the vertical interconnects by thermal oxidation resulting in high
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`stress insulation layer, it fails to teach flexible circuit layers (Note: the flexible circuit
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`Leedy teaches an IC circuit structure comprising substantially flexible circuit
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`layers wherein each of the circuit layers comprise an insulating low stress dielectric that
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`insulates electrical elements and through-substrate conductors wherein said low stress
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`dielectric layers are formed by an alternative dielectric deposition (Fig. 3 and 8, Col. 9,
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`lines 15-49 and Col. 16, lines 38-56).
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`will enhance the performance of the circuit operation (Col. 6, lines 22-58).
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`In view of the teachings of Leedy, it would have been obvious to a person having
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`ordinary skill in the art at the time of the invention to modify the teachings of Bertin to
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`include that the insulating dielectric used in the IC structure and the circuit layers is a
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`low stress dielectric layer (by using the formation technique of Leedy rather than Bertin)
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`such that the circuit layers including the flexible substrate will then too be flexible circuit
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`layers due to the inclusion of the low stress dielectric and the thinned semiconductor
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`wafer because low stress dielectrics are desirable to form flexible circuit layers such that
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`they may be able to withstand external stresses and furthermore still include a dielectric
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`that can insulate the conductors formed therein from each other and other elements.
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`Furthermore, as shown by Leedy, depositing the dielectric materials through the
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`deposition process as taught results in a dielectric layers that have much lower stress
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`as compared to the high stress films formed through oxidation. Also, Leedy teaches that
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`these low stress dielectrics may be formed to match the coefficient of thermal expansion
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`of the semiconductor material of the substrate which will help to minimize the extrinsic
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`overall stress of the circuit layers. Furthermore, Leedy teaches that using the low stress
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`dielectric provide advantages to lower the cost and complexity of circuit fabrication and
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`Regarding Claims 4, Bert/n teaches a first circuit layer comprising a first
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`substrate and having a first and a second surface, wherein said second surface is
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`opposite to said first surface (Fig. 3, circuit layer 50, substrate 52, first/second surfaces
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`56/58 (not necessarily respectively), interconnect contacts 68/82) and a second circuit
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`layer comprising a second substrate and a first surface and a second surface each
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`having interconnect contacts, wherein the second surface is opposite the first surface
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`(Fig. 3, circuit layer 50, substrate 52, first/second surfaces 56/58 (not necessarily
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`respectively); interconnect contacts 68/82); wherein at least one of the first and second
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`circuit layers comprises a substrate thereof that is a substantially flexible semiconductor
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`substrate made from a semiconductor wafer thinned by at least one of abrasion, etching
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`and parting (Fig. 2, y to y‘ in which substrate is thinned to 5-20pm and thinning
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`specifically shown in Fig. 3f-3g), and wherein the at least one of the first and second
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`circuit layers comprising at least one vertical interconnect extending from a the first
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`surface thereof to an the-second surface thereof and formed within a via etched into the
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`Application/Control Number: 12/497,652
`Art Unit: 2896
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`between the second surface of the second circuit layer and the first surface of the third
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`semiconductor substrate to accommodate the vertical interconnect, the vertical
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`interconnect comprising a conductive center portion and an insulating portion
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`surrounding the conductive center portion and adjoining sides of the via (Fig 3, vertical
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`interconnects 66, insulated by silicon oxide); a third circuit layer comprising a third
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`substrate and having a first and a second surface, wherein said second surface is
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`opposite to said first surface; a plurality of bond formed contacts between the first
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`surface of the first circuit layer and the first surface of the second circuit layer and
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`Application/Control Number: 12/497,652
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`Page 16
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`substrate circuit layer; wherein at least two of said contacts are selected from a group
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`consisting of: a conductive signal path; a conductive contact; and a non-conductive
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`contact; wherein the at least one of the first and second circuit layers comprises
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`integrated circuitry defining an integrated circuit die having an area, wherein the
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`substrate of the at least one of the first and second circuit layers extends throughout at
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`least a substantial portion of the area of the integrated circuit die. (Fig. 3, third substrate
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`not shown but the steps repeat as described; bonds are shown specifically in Fig. 3i
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`between interconnect contacts 68/82; Col. 3-5; vias are insulated with silicon dioxide).
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`Bert/n fails to specifically teach the at least one of the first and second circuit
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`layers is subsequently polished to form a polished surface after thinning.
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`Kato teaches using CMP to polish a surface to expose signal paths on a second
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`surface (Fig. 4(g-i); substrate 1, conductive posts 4a/