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`27th annual
`§ proceedings
`
`. reliability
`'
`physics
`
`1989
`
`7OVLUb'OL
`
`Phoenix, Arizona 0 April 11, 12, '13, 1989
`345 East 47th St., New York, NY. 10017
`
` Sponsored by
`
`the IEEE Electron Devices Society an
`
`5 the IEEE Reliability Society
`
`1
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`'
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`«
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`IEEE Catalog No. 89cH2650-0
`,
`I
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`‘ Library of CongressCatalog Card No. 82-640313
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`Copyright © 1989 by the Institute of Electrical and Electronics Engineers, Inc.
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`SAMSUNG EXHIBIT 1016
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`Page 1 of 11
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`1989 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUMW
`_ NEWS
`79??
`
`SYMPOSIUM OFFICERS
`
`
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`’
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`m I
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`GENERAL CHAIRPERSON ............................................B. L. Euzem, Im’ez
`VICE GENERAL CHAIRPERSON...
`.. w. H. Schroen, Texas Instruments
`SECRETARY ..........................................
`.
`M. Towner, Xicor
`FINANCE............................................................................................... .. D. A. Baglee, Intel
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`-
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`f
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`1
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`l‘
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`SYMPOSIUM COMMITTEE CHAIRPERSONS
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`TECHNICAL PROGRAM ............................................. P. E. Kennedy, HughesAircraft
`PUBLICITY ........................................................................................... H. A. Schafft, NIST
`REGISTRATION ................................................................................B. A. Moore, RADC
`ARRANGEMENTS ..............................................................................R. C. Blish, II, Intel
`AUDIO~VISUAL .......................................................... C. A. Duvvury, Texas Instruments
`PUBLICATIONS ....................................D. Feliciano-Welpe, Oneida ReSearch Services
`EQUIPMENT DEMONSTRATIONS ............................................. G. A. Scoggan, IBM
`CONSULTANT................................................................... R. C. Walker, SAR Associates
`. CONSULTANT......................................................... D. F. Barber, Scien-TecliAssociates
`
`BOARD OF DIRECTORS
`B LEI-126m
`Intel
`7
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`A. L. Tamburrino
`RADC
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`L. A. Kasprazak '
`IBM
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`N. McAfee
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`L
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`R. W. Thomas
`RADC‘
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`M. H Woods
`Intel
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`'
`'
`'
`fee incl"
`page, provided the per-co
`'_ Street, Salem, MA 01970.13ylnstructgmed m the “dc 18 Paid lhrough the Copynghl Clearance Came" 21 congress
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`rs are permitted to hotoco
`isolated articles for noncommercial classroom
`n
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`.
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`ces
`use Wllhout fee. For other copyin
`re
`‘
`.P .
`Py
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`IEEE, 345 E33147”) Street, New 3’
`p m or republication permissron, write to Director, Publrshmg Seer
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`Electrical and Electronics Engineeerfrti NY 10017. A“ fights resewed' cepyrigm © 1989 by the Inmth or
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`SAMSUNG EXHIBIT 1016
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`Page 2 of 11
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`.I TABLE OF CONTENTS
`DIELECTRIC RELIABILITY
`Session Chairperson: N. Mielke, Co-Chairperson: Eiji Takeda
`
`Effect of Mechanical Stress For Thin Si02
`Y. Ohno, A. Ohsaki, T. Kaneoka, J. Mitsu
`
`Extensions of the Effective Thicknes
`D.J. Coleman, Jr., W.R. Hunter,
`
`>
`5 Theory of Oxide Breakdown
`G.A. Brown and I.-C. Chen ............................................................
`
`39
`
`.............. 43
`'
`V
`
`radiative Regions
`
`,
`
`V
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`Time Dependent Dielectric Breakdown of 210A Oxides
`K.C. Boyko and BL. Gerlach .....................................................................................................................1
`A Study of the Breakdown Testing of Thermal Silicon Oxides and the Effects of Preoxidation
`Surface Treatment
`, D.B. Kao, B.E. Deal, J.M. deLarios and CR. Helms ........................................
`...........................L...9
`Interface Degradation and Dielectric Breakdown of Thin Oxides Due to Homogeneous Charge
`InjectionsM. Kerber and U. Schwalke...................................................................................................................... 17
`Interface State Generation Due to Election Tunneling into Thin Oxides
`'
`‘
`Y. Ozawa, M. Iwase and A. Toriumi....................................................................................................... 22
`Polarity Dependence of Thin Oxide Wearout
`'
`‘
`‘
`-
`-
`DJ. Dumin, KJ. Dickerson, M.D. Hall and GA. Brown.....................................................;..............28
`Films in TDDB and CCST Characteristics
`hashi, M. Hirayama and T. Kato....................................34
`
`Y. Fong and C. Hu ....................................................................
`
`FAILURE ANALYSIS, SPECIAL DEVICES and E80
`Session Chairperson: Steve Groothuis, Co-Chairperson: Wallace Anderson
`New Applications of Focused Ion Beam Technique to Failure Analysis and Process
`M. Murase, T. Kaito, T. Adachi, and S. Inoue ..................................
`Monitoring of VLSI
`K. Nikawa, K. Nasu,
`nect Vias
`A New Reliability Problem Associated with AI Ion Sputter Cleaningrof Intercon
`H. Tomioka, S.-I. Tanabe and K. Mizukami.................................
`....................................._................ 53
`Analysis of Aluminum Gallium Arsenide Laser Diodes Failing Due to Non
`Behind the Facets
`,
`7
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`. Fritz, L.B. Bauer, and 08. Miller.....................................
`.........................................................59
`Aging Effects in GaAs Schottky Barrier Diodes
`K.A. Christianson..................L................_...
`
`......
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`ESD Phenomena in Graded Junction Devices
`C. Duvvury, RN. Rountree, HJ. Stiegler, T. Polgreen, and D. Corum .......................................
`
`71
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`Internal ESD Transients in Input Protection Circuits
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`SAMSUNG EXHIBIT 1016
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`Page 3 of 11
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`HOT-CARRIER EFFECTS I
`Session Chairperson: Cary Yang, Co-Chairperson: Bob Yun
`
`The Effect of Minute Impurities(H,OH.F‘) on SiOZ/Si Interface Investigated by Nuclear
`Resonant Reaction and Electron Spin Resonance
`.
`.
`_
`.
`Y. Ohji, Y. Nishioka, K. Yokogawa, K. Mukai, Q. Qiu, E. Arai, and
`T. Sugano..................................................................................................................................................... 82
`
`Kinetics of Hot—Carrier Effects for Circuit Simulation
`
`S. Aur ......................................................................................................................................................... .. 88
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`Low-Voltage Hot-Electron Currents Degradation in Deep Submicrometer MOSFETs
`J. Chung, M.-C. Jeng, J.E. Moon, P.K. K0, and C. Hu ....................................................................... ..92
`
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`Hot-Carrier Degradation in P-Channel MOSFETs
`s.w. Mitt], and MJ. Hargrove ..........................................................................................................
`
`98
`
`/
`An Investigation of the Time Dependence of Current Degradation in MOS Devices
`R. Rakkhit, M.C. Peckerar, and CT. Yao ................................,..........................................................103
`
`Hot-Carrier-Induced Latchup and Trapping/Detrapping Phenomena
`, C.M. Wang, J.J. Tzou, P. Tan, and CY. Yang ...........................................................
`
`_
`-
`...................110
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`PACKAGING ISSUES ,
`Seesion Chairperson: Gene Gottlieb,
`Co-ChaIrperson: Melanie Iannuzzi-Glogovsky .
`
`I
`HAST Applications: Acceleration Factors and Results for VLSI Components
`D.D. Danielson, G.Marcyk, E. Babb and S. Kudva...........................................................................“114
`
`Improved EPROM Moisture Performance Using Spin-On-Glass (SOG) for Passivation
`Planarization .
`'
`I
`f .-
`.-
`a
`I. GaetaandKJ. Wu ......................................................
`.........................
`......
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`........
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`.....
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`On-Chip Measurement of Package-Related Metal Shift Using an Integrated Silicon Sensor .
`A. Bossche..........................................................................
`..............
`...................................................41273
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`1
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`A
`p
`k
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`L
`The Impact of Wafer Back Surface Finishion Chip Strength
`T.B. Lim............................................................................................................................l31 .
`
`V
`I
`V
`A Reliability Study of All-Sn Eutectic Bonding with GaAs Dice A
`GS. Matijasevic and CC. Lee...............................................................................................................137
`
`.7
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`f
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`Electrical Overstress of Nonencapsulated Bond Wires
`.............
`.......
`R- K1118, C. Van Schaick andJ. Lusk.........................................
`DEVICE RELIABILITY I
`SesSIon Chairperson: Walter Slusark, Co-Chairpersoni David'Gibeon' V
`I
`Angled Implant Fully Overlapped LDD (AleFOLD) NFE'i‘S for Performanceand Reliability 7
`,.
`,5
`A. Bryant T. Furukawa J Mandelman S Mi
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`til, W. Noble, E. N
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`r W. Wade, S. Ogura, and M. Wordeman ..........................................
`........................................152 -;
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`t
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`Page 4 of 11
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`Long Term Reliability of SiO /SiN/Si02 Thin Layer Insulator Formed in 9pm Deep Trench on
`High Boron Concentrated Si icon
`,
`S. Murata, S. Kuroda, 0. Enomoto, A. Nishirnura, H. Kitagawa
`’
`and S. Hasegawa .......................................................................................................................................
`Reliability Aspects of Laser Programmable Redundancy: Infrared vs. Green, Polysilicon vs.
`Silicide
`J.D. Chlipala and L.M. Scarfone...........................................................................................................163
`Fatigue Mechanisms in Thin Film Potassium Nitrate Memory Devices
`A.K. Kulkarni, G.A. Roher, L.D. McMillan and SE. Adams...........................................................171
`
`158
`
`HOT-CARRIER EFFECTS II
`Session Chairperson: Wendell Noble
`
`P-MOSFET Gate Current and Device Degradation
`T.—C. Ong, K. Seki, P.K. K0, and C. Hu...............................................................................................178
`Oxide Charge Trapping and HCI Susceptibility of a Submicron CMOS Dual—Poly (N+/P+)
`Gate Technology
`S.W. Sun, K.-Y. Fu, C. Swift, and J.R. Yeargain................................................................................183
`Hot-Carrier Induced Instability of 0.5 pm CMOS Devices Patterned Using Synchrotron X-ray
`Lithography
`,
`C.C.-H. Hsu, L.K. Wang, J.Y.-C. Sun, M.R. Wordeman, and TH. Ning........................................
`
`189
`
`J.S. Suehle and HA. Schafft..................................................................................................................229
`
`ELECTROMIGRATION and METALLIZATION
`Session Chairperson: John Yue, Co-Chairperson: Giorgio Riga
`Stress Driven Diffusive Voiding ofAluminum Conductor Lines
`F.G. Yost, D.E. Amos and AD. Romig, Jr......................................;..................................................193
`r and Titanium Additionto Aluminum Interconnects on Electro- and Stress-
`Effects of Coppe
`Migration Open Circuit Failure
`T. Hosoda, H. Yagi and H. Tsuchikawa ...............................................................................................202
`Beam Deposited Aluminum Metallimtions
`Electromigration of Ionized Cluster
`R. E. Hummel.............................................
`.......................
`..............
`................................................
`The Properties ofAl-Cu/Ti Films Sputter Deposited at Elevated Temperatures and High DC
`Bias
`T. Takada and H. Tsuchikawa ...................................................
`
`207
`
`T. Hariu, K. Watanabe, M. Inoue,
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`Electromigration Interconnect Lifetime Under AC and Pulse DC stress
`B.K. Liew, N.W. Cheung and C. Hu......................................................................................................
`irectional (BC) and Pulsed Unidirectional
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`- Characterization of Electromigration Under Bid
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`215
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`210
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`The Electromigration Damage Response Time and Implications for DC and Pulsed
`Characterizations
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`SAMSUNG EXHIBIT 1016
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`Page 5 of 11
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`THE IMPACT OF WAFER BACK SURFACE FINISH ON CHIP STRENGTH
`
`Thiam Beng Lim
`Texas Instruments Singapore Pte Ltd
`990 Bendemeer Road
`Singapore 1233
`Tel: 2902208
`
`Abstract
`
`A correlation has been found between the
`wafer back surface roughness and the resistance
`of
`the chip to stress induced failures.
`Chip
`strength was measured using the "simply-supported
`beam" method
`for
`chips of different backside
`roughness.
`Encapsulated
`samples
`were
`subsequently
`subjected
`to mechanical
`impact
`loading and thermal stresses as
`in vapour phase
`reflow (VPR).
`The results show that
`the chip
`strength
`bears
`an
`inversely
`proportional
`relationship with
`the roughness of
`the wafer
`back.‘ It is hence important to control
`the wafer
`back
`surface
`roughness
`for
`reliability
`improvement,
`especially
`surface
`mount
`devices.
`
`for
`
`Introduction
`
`Chip cracking within an encapsulated IC
`device, Figure (1),
`is a stress related mechanism
`and is a combined effect of the strength of the
`chip and assembly stresses.
`
`PLASHC
`
`SUCON CWP
`CONNECHNG
`VVfliE
`
`I
`CHP BOND J
`
`\ CHTP PAD_
`
`Fig (1) Typical cross-sectional view of an SMD
`
`dePends,
`surface
`
`The mechanical strength of a silicon chip
`to a large extent, on the quality of its
`finish since
`surface
`flaws
`such
`as
`
`for~ stress
`sites
`produce
`grooves or craters
`concentration [1]. Wafer fabrication finishing
`proceSSes
`such as grinding,
`lapping, polishing,
`or dry etching have a direct impact on the extent
`of surface damage.
`Thermal mismatch between the
`silicon chip and
`the other materials
`commonly
`used in IC assembly can result
`in high reSidual
`Stresses in the chip.
`These,
`as well
`as other
`externally applied stresses,
`together with the
`surface flaws
`invariably weaken the chip.
`In
`severe cases the chip cracks. While in others
`micro-cracks or fissures are initiated and these
`d0
`not manifest
`themselves
`until
`additional
`Stresses are imposed on the package cauSing the
`chip to crack.
`CH2650-0/89/0000—0131$01.00 © 1989 IEEE/l RPS
`
`Efforts [2,3,4,5] to reduce or eliminate
`this failure mechanism have,
`in the past,
`been
`directed mainly in the reduction of
`IC assembly
`stresses. These include improvements in wafer saw
`quality,
`choice of better
`thermally compatible
`materials,
`optimisation
`of
`package
`design,
`reduction of voids in the die attach and, of late,
`use of
`low stress die
`attach materials which
`either have a low modulus of elasticity or which
`require a low temperature curing, or both.
`The
`results had meant that such a failure mode is now
`significantly reduced.
`However,
`for
`a
`total
`eradication,
`there are other factors which need to
`be considered.
`rThe influence of wafer fabrication
`finishing processes,
`for example, has yet
`to be
`investigated thoroughly.
`
`as illustrated in Figure (2).
`
`
`
`Surface mount devices (SMD) are generally
`more vulnerable to stress induced failures.
`This
`is
`due mainly to the elevated temperatures
`in
`solder reflow,
`such as vapour phase reflow (VPR)
`or
`infrared reflow (IR) processes, which subject
`the devices
`to an
`enhanced state of mismatched
`thermal expansion.
`
`by
`thinning
`of wafer
`The mechanics
`lapping or
`as grinding,
`mechanical means
`such
`removal
`of material
`by
`polishing involve
`the
`abrasion.
`Although unintentional,
`these actions
`leave
`flaws
`on
`the wafer
`surface which become
`local regions of weakness. Further processing may
`include an etching step which can rectify such
`local
`flaws and tends to restore the chip strength
`to some extent
`[6].
`However,
`not all wafer
`fabrication practices include this extra etching
`step.
`The present works
`focus on the need for
`controlling the wafer
`back
`surface quality as
`produced by the later category of practice,
`in
`particular, wafer thinning by grinding.
`. Measurement of surface defects
`
`- when
`produced,
`however
`surface,
`Any
`suitably magnified, will reveal itself as a series
`of
`“peaks
`and valleys" which may vary both in
`height
`and
`spacing.
`The wafer back surface as
`produced by grinding is no exception.
`It-is by
`the magnitude of
`these
`irregularities that
`the
`finish of surface is determined.
`Thus,
`in order
`to control
`the grinding process,
`it is useful
`to
`employ a surface quality parameter as a measure of
`its roughness.
`The extent of the surface damage
`is thus reflected by the value of this parameter;
`a
`larger value indicates more
`severe flaws
`and
`vice-versa.
`
`The most commonly used method of assessing
`roughness
`employs
`a
`sharply
`pointed
`surface
`the excursion of which,
`as
`it
`traversed
`stylus,
`these
`irregularities,
`are magnified,
`across
`recorded and computed to give a measure of
`its
`roughness.
`These
`are
`recorded ‘in units ’of
`micro-meter or micro—inch.
`Three most
`commonly
`quoted roughness parameters are Ra, Rmax and Rt,
`
`SAMSUNG ET AL. EXHIBIT 1016
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`SAMSUNG EXHIBIT 1016
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`Page 6 of 11
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`.... ma,
`Wm H ,
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`s. _ a
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`ln1=rneosured Ien th
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`Fig (2) Definitions of surface roughness
`parameters
`
`arithmetic mean
`the
`is
`The Ra _value
`roughness measured
`along
`a
`sampling
`surface
`length and is commonly used as a general purpose
`surface finish parameter.
`These are mean values
`'and do not
`fully reflect
`the extent of
`local
`surface defects.
`The Rmax values on the other
`hand give the maximum individual peak to valley
`height
`along
`the measured
`length
`and
`thus
`measure the largest surface defect.
`The distance
`between the highest peak and the lowest valley
`along the measured length is represented by the
`Rt value.
`~
`
`Fracture strength
`
`the material
`Depending on the nature of
`yunder stress,
`its ultimate fracture may or may
`not
`be
`preceeded
`by
`some
`degree
`of plastic
`deformation.
`A brittle material
`like silicon
`exhibits no plastic deformation and its fracture
`is highly dependent
`on
`its ’surface condition.
`The fracture strength of silicon is therefore not
`a unique material property [1]. Average fracture
`strength
`ranging from 2530
`lb/in2 to 115600
`lb/in2 corresponding to surface flaws of between
`0.02 uin and 0.4 uin depth have been reported
`:L[3].
`.
`-
`Conventional strength testing methods are
`also applicable to brittle materials
`although
`some hardware modifications are usually necessary
`[1].
`A "three—point
`loading" or "simply-
`supported"simply-supported beam"
`test method is
`commonly used for silicon.
`_The
`test
`sample is
`supported at both ends with the loading applied
`at the middle.
`An alternative method consists of
`uniformly loading a thin disk of silicon until it
`fractures.
`In both cases the outer fibre of
`the
`sample is in tension and failure occurs when the
`stress concentrated at
`the local
`flaws exceeds
`the ultimate strength of the atomic bonds.
`
`.
`
`Many empirical' fracture criteria have
`been proposed to predict the fracture stress as a
`function of the flaws size including [7]:
`
`m x Kic
`5c = ................... --
`Sq root
`(3.142 x a)
`
`Where Sc = tensile fracture stress
`2a = size of semi-ellipical flaw
`m = flaw geometrical constant
`Kic = material fracture toughness
`
`reduction in the flaw
`a
`is seen that
`It
`size strengthens the material. Conversely,
`lower
`applied
`stresses
`increase
`the
`tolerance
`for
`surface flaws.
`
`Experimental procedure
`
`Sample preparation
`
`A test of chip strength in relation to its
`surface finish requires a technique in which both
`parameters
`can
`be
`measured
`accurately.
`Additionally,
`the test methods adopted must also
`realistically reflect
`the stresses that
`can
`be
`experienced by an encapsulated chip.
`Thus,
`in
`order
`to obtain the desired degrees of
`surface
`finish on the chips, several wafers were processed
`using
`deliberately
`altered
`grinding
`process
`parameters.
`These wafers were nominally 19 mils
`thick and subsequently diced to 160 x 300 mils
`chips,
`corresponding to
`an
`actual
`SMD device
`size.
`The
`surface finish of
`these chips were
`determined individually on a Taylor—Hobson, Model
`5—12 profilometer.
`All
`three surface roughness
`parameters on the same measured length were noted
`and the chips were
`subsequently subjected to a
`series of stress tests.
`This enables
`a direct
`correlation between
`chip
`strength and
`surface
`finish.-
`I
`
`Visual examination of these surfaces using
`the scanning electron microscope showed that
`the
`rougher samples had suffered surface damages: deep
`grinding marks as well as pitting and cratering on
`the silicon surface.
`A typical comparison between
`rough and smooth grinding can be seen in Figure
`(3)
`
`ig (3a) Rough silicon chip surface finish
`produced by grinding
`
`132
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`.k
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`SAMSUNG EXHIBIT 1016
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`Page 7 of 11
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`

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`we...‘“a,a.
`
`that
`showed
`experimentation
`Extensive
`depending on the drop height,
`fracture can occur
`in the chip only or
`in both the chip and the
`plastic encapsulant.
`Fracture in both the chip
`and encapsulant does not reflect
`the strength of
`the
`chip.
`Thus
`the
`test was
`calibrated by
`adjusting the drop height
`such that
`the impact
`induced only the chip to fracture without damage
`to the plastic.
`The drop height
`in these tests
`was set at 12 inches so that the impact energy was
`constant
`in
`each
`case.
`Inspection for
`chip
`failures is by means of acid decapsulating the
`tested specimens.
`A dry decapsulation method by
`mechanical means is not preferred as the chip may
`be
`fractured in
`the process
`and
`renders
`the
`results unrepresentative.
`
`Fig (3b) Smooth silicon chip surface
`‘
`produced by grinding
`
`Simply-supported beam test
`In this test
`individual chip with known
`surface finish is
`supported on
`a V—block
`and
`centrally loaded via a semi-spherical
`ram until
`fracture occurs.
`A schematic representation of
`this set-up is illustrated in Figure (4).
`
`. \’!”,,,- FORCE undGE
`
`METALLIC BALL
`(d 140 mils)
`
`ELASTOMER PAD
`(1601315x43 mils)
`suucow DIE
`(160x300x1 9 mile)
`
`“ASKING TAPE
`(GREATLY
`EXAGGERATED)
`
`VEE " BLOCK
`
`_.
`
`Flg (4) "Simply-supported beam" test
`for chip strength
`
`the
`This subjects the ground surface of
`Chip to a state of
`tensile stress.
`The ram is
`set to traverse at a constant speed of 0.1 in/min
`SO that dynamic effects may be minimised;
`A
`force gauge attached to the ram registers the
`fracture strength of the chip.
`
`test can be conducted in two ways;
`The
`in which the ram comes
`into direct contact
`one
`with the chip and the other in which the applied
`load is cushioned by an elastonomer pad.
`The
`latter
`arrangement
`is
`preferred
`since
`it
`distributes
`the
`applied load somewhat
`and
`in
`avoiding point contact also avoids concentrated
`loading.
`
`Impact test
`
`to the simply-supported beam
`In contrast
`the
`strength of
`the
`chip
`test which measures
`an impact
`test was devised
`before encapsulation,
`as
`a
`highly
`accelerated test
`to
`assess
`the
`strength of
`the chip in the encapsulated form.
`This test bears similarity to the standard Charpy
`test or
`the Izod test
`[8] which determines
`the
`toughness of
`a material
`and
`its capacity for
`resisting shock.
`A swinging pendulum is set
`to
`strike a
`standard notched test
`specimen.
`The
`notch sets up
`stress concentration and ensures
`failure.
`The
`recorded energy on
`impact
`is
`a
`measure of its mechanical strength.
`
`encapsulated
`subjects
`test
`The present
`chips with known surface finish to a mechanical
`impact or shock loading.
`A 310g weight is allowed
`to fall
`freely from some height once onto each
`specimen as shown in Figure (5).
`
`l
`
`310
`m
`
`\
`
`- DROP
`WSGHT
`
`STATIONARY
`PLUNGER
`
`ENCAPSU LATED
`CHIP
`
`Fig 5 The mechanical
`
`impact test
`
`For simplicity the surface finishes of the
`chips were first determined and segregated into a
`"rough"
`and
`a
`"smooth"
`group
`before
`encapsulation. These have Ra values of 7 to 9 uin
`and
`1
`to 2 uin respectively.
`,
`A statistical
`analysis on the number of fractured chips in these
`two
`groups
`observed
`under
`identical
`test
`conditions helps determine
`their
`resilience to
`fracture under impact
`loading.
`
`
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`_______________________________
`Surface mount stress simulation
`
`Segregated chips with rough (7 to 9 uin
`and smooth (1 to 2 uin Ra) surface finishes
`Ra)
`assembled
`following the
`normal
`assembly
`were
`process
`flow.
`A
`copper
`leadframe was used.
`These were subjected to a VPR process to impose
`additional
`stresses
`on
`the encapsulated chip.
`The
`samples were
`exposed
`to
`a
`215
`deg
`C
`60
`temperature
`for
`seconds.
`The
`test was
`repeated three times to simulate possible board
`rework as is widely practised.
`As
`in the impact
`test,
`inspection for chip failures was by means
`of acid decapsulating the tested specimens.
`'
`
`.Experimental results
`
`is seen
`any given chip surface it
`For
`.
`that the extent of surface damage or irregularity
`can be
`reflected very differently depending on
`the choice of surface finish parameters.
`Table
`(1)
`shows
`some examples of the typical measured
`values of Ra, Rt and Rmax of the same chip and on
`the same sampling length.
`The Ra readings which
`give
`the
`average
`.values
`of
`the
`surface
`irregularities
`are
`noted
`to be
`an order of
`magnitude smaller than the Rt or Rmax readings.
`
`WRU'IU'IQ-hbkom
`
`9.
`8.
`8.
`7.
`9.
`1.
`l.
`1.
`
`1l
`
`4664O1551l
`
`Table (1) Typical measured chip surface finish
`
`fracture strengths measured in the
`The
`simply-supported beam test
`are charted against
`the Ra, Rt and Rmax values as in Figures (6),
`(7)
`and (8).
`
`
`
`S
`
`a
`
`‘15
`
`is
`s
`Ra (MICRO-INCH)
`
`m
`
`as r
`
`is
`
`Fig (6) Variation of chip strength with
`surface finish parameter Ra
`
`
`
`
`
`134
`
`UDDI—mmc—cnbm‘fl
`
`
`
`Rmax (MICRO-INCH)
`
`Fig (7) Variation of chip strength with
`surface finish parameter Rmax
`
`Rt
`
`(MICRO INCH)
`
`Fig (8) Variation of chip strength with
`surface finish parameter Rt
`
`Chips with the rougher finish fractured fl
`loads than those which are smoother.
`For
`lower
`range
`of
`surface
`finish
`considered the
`the
`difference in the fracture strength can be as much
`a§ a factor of 2.
`It was noted that
`the CMPS
`with the smoother
`finish had
`the
`tendency to
`ShattEF
`on
`failing whereas
`those which were
`rougher
`tended to break
`into two halves.
`A"
`‘“Y9”Sely Proportional
`relationship is
`seen to
`eXlSt between the fracture strength and the three
`surface finish parameters:
`the chip weakens as the
`degree of surface damage is increased.
`
`the chip is weakEned by a rough haCk
`That
`grinding process
`is
`further
`illustrated by F“
`«‘WPaCt test.
`Even in the encapsulated form, Ch‘ps
`with the r0Ugher
`finish were noted to have
`a
`h19her
`tendency to fracture under
`such loading'
`hgse results are tabulated in Table (2). U5)”2
`hi-square
`statistical
`analysis,
`these
`FESUItS
`show that up to a 98% confidence level
`there “
`ifference between the two samples-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`7 -187 70-188
`
`Propn of
`failure
`Surface in impact
`Finish
`test
`
`Smooth
`Rough
`
`5/80
`’ 17/80
`
`Propn of
`failure
`in VPR
`
`‘
`
`0/40
`2/40
`
`
`
`Rt
`(uin)
`
`5
`5
`
`Rmax
`(um)
`
`5-47
`
`This
`finish are weaker.
`surface
`rougher
`the
`reinforces
`the validity of
`the simply-supported
`beam test
`results and is significantly important
`since some form of
`impact
`loading on the package
`is
`likely in the manufacturing process.
`These
`'include general handling, backend processes such
`as
`trim and
`form,
`transit
`in electrical
`test
`handlers and during board mounting.
`
`Table (2) Experimental results
`
`In the VPR test for surface mount stress
`simulation,
`fractured chips were noted in the
`group with the rougher finish whereas there were
`no failures from the smooth group. These results
`are included in Table (2).
`The failure mode was
`different from those seen in the simply-supported
`beam and the impact
`tests in that
`the chips did
`not
`shatter nor were
`they completely broken.
`Rather,
`they appeared to have cracked;
`the crack
`lines originating from the ground surface. These
`results further reinforce the observations that
`chips with
`the
`rougher
`surface
`finish
`are
`In
`weaker.
`addition
`these
`surface
`defects
`provide local
`regions of weakness since they can
`act as sites for stress concentration.
`
`Discussion of results
`
`That the measured values for Rmax and Rt
`ground
`chip
`surface
`do
`not differ
`the
`on
`significantly appears to suggest
`that
`the wafer
`back grinding process is fairly consistent:
`the
`maximum individual peak to valley height
`in each
`case is almost
`identical
`to the overall peak to
`valley height.
`0f
`the
`three surface
`finish
`parameters,
`the
`Rmax
`values
`are
`deemed most
`important
`from the current
`research view point
`since
`it
`is
`a measure of,
`the largest
`surface
`defect. Additionally and more importantly,
`the
`strength of
`the material
`is dependent
`on
`its
`weakest
`local
`region rather
`than
`on
`average
`values.
`
`A
`
`chip
`of
`trend
`decreasing
`general
`surface
`with
`increasing
`strength
`fracture
`three
`the
`is observed for
`each of
`muthess
`chips
`surface
`finish parameters,
`showing that
`It
`is
`with rougher finish have been weakened.
`noted that the plot for the Ra values are not as
`well distributed as those for Rmax and Rt values;
`the R3 Plot
`is skewed. This means that there 15
`a tendency for chips with severe surface damage
`t0
`be mis-represented
`by
`a
`smaller
`average
`values.
`In addition it
`fulfills theoretical
`EXPectations
`that
`the strength of
`the material
`does not depend on average values of the surface
`defECtS-
`It would
`therefore
`appear
`that
`a
`Suitable control on the grinding process is one
`meh Produces desirably small values of the Rmax
`parameter
`since
`this
`serves
`as
`an
`effective
`control on the chip strength.
`
`that even in the
`shows
`test
`impact
`The
`enCéilisulated form the chip surface roughness has
`E1$lgnificant
`influence on its susceptibility to
`failure: for a given impact energy, chips w1th
`
`An encapsulated IC device is in principle
`a bonded composite body of
`3 different materials
`namely,
`silicon chip,
`leadframe and the plastic
`encapsulant,
`each
`having
`vastly
`differing
`Of
`mechanical
`properties.
`these
`the most
`important
`is the coefficient of thermal expansion
`(CTE).
`Elevated
`temperatures
`introduce
`an
`enhanced
`state of mismatched thermal
`expansion
`within the composite body and induce a high stress
`in the chip.
`The material with a larger CTE is
`restricted from expanding naturally by one with
`the smaller CTE, while on
`the other hand,
`the
`material with the smaller CTE would be compelled
`to expand more than its natural capability. Under
`these conditions,
`the silicon chip, which has the
`smallest CTE,
`is induced by the leadframe chip pad
`to be
`in tension.
`Similarly, when SMD's
`are
`subjected to temperatures in the region of 215 deg
`C during board mounting by VPR or IR processes,
`a
`high
`tensile
`stress
`in
`the
`chip
`is
`to
`be
`expected.
`Indeed,
`the introduction of
`such high
`stresses is verified by stress analysis using the
`Finite Element Modelling technique at 215 deg C.
`[The stress distribution thus obtained is shown in
`‘ Figure (9).
`
`
`
`Fig (9) Stress distribution of an SMD at a typical
`solder reflow temperature, 215‘degc
`
`The VPR stress simulation shows that such
`stresses are sufficiently high to cause failures
`in the chips with the rougher surface finishand
`is of vital
`importance
`to SMD's.
`It will
`be
`realised that
`the chip experiences similar state
`of stress in the simply—supported beam tests.
`
`135
`
`
`
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`Acknowled es
`
`to the engineering
`The author is grateful
`personnel of TI Singapore who have in one way or
`another contributed to the success of
`this work.
`Special
`thanks goes
`to Dan Dunn
`(TI Dallas)
`for
`preparation of the experimental wafers, Leong Chew
`Heng and Liaw Kok Pang for their assistance in the
`experimental works, Lim Kim Kok for the graphical
`illustrations
`and
`last
`but
`not
`least Masood
`Murtuza for his continued encouragement.
`References
`
`M) Rmym1WR:"SflimnsaMcmdmtm
`technology” McGraw-Hill, 1975
`
`"Die attach in
`(2) Bolger J C and Mooney C T:
`Hi-Rel P-Dips: Polyimide or low chloride
`epoxies?", Proc 34th ECC, CHMT (IEEE),
`pp 63-67, 1984
`
`
`
`Kessel C G M, Gee S A and Murphy J J:
`"The quality of die-attachment and its
`relationship to stresses and vertical die—
`cracking”, Proc 33rd ECC, CHMT (IEEE),
`pp 237-244, 1983
`*
`
`Groothuis S, Schroen w and Murtuza M:
`"Computer aided stress modelling for
`optimizing plastic package reliability",
`Proc 23rd IRPS, pp 184—191, 1985
`
`Ted B C and Lim T B: "Die bonding stress
`analysis", Digest of 5th TI Japan Technical
`Meeting, vol 5, pp 15-16 1988
`
`Hawkins G, Berg H, Mahalingam M, Lewos G and
`Lofgran L: "Measurement of silicon strength
`as afffected by wafer back processing", Proc
`25th IRPS, pp 216-223 1987
`
`Broek D: "Elementary engineering fracture
`mechanics", Noordhoff Int Publ 1974
`
`Higgins R A: "Engineering Metallurgy - Part
`Applied Physical Metallurgy", English
`
`1
`
`thermally matching
`of
`choice
`The
`materials can help reduce this stress.
`However,
`this
`is usually made at
`the expense of other
`considerations.
`The
`CTE of
`some
`typical
`IC
`assembly materials are as follows:
`
`Material
`Silicon
`Alloy 42 leadframe
`Copper
`leadframe
`Mold compound
`
`CTE (E-OS/deg C)
`2.3
`4.7
`17.0
`18.0
`
`A lower stressed chip is to be expected
`with Alloy
`42
`leadframe
`in
`view of
`its
`considerably smaller CTE. However, both the VPR
`simulations
`and
`the
`stress
`analysis
`in
`the