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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________________
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`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
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`ELM 3DS INNOVATIONS, LLC
`Patent Owner
`
`____________________
`
`Patent No. 8,791,581
`____________________
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`DECLARATION OF DR. PAUL D. FRANZON
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,791,581
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`TABLE OF CONTENTS
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`
`INTRODUCTION ........................................................................................... 1
`I.
`II. QUALIFICATIONS ........................................................................................ 1
`III. SUMMARY OF OPINIONS ........................................................................... 4
`IV. TECHNOLOGICAL BACKGROUND .......................................................... 5
`1.
`Traditional “2d” Circuits ............................................................. 5
`2.
`Development of “3D” Circuits.................................................. 20
`LEVEL OF ORDINARY SKILL IN THE ART ........................................... 41
`V.
`VI. THE ’581 PATENT ....................................................................................... 42
`A.
`Summary of the ’581 Patent ................................................................ 42
`B.
`Claim Construction ............................................................................. 49
`1.
`“substantially flexible monocrystalline semiconductor
`substrate” (claims 36, 54, 78, 116, and 136) ............................. 49
`VII. THE PRIOR ART TEACHES OR SUGGESTS EVERY FEATURE
`OF THE CHALLENGED CLAIMS OF THE ’581 PATENT ..................... 51
`A. Overview of the Prior Art References and Reasons to Combine ........ 51
`1.
`U.S. Patent No. 5,627,106 (“Hsu”) (Ex. 1008) ......................... 51
`2.
`U.S. Patent No. 4,701,843 (“Cohen”) (Ex. 1092) ..................... 60
`3.
`U.S. Patent No. 5,354,695 (“Leedy ’695”) (Ex. 1006) ............. 72
`4.
`U.S. Patent 5,502,333 (“Bertin ’333”) (Ex. 1010) .................... 83
`B. Hsu and Cohen Teach or Suggest Every Feature of Claims 1and
`5 ........................................................................................................... 88
`1.
`Claim 1 ...................................................................................... 89
`2.
`Claim 5 ...................................................................................... 98
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`C. Hsu, Cohen, and Leedy ’695 Teach or Suggest Every Feature of
`Claims 12, 36, 54, and 78 ..................................................................101
`1.
`Claim 12 ..................................................................................101
`2.
`Claim 36 ..................................................................................108
`3.
`Claim 54 ..................................................................................114
`4.
`Claim 78 ..................................................................................116
`D. Hsu, Cohen, and Bertin ’333 Teach or Suggest Every Feature of
`Claims 113 and 133 ...........................................................................119
`1.
`Claim 113 ................................................................................119
`2.
`Claim 133 ................................................................................121
`Hsu, Cohen, Bertin ’333 , and Leedy ’695 Teach or Suggest
`Every Feature of Claims 116 and 136 ...............................................124
`VIII. CONCLUSION ............................................................................................125
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`E.
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`I, Paul D. Franzon, declare as follows:
`
`I.
`
`INTRODUCTION
`1.
`I have been retained by Samsung Electronics Co., Ltd. (“Petitioner”)
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`as an independent expert consultant in this proceeding before the United States
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`Patent and Trademark Office (“PTO”).
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`2.
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`I have been asked to consider whether certain references teach or
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`suggest the features recited in claims 1, 5, 12, 36, 54, 78, 113, 116, 133, and 136 of
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`U.S. Patent No. 8,791,581 (“the ’581 patent”) (Ex. 1001), which I understand is
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`allegedly owned by Elm 3DS Innovations, LLC (“Patent Owner”). My opinions
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`and the bases for my opinions are set forth below.
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`3.
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`I am being compensated at my ordinary and customary consulting rate
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`for my work.
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`4. My compensation is in no way contingent on the nature of my
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`findings, the presentation of my findings in testimony, or the outcome of this or
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`any other proceeding. I have no other interest in this proceeding.
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`II. QUALIFICATIONS
`5.
`I am currently the Cirrus Logic Distinguished Professor in the
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`Department of Electrical and Computer Engineering at North Carolina State
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`University (“NCSU”) in Raleigh, North Carolina. I have been affiliated with
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`NCSU in various roles since 1989.
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`I obtained my Ph.D in Electrical and Electronic Engineering in 1989
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`6.
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`from the University of Adelaide in Australia. I obtained two additional degrees
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`from the University of Adelaide, a Bachelor of Engineering in Electrical and
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`Electronic Engineering (1984) and a Bachelor of Science in Physics and
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`Mathematics (1983).
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`7.
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`I have well over twenty years of experience with 3D circuits,
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`applications, analysis, and fabrication. “3D” refers to stacking of chips or circuits,
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`interconnecting and bonding multiple circuit layers (e.g., with through-silicon vias
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`(“TSVs”)), and the packaging of these chips. My experience in 3D circuits began
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`in the 1980s when I began publishing on Wafer Scale Integration and other related
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`topics.
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`8.
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`I have been involved in 3D memory stacks in various projects,
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`including early projects with MCNC, my work for Rambus where I am a named
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`inventor on certain Rambus memory patents, and current work with the Air Force
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`Research Labs, Tezzaron, and Intel.
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`9.
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`I have worked on several other projects in and regarding 3D
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`integration, including design and submission projects for fabrication of 3D logic
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`structures, as funded by DARPA, Google, and Intel, as well as 3D thermal
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`analysis, as funded by Qualcomm.
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`10. While a professor at NCSU, I have built and developed processes for
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`integrating 3D chip stacks using contactless signaling. I am currently the principal
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`investigator of a project conducting detailed stress and thermal analysis of a 3D
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`heterogeneous chip stack. Other projects of mine in this area include exploring
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`advantages specific to 3D in computing, signal processing and other areas, as well
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`as putting together Computer Aided Design flows to support 3D design.
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`11. While Vice President of Engineering for Lightspin, I led a group that
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`put together fabrication recipes for, and fabricated and tested a series of Gallium
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`Arsenide based Light Emitting Diodes and Heterojunction Bipolar Transistors.
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`These were built largely in the Nanofabrication Facility at NCSU. While a
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`professor at NCSU, my group has put together fabrication recipes for, and
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`fabricated and tested a number of micromachined structures for various
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`applications as well as a new memory device. These were built largely in the
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`Nanofabrication Facility at NCSU.
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`12.
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`I have also authored nearly 300 peer-reviewed articles, chapters,
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`textbooks, and other publications relating primarily to electrical engineering and
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`VLSI design, including numerous publications directed to 3D chip stack
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`technologies and applications. I have authored and/or edited three books, including
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`two concerning multichip modules and packages in 1993 and 1996. I co-authored
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`an article entitled “A Review of 3-D Packaging Technology,” where I reviewed the
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`state-of-the-art in three dimensional (“3-D”) packaging technology for VLSI
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`applications that existed by 1997. I also reviewed various vertical interconnect
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`techniques that existed at the time that were used for 3D stacking of integrated
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`circuits. This article was ultimately published in the IEEE Transactions on
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`Components, Packaging and Manufacturing Technology in February 1998.
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`13.
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`I have been awarded sixty research grants and contracts, one
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`equipment grant, one educational grant, and seven cash gifts which total over $41
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`million.
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`14. Additional qualifications are detailed in my curriculum vitae, which I
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`understand has been submitted as Exhibit 1003 in this proceeding.
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`III. SUMMARY OF OPINIONS
`15.
`In preparing this declaration, I have reviewed the documents
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`identified in Appendix A and other materials referred to herein. In addition to these
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`materials, I have relied on my education, experience, and my knowledge of
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`practices and principles in the relevant field, e.g., semiconductor processing. My
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`opinions have also been guided by my appreciation of how one of ordinary skill in
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`the art would have understood the claims and specification of the ’581 patent
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`around the time of the alleged invention, which I have been asked to assume is the
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`earliest claimed priority date of April 4, 1997.
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`16. Based on my experience and expertise, it is my opinion that certain
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`references teach or suggest all the features recited in claims 1, 5, 12, 36, 54, 78,
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`113, 116, 133, and 136 of the ’581 patent, as explained in detail below.
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`IV. TECHNOLOGICAL BACKGROUND
`1.
` Traditional “2d” Circuits
`17. An integrated circuit (“IC”) is electronic circuitry typically fabricated
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`on a thin slice of silicon called a wafer and then is “singulated” or cut into
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`individual devices known as a die or dice. A basic two-dimensional (“2D”) IC is a
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`standard IC with a single, active circuit layer where a die or dice are mounted in a
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`package in a single plane. 2D ICs are the most common form of IC and have
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`existed since the creation of the IC in 1958. Within each die, a 2D IC has a wafer
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`as a base level, typically made of silicon, with various other materials implanted
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`within and/or deposited on top of the wafer. For example, 2D IC’s have metal
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`wiring that forms the connections for the transistors of the IC. This is commonly
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`referred to as a conductive and/or metal layer or level. 2D ICs also have one or
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`more “thin films” of non-metal materials ranging from a few nanometers to several
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`micrometers (commonly referred to as micron(s) and/or the symbol µm) thick that
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`are grown or deposited on an IC. Ex. 1040 at 109-10. One common “thin film”
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`used in IC design is a dielectric film. The basic function of a dielectric is as an
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`electrical insulator. Dielectrics provide crucial functions in integrated circuits most
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`commonly to isolate various components in an IC chip from the substrate and from
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`each other, such as isolating the metal layer from other elements on the IC.
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`18. Silicon wafers are cut from a grown crystalline ingot. By far the
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`majority of silicon wafers used to make integrated circuits, such as DRAMs,
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`SRAMs, EPROMS, analog, and logic are made from single crystal wafers, that is,
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`wafers grown to have a uniform single crystal lattice. The alternative is a
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`polycrystalline wafer, which does not have a single uniform crystal lattice. Ex.
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`1040, Ch. 1. Though Wolf does not use the term “monocrystalline,” a practitioner
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`of the art would have used that term interchangeably with “single crystal,” “mono”
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`meaning “single” in this context. Wolf states, “[i]f the [crystal] periodic
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`arrangement exists throughout the entire solid, the substance is defined as being
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`formed of a single crystal. If the solid is composed of a myriad of small single
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`crystal regions the solid is referred to as polycrystalline material.” Id. at 1-2. Wolf
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`goes on, “The fabrication of VLSI takes place on silicon substrates possessing very
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`high crystalline perfection. G.K. Teal originally recognized the critical importance
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`of utilizing single crystal material for the transistor regions of microelectronic
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`circuits. He reasoned that polycrystalline material would exhibit inadequately
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`short minority carrier lifetimes.” Id. at 5.
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`19. Terms like “top,” “bottom,” “front,” “back,” and “face,” often with
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`the addendum “side,” are typically used to refer to a particular side of a wafer or
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`substrate. In the field, “top,” “front,” and “face” generally refer to the side of the
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`silicon wafer on which the transistors and metal layers are built, while “back” and
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`“bottom” are the opposing side.
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`20. Since the creation of the IC in 1958, the microelectronics industry has
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`worked to improve computing power and efficiency of electronic structures. This
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`constant drive to improve IC’s was so predictable that, in 1965, Gordon Moore
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`coined “Moore’s law,” which states that the number of transistors on an IC would
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`double approximately every year (later revised in 1975 to every two years). This
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`“law” has been the most powerful driver for the development of the
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`microelectronics industry in the past 50 years. Higher computing power has been
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`achieved primarily through scaling down device dimensions (such as individual
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`transistors) to include more transistors in a semiconductor device. Semiconductor
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`devices are made in wafer form, and then singulated to create individual die. Due
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`to the desire for high yield (the percentage of the die that functions correctly), these
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`die, or chips, are relatively small. These size limits in turn limit the amount of
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`connectivity between chips, especially as off-chip connection bandwidth does not
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`scale with Moore’s Law. Among the issues that 2D IC designers faced that are
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`relevant to the patent at issue in this matter are thinning and polishing of the
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`substrate, increasing off-chip connection bandwidth and material stress
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`management to address, for example, IC warping and cracking.
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`a)
`Thinning and Polishing
`21. Since the early days of IC mass fabrication in the 1960s, IC designers
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`have thinned and polished substrates to create thin electronic circuits that could fit
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`in ever-smaller commercial devices. See, e.g., Ex. 1041. In IC fabrication,
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`typically, a large, single crystal of silicon is shaped into a solid cylinder (known as
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`ingots), and then sliced into thin discs called wafers. The resulting wafer is
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`processed so that thin chips could be implemented in microelectronics. Thinning
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`has traditionally been performed by backside grinding and polishing of the silicon
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`wafer. Rather than leave a rough, unfinished surface after grinding, it was a
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`common practice to polish the ground substrate to reduce surface roughness. See,
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`e.g., Ex. 1040 at xxiii, 6, 24. A polished surface was desired due to a known
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`correlation between wafer back surface roughness and the resistance to stress
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`induced failures. Ex. 1016. In some cases, grinding removed much more substrate
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`whereas polishing was used as a final step to reach a desired thickness. For
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`example, Motorola’s U.S. Patent No. 3,508,980 discusses a common practice of
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`backside thinning of a silicon substrate and polishing to reach desired and uniform
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`thickness. Ex. 1041 at 1:19-31, 2:8-10, 3:33-35.
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`b)
`Through Silicon Vias
`22. The microelectronics industry has, since nearly the inception of the
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`IC, also implemented vertical interconnections to connect different surfaces of an
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`IC. In 1958, Nobel Laureate William Shockley, the co-inventor of the transistor,
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`invented the first of what is now known as a through silicon via (“TSV”). In U.S.
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`Patent NNo. 3,044,9909, Mr. S
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`used as a TSV:
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`hockley deescribed annd depictedd holes thaat could be
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`(annotatio
`Ex. 10442 at Fig 4
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`n added). Accordingg to Mr. Shhockley, thhese “holess”
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`would aallow electrical conneection throough the waafer to varrious layerss within th
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`IC. Id. at 2:27-499.
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`c)
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`ress Manaagement
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`223. As thhe microeleectronics inndustry creeated moree powerful
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`and efficieent
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`2D ICs,, the industtry was alsso concerneed with immproving thhe reliabilitty of the ICCs.
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`For semmiconductoor fabricatoors, one important meeasuremennt of successs is
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`commonnly referreed to as thee “yield,” wwhich is thee proportioon of semicconductor
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`devices on a wafer that funcction propeerly. The ggreater the
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`yield, the mmore
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`semiconnductor devvices a maanufacturerr can sell.
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`fabricattion of siliccon ICs, hoowever, immpose stres
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`Many of thhe processses used in
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`licon substtrate whichh
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`may ultimately affffect the yieeld. Conseequently, sstress has aalways beenn a concerrn of
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`In the context of semiconductors, stress (σ) is the force per unit area
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`24.
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`that is acting on a surface of a solid. It is usually expressed in terms of Mega
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`Pascals (“MPa”) or dynes/cm2. 50 MPa is the equivalent of 5x108 dynes / cm2.1
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`Stress can be classified in two groups: extrinsic and intrinsic. Extrinsic stress is
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`caused by the different coefficients of thermal expansion of the different materials
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`that are added as films go into making an integrated circuit. Generally these
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`materials are not deposited at room temperature. As the wafer cools after adding a
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`new material, the different materials contract at different rates, causing stress.
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`Intrinsic stress depends on a number of factors such as deposition rate, deposition
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`temperature, pressure in the deposition chamber, incorporation of impurities during
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`growth, grain structure, and fabrication process defects.
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`25. Stress also can be uniform or non-uniform throughout a thin film. If
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`the stress is uniform, its measurement will give an average stress. If the stress is
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`non-uniform, a difference of stress or stress gradient exists between the top and
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`the bottom of the thin film, as well as different stress at different locations from the
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`center of the film outward to the edges. There is a vertical and lateral variation of
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`stress. Consequently, just indicating that a film is “low stress” or “low tensile
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`stress” does not provide enough context to one of skill in the art because the phrase
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`alone does not indicate whether extrinsic or intrinsic stress, average stress
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`1 This is the relevant stress level mentioned in the patent at issue.
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`measureement, or tthe measurrement poinnt along thhe film is inndicated. FFor net str
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`each inddividual fillm contribuutes stress,, either possitive (tenssile) or neggative
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`(compreessive). Thherefore, thhe net stresss is the suum of the inndividual IIC films
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`contribuutions since each are additive.
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`226. A filmm under sttress can exxpand or coontract by
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`bending inn a verticall
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`direction. Accordiing to the WWolf Textbbook:
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`Nearly all ffilms are foound to be in a state oof internal
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`stress, reggardless
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`of the meanns by whichh they have been prooduced. Thhe stress mmay be
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`ompressivee or tensilee. Compreessively strressed filmms would likke to
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`xxpand paraallel to the substrate surface, annd in the exxtreme, filmms in
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`ompressive stress wiill buckle uup on the suubstrate, aas shown inn Fig. 4.
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`Films in tennsile stresss, on the othher hand, wwould likee to contracct
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`parallel to tthe substratte, and may crack if ttheir elastiic limits arre
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`Ex. 10440 at 114 (eemphasis inn original)). In other
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`that is inn tension, mmeaning thhat it pulls
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`“Compresssive” sugggests a filmm
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`that is inn compression, meanning that it pushes inwward. Thee Wolf Texxtbook furtther
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`providees a graphiccal depictioon of the eeffects tenssile and commpressive
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`have onn a substratte after thinn film depoosition:
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`stresses mmay
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`DDeclarationn of Dr. Pauul D. Fran
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`Inter PPartes Revview of U.
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`S. Patent NNo. 8,791,5581
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`Id. at 1117.
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`227. As deepicted in tthe image above fromm the Wolff Textbookk, given
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`enough stress, a siilicon subsstrate will bbend and ppossibly geenerate disllocations.
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`Other p
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`otential meechanical sstress relatted issues iinclude waafer crackinng, metal
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`voidingg, fracture aand delamiination of ffilms, and
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`arise durinng the fabrrication
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`processes. Some examples aare the usee of materiaals with a ccoefficientt of thermaal
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`1043 at 1558 (discuss
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`expansiion (“CTE””) “differennt from thaat of siliconn, depositiion of film
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`intrinsicc stress, annd oxidation of nonpllanar surfacces.” Ex.
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`228. One oof the firstt compreheensive revie
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`of thin ffilms was ppublished bby R. W. HHoffman inn 1966. Seee Ex. 10444. This
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`publicattion contaiins a sectioon on the inntrinsic strresses in evvaporated ffilms. Id. aat
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`219-53. Mr. Hofffman’s dataa showed tthat metal ffilms prodduced by evvaporation
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`dominannt technoloogy at the ttime) weree generallyy in tensionn, whereas
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`229. Moreeover, since the beginnning of seemiconducctor wafer ffabricationn,
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`semiconnductor maanufacturerrs have exaamined strress managgement to rreduce the
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`potentiaal of mechaanical stresss induced problems.. Specificaally, by 19
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`79, the
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`industry had already examined mechanical stresses that occurred as a result of the
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`deposition in thin films on semiconductor substrates. In one article, it was
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`disclosed that “The mechanical properties of materials used in Si [silicon] device
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`processing, such as Si, thermal SiO2 [silicon dioxide], and deposited SiO2 and
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`Si3N4 [silicon nitride], are rapidly becoming limiting factors in advanced
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`integrated-circuit technology.” Ex. 1045 at 8. In particular, Mr. EerNisse
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`observed that “high-temperature dislocation” occurred between silicon and
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`deposited films such as silicon dioxide and silicon nitride and “lead to yield
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`problems as device packing density increases. Mechanical stress-induced cracking
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`in Si3N4/SiO2 masking layers at discontinuities degrades yield.” Id. Mr. EerNisse
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`also recognized that stress free and/or “small tensile stresses” could be created in
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`SiO2 films by growing such films at high temperature. Id. Mr. EerNisse disclosed
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`that “[n]o stress is observed at 975 and 1000o C with possible small tensile stresses
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`seen above 1000o C.” Id. at 10 (emphasis added). He then concluded that his
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`“results, which treat the stresses during growth at the growth temperature, should
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`be of value in avoiding mechanical damage effects in VLSI or VHSI technologies
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`by careful choice of SiO2 growth temperatures.” Id.
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`30. By 1987, several industry members recognized the mechanical stress
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`related problems associated with the deposition of thin films on silicon substrates
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`and recommended controlling stress to limit stress related failures in
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`13
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`semiconductor manufacturing. One approach was the use of films with
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`intrinsically low stress. For example, in the Wolf Textbook, it was suggested that
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`the use of high stressed films would be disadvantageous for various reasons:
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`In general, the stresses in thin films are in the range of 108-5 x 1010
`dynes/cm2. Highly stressed films are generally undesirable for
`VLSI applications for several reasons, including: a) they are more
`likely to exhibit poor adhesion; b) they are more susceptible to
`corrosion; c) brittle films, such as inorganic dielectrics, may undergo
`cracking in tensile stress; and d) the resistivity of stressed metallic
`films is higher than that of their annealed counterparts.
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`Ex. 1040 at 115 (emphasis added). By providing a range of stresses and
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`recommending avoiding “highly stressed films,” the Wolf Textbook taught the use
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`of low stress films closer to the base of the given range which he identified as
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`1x108 dynes/cm2.
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`31.
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`Industry participants also recognized the disadvantages of using
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`intrinsically high stressed films. In September 1987, IBM published an article that
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`recognized that “[t]he fracture and delamination of thin films is a relatively
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`common occurrence, and prevention of these mechanical failures is essential for
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`the successful manufacture of thin-film devices.” Ex. 1046 at 585. IBM noted the
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`source of mechanical stress related issues was the use of thin films with an intrinsic
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`stress above 109 dynes/cm2:
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`[S]tress present in thin films is an inherent part of the deposition
`process, and can be either tensile or compressive. The sign and
`magnitude of film stress are for the most part determined by the
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`14
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`deposition parameters, i.e., substrate temperature, kind of substrate,
`deposition rate, and method of deposition. Stresses of about 109 - 1010
`dynes/cm2 are often observed, and it has been commonly found that
`these stresses cause film fracture, delamination, and occasionally
`substrate fracture.
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`Id. (emphasis added). IBM concluded that “[t]o avoid catastrophic film failure
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`[stress and film thickness] must be reduced in some manner.” Id. at 590. To deal
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`with these issues in memory devices in particular, another IBM article recognized
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`that “[t]wo general approaches can be followed to eliminate dislocation generation
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`in DRAM cells: Reduce the amount of stress in the substrate or eliminate the
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`source of nucleation for dislocations.” Ex. 1043 at 178.
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`32. By 1990, the prior art taught that the way to avoid mechanical stress
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`related issues due to high stress films placed directly on the substrate was to use
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`low-tensile stress dielectrics. For example, U.S. Patent No. 4,948,482 proposed a
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`method for forming a silicon nitride film for use in “semiconductor chips or
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`memory disks and an X-ray transmission film.” Ex. 1047 at 1:7-10. In particular,
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`Kobayashi found that depositing a 2μm thick silicon nitride film on a silicon
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`substrate where “sputtering gas pressure = 0.5 Pa, the internal stress can be
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`controlled at 5x108 dyn/cm2 or less in terms of a tensile stress over a wide
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`substrate temperature range of 200-290o C….” Id. at 4:18-21 (emphasis added).
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`33. Likewise, NEC published a paper in 1990 where the authors posited
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`that “the dielectrics deposition temperature induced stress, caused by the difference
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`DDeclarationn of Dr. Pauul D. Fran
`zon
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`Inter PPartes Revview of U.
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`S. Patent NNo. 8,791,5581
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`of the exxpansion ccoefficientss to Al [aluuminum], iis the mainn factor forr [stress-
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`migratioon].” Ex. 1048 at 363. Thus, NNEC conclluded the ““best way oof dielectriics
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`formatioon against [stress-migration] is, ‘depositinng low Al
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`diffusivityy dielectriccs at
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`low temmperature aafter stress [sic] reluxxation.” Idd. As part oof its expe
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`showedd that usingg a spin-on polyimidee layer of 00.5 μm thicckness wouuld result i
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`low tensile stress of 50 MPaa (5x108 dyyne/cm2) wwith zero faailures in thhe film as
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`depictedd below:
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`Id. at 3664 (annotattion addedd).
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`34. The pprior art also discloseed how IC
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`depositiion of low stress filmms by changging the chharacteristiic of the inntrinsic streess
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`of a filmm from eithher “tensilee” to “commpressive” oor vice verrsa. Novelllus, a
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`promineent semicoonductor mmanufacturiing equipmment makerr, touted thhe use of DDual
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`16
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`DDeclarationn of Dr. Pauul D. Fran
`zon
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`Inter PPartes Revview of U.
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`S. Patent NNo. 8,791,5581
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`frequenncy Plasmaa Enhancedd Chemicall Vapor Deeposition (““PECVD””) to “contrrol
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`the filmm stress” in order to reeduce “streess crackinng, stress innduced meetal
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`voidingg….” Ex. 11049 at 1944, 196. Noovellus statted that Duual Frequenncy PECVVD
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`could caause “a chaange in thee intrinsic ffilm from ttensile to ccompressivve and
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`increasee[] the filmm density.” Id. at 1966. As showwn in Figurre 3, the chhange is
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`gradual and easy tto control.””
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`d). tion addedId. at 1996 (annotat
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`35. As mmultiple filmms, metal llayers, andd other matterials weree placed onn
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`top of thhe substratte in a 2D IIC, the prioor art discllosed that bbalancing tthe stress oof
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`these mmaterials waas necessarry to solve mechanic
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`al stress isssues such
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`as stress
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`migratioon, crackinng, delaminnation, andd other streess inducedd failures.
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`At the timme,
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`17
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`Declaration of Dr. Paul D. Franzon
`Inter Partes Review of U.S. Patent No. 8,791,581
`the prior art was recommending low stress materials, it also disclosed stress
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`balancing. For example, Fujitsu’s U.S. Patent No. 5,160,998 disclosed stress
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`balancing by using differing layers of dielectric material with tensile and
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`compressive intrinsic stresses:
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`[A]ccording to one aspect of the present invention, there is provided a
`semiconductor device comprising a semiconductor substrate; a metal
`wiring layer formed on the semiconductor substrate; a first insulation
`layer formed on the metal wiring layer, the first insulation layer being
`formed by a tensile stress insulation layer having a contracting
`characteristic relative to the substrate; and a second insulation layer
`formed on the first insulation layer, the second insulation layer being
`formed by a compressive stress insulation layer having an expanding
`characteristic relative to the substrate.
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`Ex. 1050 at 1:35-46. By stress balancing, Fujitsu found that:
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`[A]s show in the experimental data described in detail below, a
`semiconductor device according to the present invention (i.e., a
`semiconductor device comprising a tensile stress insulation layer
`formed on the metal layer and a compressive stress insulation layer
`formed on the tensile stress insulation layer) effectively prevents both
`a disconnection of the metal layers due to stress migration and a
`generation of cracks in the insulation layers . . . .
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`Id. at 3:9-17. The Fujitsu patent did not require alternating tensile and compressive
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`dielectrics to eliminate cracking. It showed that various numbers of such layers
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`could be used so long as the stress was balanced:
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`18
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`DDeclarationn of Dr. Pauul D. Fran
`zon
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`Inter PPartes Revview of U.
`
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`S. Patent NNo. 8,791,5581
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`Id. at Fiig.10 (annootation addded). This figure shoows Fujitsuu’s experimmental dataa
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