UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`LG ELECTRONICS, INC.
`Petitioner
`
`v.
`
`ATI TECHNOLOGIES ULC
`Patent Owner
`____________
`
`Case No.: IPR2017-01225
`Patent 8,760,454
`____________
`
`Declaration of Dr. Nader Bagherzadeh
`
`723453262
`
`LG Ex. 1005, pg 1
`
`LG Ex. 1005
`LG v. ATI
`IPR2017-01225
`
`

`

`TABLE OF CONTENTS
`
`Page
`
`I.
`
`II.
`
`III.
`IV.
`
`V.
`
`VI.
`
`INTRODUCTION ..........................................................................................1
`A.
`Engagement..........................................................................................1
`B.
`Background and Qualifications............................................................1
`C.
`Compensation and Prior Testimony.....................................................3
`D. Materials Considered............................................................................3
`LEGAL UNDERSTANDINGS......................................................................4
`A.
`Person of Ordinary Skill in the Art ......................................................4
`B.
`Anticipation..........................................................................................4
`C.
`Obviousness..........................................................................................5
`TECHNOLOGY BACKGROUND................................................................8
`THE ’454 PATENT......................................................................................13
`A.
`Prosecution of the ’454 Patent ...........................................................13
`B.
`Person of Ordinary Skill in the Art ....................................................16
`C.
`Overview of the ’454 Patent...............................................................17
`GENERAL ISSUES .....................................................................................19
`A.
`Claims of the ’454 Patent That I Am Addressing..............................19
`B.
`Interpretation of Certain Claim Terms...............................................21
`C.
`Prior Art References...........................................................................21
`1.
`Ex. 1003 - U.S. Patent 7,038,685 to Lindholm et al................22
`2.
`Ex. 1004 – WO 00/62182 to Stuttard et al...............................22
`3.
`Ex. 1009 / Ex. 1010 – OpenGL Graphics System: A
`Specification, Version 1.4, and OpenGL Overview................23
`PATENTABILITY ANALYSIS ..................................................................26
`A.
`Summary of Opinions ........................................................................26
`B.
`Lindholm as Primary Reference.........................................................27
`1.
`Brief Overview of Lindholm ...................................................27
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`LG Ex. 1005, pg 2
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`

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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`2.
`
`(iii)
`
`(iv)
`
`Ground 1: Lindholm Anticipates Claims 2-11. .......................32
`a.
`Lindholm Discloses Claim 2. ........................................32
`(i)
`“A unified shader”...............................................32
`(ii)
`“a general purpose register block for
`maintaining data” ................................................35
`“a processor unit … wherein the processor
`unit executes instructions that generate a
`pixel color in response to selected data from
`the general purpose register block and
`generates vertex position and appearance
`data in response to selected data from the
`general purpose register block”...........................36
`“a sequencer, coupled to the general purpose
`register block and the processor unit, the
`sequencer maintaining instructions operative
`to cause the processor unit to execute vertex
`calculation and pixel calculation operations
`on selected data maintained in the general
`purpose register block”........................................40
`Lindholm Discloses Claim 3. ........................................45
`(i)
`“A unified shader”...............................................45
`(ii)
`“a processor unit operative to perform vertex
`calculation operations and pixel calculation
`operations”...........................................................46
`“shared resources, operatively coupled to the
`processor unit”.....................................................49
`
`b.
`
`(iii)
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`LG Ex. 1005, pg 3
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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`(iv)
`
`(iii)
`
`(iv)
`
`“the processor unit operative to use the
`shared resources for either vertex data or
`pixel information and operative to perform
`pixel calculation operations until enough
`shared resources become available and then
`use the shared resources to perform vertex
`calculation operations”........................................51
`Lindholm Discloses Claim 4. ........................................56
`(i)
`“A unified shader”...............................................56
`(ii)
`“a processor unit operative to perform vertex
`calculation operations and pixel calculation
`operations”...........................................................57
`“shared resources, operatively coupled to the
`processor unit”.....................................................57
`“the processor unit operative to use the
`shared resources for either vertex data or
`pixel information and operative to perform
`vertex calculation operations until enough
`shared resources become available and then
`use the shared resources to perform pixel
`calculation operations”........................................57
`Lindholm Discloses Claim 5. ........................................62
`(i)
`“A unified shader”...............................................63
`(ii)
`“a processor unit” ................................................63
`(iii)
`“a sequencer, coupled to the processor unit,
`the sequencer maintaining instructions
`operative to cause the processor unit to
`execute vertex calculation and pixel
`calculation operations on selected data
`maintained in a store depending upon an
`amount of space available in the store”...............63
`
`c.
`
`d.
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`LG Ex. 1005, pg 4
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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`e.
`f.
`g.
`h.
`i.
`j.
`
`(iii)
`(iv)
`
`Lindholm Discloses Claim 6. ........................................69
`Lindholm Discloses Claim 7. ........................................71
`Lindholm Discloses Claim 8. ........................................72
`Lindholm Discloses Claim 9. ........................................74
`Lindholm Discloses Claim 10. ......................................76
`Lindholm Discloses Claim 11. ......................................77
`(i)
`“A unified shader”...............................................77
`(ii)
`“a processor unit flexibly controlled to
`perform vertex manipulation operations and
`pixel manipulation operations based on
`vertex or pixel workload”....................................78
`“an instruction store”...........................................78
`“wherein the processor unit of the unified
`shader performs the vertex manipulation
`operations and pixel manipulation
`operations at various degrees of completion
`based on switching between instructions in
`the instruction store” ...........................................78
`Ground 2: Lindholm, Alone or in Combination with
`OpenGL, Renders Claims 2-11 Obvious. ................................82
`a.
`Claims 2, 8, and 9 In View of Lindholm Alone............83
`b.
`Claim 2, 8, and 9 in View of Lindholm and
`OpenGL v1.4 .................................................................84
`Claims 3-10 in View of Lindholm Alone......................90
`c.
`Stuttard as Primary Reference............................................................91
`1.
`Brief Overview of Stuttard.......................................................91
`2.
`Ground 3: Stuttard Anticipates Claims 2 and 11.....................94
`a.
`Stuttard Discloses Claim 2. ...........................................94
`
`3.
`
`C.
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`LG Ex. 1005, pg 5
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`

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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`(i)
`(ii)
`
`(iii)
`
`(iv)
`
`(iii)
`(iv)
`
`“A unified shader”...............................................95
`“general purpose register block for maintain
`data”.....................................................................96
`“a processor unit … wherein the processor
`unit executes instructions that generate a
`pixel color in response to selected data from
`the general purpose register block and
`generates vertex position and appearance
`data in response to selected data from the
`general purpose register block”...........................98
`“a sequencer, coupled to the general purpose
`register block and the processor unit, the
`sequencer maintaining instructions operative
`to cause the processor unit to execute vertex
`calculation and pixel calculation operations
`on selected data maintained in the general
`purpose register block”......................................100
`Stuttard Discloses Claim 11. .......................................107
`(i)
`“A unified shader”.............................................107
`(ii)
`“a processor unit flexibly controlled to
`perform vertex manipulation operations and
`pixel manipulation operations based on
`vertex or pixel workload”..................................107
`“an instruction store”.........................................108
`“wherein the processor unit of the unified
`shader performs the vertex manipulation
`operations and pixel manipulation
`operations at various degrees of completion
`based on switching between instructions in
`the instruction store” .........................................109
`Ground 4: Stuttard Renders Claims 2 and 11 Obvious..........114
`
`b.
`
`3.
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`LG Ex. 1005, pg 6
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`

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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`4.
`
`(iii)
`
`(iv)
`
`(iii)
`
`(iv)
`
`Ground 4: Stuttard Renders Obvious Claims 3-10................116
`a.
`Stuttard Teaches Claim 3.............................................116
`(i)
`“A unified shader”.............................................117
`(ii)
`“a processor unit operative to perform vertex
`calculation operations and pixel calculation
`operations”.........................................................117
`“shared resources, operatively coupled to the
`processor unit”...................................................117
`“the processor unit operative to use the
`shared resources for either vertex data or
`pixel information and operative to perform
`pixel calculation operations until enough
`shared resources become available and then
`use the shared resources to perform vertex
`calculation operations”......................................118
`Stuttard Teaches Claim 4.............................................124
`(i)
`“A unified shader”.............................................124
`(ii)
`“a processor unit operative to perform vertex
`calculation operations and pixel calculation
`operations”.........................................................125
`“shared resources, operatively coupled to the
`processor unit”...................................................125
`“the processor unit operative to use the
`shared resources for either vertex data or
`pixel information and operative to perform
`vertex calculation operations until enough
`shared resources become available and then
`use the shared resources to perform
`pixelcalculation operations”..............................125
`Stuttard Teaches Claim 5.............................................130
`(i)
`“A unified shader”.............................................130
`
`b.
`
`c.
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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`(ii)
`
`(iii)
`
`“a processor unit operative to perform vertex
`calculation operations and pixel calculation
`operations”.........................................................130
`“a sequencer coupled to the processor unit,
`the sequencer maintaining instructions
`operative to cause the processor unit to
`execute vertex calculation and pixel
`calculation operations on selected data
`maintained in a store depending upon an
`amount of space available in the store”.............131
`Stuttard Teaches Claim 6.............................................135
`d.
`Stuttard Discloses Claim 7. .........................................137
`e.
`Stuttard Teaches Claim 8.............................................139
`f.
`Stuttard Teaches Claim 9.............................................140
`g.
`Stuttard Teaches Claim 10...........................................141
`h.
`VII. SUPPLEMENTATION ..............................................................................144
`APPENDIX A ...........................................................................................................2
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`LG Ex. 1005, pg 8
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`

`

`I.
`
`INTRODUCTION
`
`A.
`
`Engagement
`
`1. My name is Nader Bagherzadeh, Ph.D., and I have been retained by
`
`the law firm of Mayer Brown LLP on behalf of LG ELECTRONICS, INC.; LG
`
`ELECTRONICS U.S.A., INC.; and LG ELECTRONICS MOBILECOMM U.S.A.
`
`INC. as an expert in the relevant art.
`
`2.
`
`I have been asked to provide my opinions and views on the materials I
`
`have reviewed in this case related to U.S. Patent No. 8,760,454 (“the ’454 patent”)
`
`(Ex. 1001), and the scientific and technical knowledge regarding the same subject
`
`matter before and for a period following the date of the first application for the
`
`patent-at-issue was filed.
`
`B.
`
`Background and Qualifications
`
`3.
`
`I am a Professor in the Department of Electrical Engineering and
`
`Computer Science at the University of California at Irvine in Irvine, California. My
`
`curriculum vitae is attached as Exhibit 1008.
`
`4.
`
`I received my B.S. in Electrical Engineering with honors in 1977, my
`
`Masters in Electrical Engineering in 1979, and my Ph.D. in Computer Engineering
`
`in 1987, all from the University of Texas at Austin, in Austin, Texas.
`
`5.
`
`From 1980 to 1984, I was a member of the technical staff at AT&T
`
`Bell Laboratories in Holmdel, New Jersey. My work at AT&T Bell Labs involved
`
`hardware and software design of a T1 line circuit board called Digital Facility
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`LG Ex. 1005, pg 9
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`

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`Interface (DFI), as part of the #5 ESS project, the first fully digital telephone
`
`transmission and switching system in the world.
`
`6.
`
`I joined the University of California at Irvine as an Assistant Professor
`
`in 1987, and I have been a Full Professor since 1998. From 1998 to 2002, I was the
`
`Chair of the Electrical/Computer Engineering and Electrical
`
`Engineering/Computer Science Department. I became an IEEE Fellow in 2014 for
`
`my work on reconfigurable computing for System-on-Chip (“SoC”).
`
`7.
`
`In the past, as part of my university research, I have worked on
`
`microarchitecture optimization techniques by combining superscalar and
`
`multithreading concepts to introduce a new approach for achieving high
`
`performance computing platforms.
`
`8. My current research focuses on development of high performance
`
`SoC using Network-on-Chip (“NoC”) technology for connecting hundreds of IPs
`
`(intellectual property cores) on the same die. Additionally, I am working on
`
`extending our work for 3D SoCs for meeting the power and performance
`
`requirements of the next generation platforms. I have authored several book
`
`chapters, journals, and conference papers on SoC design, including NoC and on-
`
`chip interconnect architectures. Over the past decade, I have worked extensively on
`
`SoC applications, and have personally designed SoCs for smartphone applications
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`for the University of California at Irvine, and MorphoSys Technologies, a start-up
`
`for which I was the Chief Architect.
`
`C.
`
`Compensation and Prior Testimony
`
`9.
`
`I am compensated at the rate of $450 per hour for my work, plus
`
`reimbursement for expenses. My compensation has not influenced any of my
`
`opinions in this matter and does not depend on the outcome of this proceeding or
`
`any issue in it.
`
`10. My prior testimony is listed in my curriculum vitae and attached as
`
`Exhibit 1008.
`
`11. My opinions and underlying reasoning are set forth below.
`
`D. Materials Considered
`
`12.
`
`In forming my opinions for this proceeding, I considered the materials
`
`listed in Appendix A to my declaration, in addition to any materials cited in my
`
`declaration itself. In forming my opinions for this proceeding, I also relied on my
`
`years of experience in the field of electrical engineering, computer science, and
`
`graphics processing. I also relied on the general knowledge that would have been
`
`available to a person of ordinary skill in the art at the relevant timeframe, that is, at
`
`the time ATI allegedly invented the subject matter of the ’454 patent in
`
`approximately.
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`

`

`II.
`
`LEGAL UNDERSTANDINGS
`
`A.
`
`13.
`
`Person of Ordinary Skill in the Art
`
`I have been informed that the claims of a patent are judged from the
`
`perspective of a hypothetical construct involving “a person of ordinary skill in the
`
`art.” The “art” is the field of technology to which the patent is related.
`
`14.
`
`I understand that the purpose of using a person of ordinary skill in the
`
`art’s viewpoint is objectivity. Thus, I understand that the question of validity is
`
`viewed from the perspective of a person of ordinary skill in the art, and not from
`
`the perspective of (a) the inventor, (b) a layperson, or (c) a person of extraordinary
`
`skill in the art.
`
`15.
`
`I have been informed that the claims of the patent-at-issue are
`
`interpreted as a person of ordinary skill in the art would have understood them in
`
`the relevant time period (i.e., when the patent application was filed or earliest
`
`effective filing date).
`
`B.
`
`16.
`
`Anticipation
`
`I understand that the following standards govern the determination of
`
`whether a patent claim is “anticipated” by the prior art. I have applied these
`
`standards in my analysis of whether claims of the ’454 patent were anticipated at
`
`the time of the supposed invention.
`
`17.
`
`I understand that a patent claim is “anticipated” by a single prior art
`
`reference if that reference discloses each element of the claim in a single
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`embodiment. A prior art reference may anticipate a claim inherently if an element
`
`is not expressly stated, if the prior art necessarily includes the claim limitations.
`
`18.
`
`I understand that the test for anticipation is performed in two steps.
`
`First, the claims must be interpreted to determine their meaning. Second, a prior art
`
`reference is analyzed to determine whether every claim element, as interpreted in
`
`the first step, is present in the reference. If all the elements of a patent claim are
`
`present in the prior art reference, then that claim is anticipated and is invalid.
`
`19.
`
`I understand that it is acceptable to examine extrinsic evidence outside
`
`the prior art reference in determining whether a feature, while not expressly
`
`discussed in the reference, is necessarily present within that reference.
`
`C.
`
`20.
`
`Obviousness
`
`I understand that a claim can be invalid in view of prior art if the
`
`differences between the subject matter claimed and the prior art are such that the
`
`claimed subject matter as a whole would have been “obvious” at the time the
`
`invention was made to a person having ordinary skill in the art.
`
`21.
`
`I understand that the obviousness standard is defined at 35 U.S.C. §
`
`103(a). I understand that a claim is obvious over a prior art reference if that
`
`reference, combined with the knowledge of one skilled in the art or other prior art
`
`references, discloses each and every element of the recited claim.
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`22.
`
`I also understand that the relevant inquiry into obviousness requires
`
`consideration of four factors:
`
`a. The scope and content of the prior art;
`
`b. The differences between the prior art and the claims at issue;
`
`c. The knowledge of a person of ordinary skill in the pertinent art;
`
`and
`
`d. Objective factors indicating obviousness or non-obviousness1
`
`may be present in any particular case, such factors including
`
`commercial success of products covered by the patent claims; a
`
`long-felt need for the invention; failed attempts by others to
`
`make the invention; copying of the invention by others in the
`
`field; unexpected results achieved by the invention; praise of
`
`the invention by the infringer or others in the field; the taking of
`
`licenses under the patent by others; expressions of surprise by
`
`experts and those skilled in the art at the making of the
`
`1 I have seen no evidence of secondary considerations that would defeat the
`
`obviousness of these claims. Should Patent Owner offer any evidence of secondary
`
`considerations, I reserve the right to consider this and to supplement my opinions
`
`accordingly.
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`invention; and that the patentee proceeded contrary to the
`
`accepted wisdom of the prior art.
`
`23.
`
`I understand that, when combining two or more references, one should
`
`consider whether a teaching, suggestion, or motivation to combine the references
`
`exists so as to avoid impermissible hindsight. I have been informed that the
`
`application of the teaching, suggestion or motivation test should not be rigidly
`
`applied, but rather is an expansive and flexible test. For example, I have been
`
`informed that the common sense of a person of ordinary skill in the art can serve as
`
`motivation for combining references.
`
`24.
`
`I understand that the content of a patent or other printed publication
`
`should be interpreted the way a person of ordinary skill in the art would have
`
`interpreted the reference as of the effective filing date of the patent application for
`
`the ’454 patent. I have assumed that the person of ordinary skill is a hypothetical
`
`person who is presumed to be aware of all the pertinent information that qualifies
`
`as prior art. In addition, the person of ordinary skill in the art makes inferences and
`
`creative steps. He or she is not an automaton, but has ordinary creativity.
`
`25.
`
`I have been informed that the application that issued as the ’454 patent
`
`claims priority from an application filed in September 2003. As a result, I will
`
`assume the relevant time period for determining what one of ordinary skill in the
`
`art knew is mid-to-late 2003.
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`LG Ex. 1005, pg 15
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`III. TECHNOLOGY BACKGROUND
`
`26.
`
`This proceeding involves graphics processing. Specifically, the
`
`concept of multithreading will feature as background to the discussion here.
`
`27. Multithreading in computer architectures is a performance
`
`improvement technique that dates from the early 1990s. The main goal of
`
`multithreading schemes is to exploit Instruction Level Parallelism (ILP) beyond
`
`what a dynamically scheduled superscalar architecture can achieve by allowing
`
`resources on a processor core to be shared more efficiently among instructions of a
`
`program.
`
`28. A related stream of instructions is called a thread, and a program
`
`usually has many threads if hardware resources are available. Each of the different
`
`threads can perform different tasks or functions of the program. One of the main
`
`advantages of multithreaded architectures is the ability to hide latencies. If, for
`
`some reason, one of the active threads in the processor is stalled, then another
`
`thread that has been tracked by the processor will be allowed to run and use the
`
`otherwise-idle hardware resources. Multithreading improves processor execution
`
`efficiency so that available hardware resources are not idle.
`
`29.
`
`For graphics processing, a typical graphical pipeline has the following
`
`operations:
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`• Geometric Operations: The first step in t h e pipeline is
`generally performed by a vertex processor. The vertex
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`processor is tasked with (a) coordinate transformation from
`vertex to window coordinates and (b) calculating the color
`for each vertex. This step requires matrix operations related
`to transformations and object coordinate processing where, for
`precision and dynamic range requirements,
`floating point
`numbers are utilized for the vertices.
`• Assembly: The next step in the pipeline is generally clipper and
`primitive assembly. This
`stage is tasked with limiting the
`image information processed due to human visual system
`limitations, objects that are occluded, and other
`limiting
`factors. In this stage, the clipping is done on a primitive by
`primitive basis;
`therefore,
`the vertices corresponding to a
`primitive, such as a polygon or triangle must be assembled
`before performing this task.
`the pipeline is tasked with
`• Rasterization: This phase of
`taking clipped primitives and generating the pixels for the
`frame buffer. If certain pixels are within a polygon primitive,
`they should have the color designated for that region. The
`rasterizer generates fragments
`for each primitive, which
`effectively are considered pixels with color and location,
`updating the pixels in the frame buffer.
`• Interpolation and fragment processing: This is the last stage
`of processing where information about 3D objects and what is
`visible,
`texture mapping information and other final stage
`color adjustments are processed. The result of this process
`will finalize the pixel values in the frame buffer.
`
`30. One of the reasons to use multithreaded architectures for graphics
`
`processing is to exploit the data parallelism inherent in pixel data integer
`
`processing. Therefore, multiple threads can be spawned simultaneously to execute
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`integer instructions in the post-rasterization phase in order to perform fragment
`
`coloring, depth comparisons, texture mapping, and other back-end computations.
`
`31. Another equally important reason to use multithreading for computer
`
`graphics is to hide those latencies that are created because of vertex
`
`transformations that are executed using floating point instructions. Floating point
`
`instructions traditionally take more clock cycles to complete than integer
`
`instructions. Their Cycles per Instruction (CPI) is much larger than other
`
`instructions. A multithreaded processor can hide these long latencies by executing
`
`a thread associated with pixel processing on the hardware that would otherwise be
`
`idle.
`
`32. Multithreading is possible only if additional hardware resources, such
`
`as registers, are utilized to save the state of those threads that are in the execution
`
`queue, also called “active threads.” Active threads are those threads that have been
`
`designated a thread ID by the processor. Most importantly, there is a separate
`
`Program Counter register, or PC, that keeps track of the next instruction to be
`
`executed from each of the active threads. The thread ID is used to identify and
`
`properly handle instructions that belong to the same thread throughout the life of
`
`an instruction in the processor.
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`33.
`
`The figure above is a comparison of a conventional processor with a
`
`multithreaded processor, where different threads are shown in RGBY colors.
`
`34. One of the main issues for an effective multithreaded architecture is
`
`when to halt execution of instructions from the current thread and start executing
`
`another thread from several available active threads. There are many non-exclusive
`
`opportunities for thread switching in the hardware. Some of the well-known ones
`
`are discussed below:
`
`• Long latency instructions:
`
`the current
`
`thread is executing an
`
`instruction that takes many cycles to complete, during which time
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`hardware resources are not usable and the current
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`thread would
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`otherwise be idle.
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`• Branch misprediction: the branch predictor did not select the right
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`execution path. As a result, mispredicted in-flight instructions must be
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`

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`flushed from the pipelines, and new instructions fetched. During the
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`time it takes to do this, hardware resources will be idle.
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`• Cache miss: the fetching of an instruction or accessing a data memory
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`operand resulted in a cache miss (the required information is not
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`present in the cache) with many cycles of delay due to cache miss
`
`penalty (the time it
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`takes for
`
`the cache to fetch the required
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`information from slower memory). During this time, hardware
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`resources might otherwise go unused.
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`• External interrupts: An external interrupt (caused, for example, by an
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`external hardware peripheral) requires hundreds of cycles for a
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`context switch to occur, and for the slower peripheral responsible for
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`that interrupt to respond.
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`• Priority scheme: Certain threads may have higher priority selected by
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`the compiler or the programmer, indicating that they should receive
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`more access to the hardware resources than other, lower priority,
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`threads, or that they should be executed prior to other threads.
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`• Round-robin: This is an algorithm where every thread has equal
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`amount of time to run.
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`35.
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`There are three models of multithreading: coarse-grain, fine-grain, and
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`simultaneous multithreading, as shown in the following images:
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`36.
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`In coarse-grain schemes, a single thread may execute for several clock
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`cycles before switching to another thread. In the case of fine-grain multithreading,
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`each thread can only run for one clock cycle before the control is given to another
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`thread. The simultaneous multithreading is the most flexible approach where, at
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`any given clock cycle, all resources of the superscalar are available for all the
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`available threads.
`
`IV. THE ’454 PATENT
`
`A.
`
`37.
`
`Prosecution of the ’454 Patent
`
`The ’454 patent issued from U.S. Patent Application No. 13/109,738,
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`filed on May 17, 2011. On July 21, 2011, the Examiner issued a first non-final
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`Office action rejecting all the claims under 35 U.S.C. § 102(e) as being anticipated
`
`by U.S. 7,038,685 (“Lindholm”).
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`38.
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`In response to this rejection, the applicant did not amend the claims or
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`even challenge the disclosures of Lindholm. Instead, in a January 18, 2012
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`Response, the applicant attempted to “swear behind” Lindholm by submitting
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`declarations from each of the ’454 patent’s four inventors. The declarations
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`attempted to establish “conception and reduction to practice of the currently
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`claimed subject matter prior to the June 30, 2003 priority date of Lindholm.”
`
`39.
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`The Examiner was not persuaded. On March 15, 2012, he issued a
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`final Office action maintaining his rejection of the claims based on Lindholm.
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`Specifically, the Examiner found the applicant’s declarations insufficient to show
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`prior reduction to practice because they “fail[ed] to specify whether or not the
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`conception and reduction to practice was carried out in the United States, a
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`NAFTA country, or a WTO member country.” The Examiner further found that
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`the declarations also “fail[ed] to clearly explain which facts or data applicant [sic]
`
`is relying on to show completion of his or her invention prior to June 30, 2003.”
`
`40. On September 17, 2012, the applicant responded to the final action. In
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`that response, the applicant cancelled certain claims and argued that its
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`declarations “set for [sic] facts sufficient to show a conception and reduction to
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`practice sufficient to show priority of invention.”
`
`41.
`
`In a December 6, 2012 non-final Office action, the Examiner again
`
`explained why the applicant’s declarations were ineffective to overcome
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`Lindholm. The Examiner maintained his § 102(e) rejection. He also added a
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`rejection under 35 U.S.C. § 112, second paragraph, due to certain claims failing to
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`particularly point out and distinctly claim the subject matter of the alleged
`
`invention. The Examiner also added a new prior art rejection: obviousness over
`
`U.S. Patent No. 7,646,817 (“Shen”) in view of U.S. Patent No. 6,697,074
`
`(“Parikh”).
`
`42. On June 6, 2013, the applicant responded with further arguments
`
`about the sufficiency of its declarations. This time, however, the applicant also
`
`added another exhibit that allegedly “illustrate[d] claim language and
`
`corresponding code information” for the claims. The applicant argued that this new
`
`exhibit provided sufficient facts for the Examiner to find conception and reduction
`
`to practice prior to Lindholm.
`
`43.
`
`This new exhibit was apparently enough to persuade the Examiner to
`
`withdraw his Lindholm rejection. And on August 8, 2013, he issued a final Office
`
`action withdrawing the Lindholm rejection, as well as the § 112 rejection. The
`
`Examiner maintained his obviousness rejection based on Shen in view of Parikh.
`
`44.
`
`Following that action, the applicant conducted two telephone
`
`interviews with the Examiner on January 29 and 30, 2014. During these calls, the
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`Examiner represented that the applicant’s claims would be allowable with certain
`
`minor amendments. The Examiner also requested that the applicant file a terminal
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