UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`LG ELECTRONICS, INC.
`Petitioner
`
`v.
`
`ATI TECHNOLOGIES ULC
`Patent Owner
`____________
`
`Case No.: IPR2017-01225
`Patent 8,760,454
`____________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,760,454
`
`723303229
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`TABLE OF CONTENTS
`
`Page
`
`I.
`
`II.
`III.
`IV.
`V.
`
`MANDATORY NOTICES PURSUANT TO 37 C.F.R. §42.8.....................1
`A.
`Real Parties-In-Interest.........................................................................1
`B.
`Related Matters.....................................................................................1
`C.
`Lead and Backup Counsel....................................................................1
`D.
`Service Information..............................................................................2
`PAYMENT OF FEES ....................................................................................2
`STANDING....................................................................................................2
`SUMMARY OF THE PRIOR ART...............................................................3
`REQUEST FOR INTER PARTES REVIEW OF CLAIMS 2-11 OF
`THE ’454 PATENT........................................................................................3
`A.
`Technology Background ......................................................................3
`B.
`Description of the ’454 Patent..............................................................5
`C.
`Prosecution History of the ’454 Patent ................................................7
`VI. CLAIM CONSTRUCTION ...........................................................................8
`VII. COLLATERAL ESTOPPEL..........................................................................9
`VIII. GROUNDS FOR UNPATENTABILITY....................................................12
`A.
`Ground 1: Lindholm Anticipates Claims 2-11...................................13
`1.
`“unified shader” (claims 2-11).................................................15
`2.
`“general purpose register block” (claim 2) / “shared
`resources” (claims 3, 4) / “store” (claim 5) .............................17
`“processor unit” (claims 2-5, 8, 9, 11).....................................18
`“sequencer” (claims 2, 5).........................................................25
`“circuitry operative to fetch data from a memory” (claim
`6) ..............................................................................................26
`“selection circuit” (claim 7).....................................................27
`“arbiter” (claim 10) ..................................................................27
`“instruction store” (claim 11)...................................................28
`
`3.
`4.
`5.
`
`6.
`7.
`8.
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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`B.
`
`C.
`D.
`
`Ground 2: Lindholm, Alone or in Combination with the
`OpenGL Renders Claims 2-11 Obvious. ...........................................28
`1.
`Claims 2, 8, 9 ...........................................................................28
`2.
`Claims 3-10..............................................................................32
`Summary of Lindholm Grounds ........................................................33
`Ground 3: Stuttard Anticipates Claims 2 and 11. ..............................42
`1.
`“unified shader” (claims 2, 11) ................................................45
`2.
`“general purpose register block” (claim 2)..............................46
`3.
`“processor unit” (claims 2, 11) ................................................47
`4.
`“sequencer” (claim 2) ..............................................................48
`5.
`“instruction store” (claim 11)...................................................49
`Ground 4: Stuttard Renders Claims 2-11 Obvious. ...........................49
`1.
`“unified shader” (claims 3-10).................................................51
`2.
`“shared resources” (claims 3, 4) / “store” (claim 5) ................51
`3.
`“processor unit” (claims 3-5)...................................................51
`4.
`“sequencer” (claim 5) ..............................................................54
`5.
`“circuitry operative to fetch data from a memory” (claim
`6) ..............................................................................................55
`“selection circuit” (claim 7).....................................................55
`6.
`“arbiter” (claim 10) ..................................................................55
`7.
`Summary of Stuttard Grounds............................................................56
`F.
`IX. CONCLUSION.............................................................................................70
`
`E.
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`PETITIONER’S EXHIBIT LIST
`
`Exhibit # Reference Name
`1001
`U.S. Patent 8,760,454
`1002
`Prosecution History of U.S. Patent 8,760,454
`1003
`U.S. Patent 7,038,685 (“Lindholm”)
`1004 WO 00/62182 (“Stuttard”)
`1005
`Declaration of Nader Bagherzadeh, Ph.D.
`1006
`Final Written Decision in IPR2015-00325
`1007
`Final Written Decision in IPR2015-00326
`Curriculum Vitae of Nader Bagherzadeh, Ph.D.
`1008
`1009
`OpenGL Graphics System: A Specification, Version 1.4
`1010
`OpenGL Overview
`for U.S. Patent No. 8,760,454
`Infringement Chart
`(Public Ex. 21 to ITC Complaint in 337-TA-1044)
`
`1011
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Pursuant to 35 U.S.C. §§ 311-319 and 37 C.F.R. §§ 42.1-.80 & 42.100-.123
`
`et seq., Petitioner requests inter partes review of claims 2-11 of U.S. Patent
`
`8,760,454 (“the ’454 patent”) (“Ex. 1001”).
`
`I.
`
`MANDATORY NOTICES PURSUANT TO 37 C.F.R. §42.8
`
`A.
`
`Real Parties-In-Interest
`
`LG Electronics U.S.A., Inc. and LG Electronics MobileComm U.S.A., Inc.
`
`are real parties-in-interest with Petitioner LG Electronics, Inc.
`
`B.
`
`Related Matters
`
`The ’454 patent is the subject of the following actions brought by Patent
`
`Owner against Petitioner that may affect or be affected by a decision in this
`
`proceeding: U.S. International Trade Commission Inv. No. 337-TA-1044 and the
`
`U.S. District Court for the District of Delaware Case No. 1:17-cv-00065. Petitioner
`
`is concurrently filing a petition for U.S. Patent 9,582,846, which is also being
`
`asserted in those litigations. The ’454 patent is a continuation of U.S. Patent
`
`6,897,871 (“the ’871 patent”), which was subject to review in IPR2015-00326.
`
`C.
`
`Lead and Backup Counsel
`
`Robert G. Pluta (lead counsel)
`Registration No. 50,970
`Amanda K. Streff (back-up counsel)
`Registration No. 65,224
`MAYER BROWN LLP
`71 S. Wacker Drive
`Chicago, IL 60606
`Telephone: (312) 701-8641
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`

`Patent No. 8,760,454
`Petition for Inter Partes Review
`Fax: (312) 706-8144
`rpluta@mayerbrown.com
`astreff@mayerbrown.com
`
`Bryan Nese (back-up counsel)
`Registration No. 66,023
`MAYER BROWN LLP
`1999 K Street, N.W.
`Washington, DC 20006-1101
`Telephone: (202) 263-3266
`Fax: (202) 263-3300
`bnese@mayerbrown.com
`
`D.
`
`Service Information.
`
`Please direct all correspondence regarding this proceeding to lead counsel at
`
`the addresses identified above. Petitioner consents to electronic service by email:
`
`rpluta@mayerbrown.com,
`
`bnese@mayerbrown.com,
`
`and
`
`astreff@mayerbrown.com with a courtesy copy to AMDIPR@mayerbrown.com.
`
`II.
`
`PAYMENT OF FEES
`
`Pursuant to 37 C.F.R. §42.103, $23,000 is being paid at the time of filing
`
`this petition, charged to Deposit Account 130019. Should any further fees be
`
`required, the Board is hereby authorized to charge the above referenced Deposit
`
`Account.
`
`III.
`
`STANDING
`
`Pursuant to 37 C.F.R. §42.104(a), Petitioner certifies that (1) the ’454 patent
`
`is available for review; and (2) Petitioner is not barred or estopped from requesting
`
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`review of claims 2-11 of the ’454 patent on the grounds identified in this Petition.
`
`This Petition is timely filed under 35 U.S.C. § 315(b).
`
`IV.
`
`SUMMARY OF THE PRIOR ART
`
`Petitioner has a reasonable likelihood of prevailing with respect to claims 2-
`
`11 of the ’454 patent. Specifically, these claims should be found unpatentable in
`
`view of the following prior art:
`
`Patent/Publication No.
`
`US 7,038,685 (“Lindholm”)
`WO 00/62182 (“Stuttard”)
`OpenGL v1.4
`
`Priority
`Date
`6/30/2003
`10/19/2000
`7/24/2002
`
`Publication
`Date
`5/2/2006
`10/19/2000
`7/24/2002
`
`Exhibit
`No.
`1003
`1004
`1009
`
`V.
`
`REQUEST FOR INTER PARTES REVIEW OF CLAIMS 2-11 OF
`THE ’454 PATENT
`
`Pursuant to 37 C.F.R. §42.104(b), Petitioner requests that the Board find
`
`claims 2-11 of the ’454 patent unpatentable.
`
`A.
`
`Technology Background
`
`Graphics processing systems were well known before the effective filing
`
`date of the ’454 patent. E.g., Ex. 1001, 1:38-2:29, FIGS. 1-3. The patent discloses
`
`that graphics processors generate complex shapes and structures for display on a
`
`screen. Id. at 1:38-48. Often, programs called shaders included in graphics
`
`processors are used to specify how, and with what corresponding attributes, “a
`
`final image is drawn on a screen … .” Id. at 1:51-54.
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`For example, a shader can accept a plurality of inputs such as shape, color,
`
`and texture data of an object, and process those inputs to create an output. Id. at
`
`1:54-62. The shader output may represent the constructed object with appearance
`
`properties that can be displayed on a screen. Id. at 1:54-62.
`
`Early graphics processors used two types of shaders: vertex and pixel. Id. at
`
`2:25-29. “Vertex” shaders accepted coordinate data representing 3D objects and
`
`transformed the coordinate data into data that can be displayed on a screen. Id. at
`
`1:63-2:7. “Pixel” shaders accepted pixel data of rendered graphic objects and
`
`provided appearance attributes, such as color values, to each pixel. Id. at 2:8-12.
`
`Figure 3 of the patent illustrates vertex and pixel shaders positioned in a sequential
`
`or serial fashion in a graphics processor architecture:
`
`Ex. 1001, FIG. 3
`
`4
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`After vertex shader 46 performs coordinate transformation, the transformed
`
`vertex data is transmitted to a primitive assembly block 50, which converts the
`
`transformed vertex data into a plurality of primitives (or, objects) to be further
`
`processed. Id. at 3:44-46. The next sequential processing occurs when the
`
`assembled data is converted to pixel data by a rasterization engine 52. Id. Finally,
`
`the pixel data is processed by pixel shader 54 to generate color and other
`
`appearance attributes.
`
`Id. at 3:54-60; see Ex. 1005, Declaration of Nader
`
`Bagherzadeh, Ph.D., ¶¶26-36, 222.
`
`B.
`
`Description of the ’454 Patent
`
`The ’454 patent describes a graphics processing architecture that uses a
`
`single shader (a so-called unified shader) to perform both vertex and pixel
`
`operations, instead of separate shaders for each type of operation. Ex. 1001,
`
`Abstract. Figure 4a of the patent
`
`illustrates the described graphics processor
`
`architecture:
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`Patent No. 8,760,454
`Petition for Inter Partes Review
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`Ex. 1001, FIG. 4A
`
`This architecture includes “an arbiter circuit for selecting one of a plurality
`
`of inputs for processing ….” Id. at 2:62-65. The inputs can either be vertex data or
`
`pixel data. Id. at 4:13-28. After the arbiter selects the inputs, a shader 62 performs
`
`either vertex operations or pixel operations. Id. at 2:66-3:3. Shader 62 is connected
`
`to a cache block 70, which stores parameter and position information, and which is
`
`connected to a primitive assembly block 72. Id. at 5:53-63. Primitive assembly
`
`block 72 is connected to a rasterization engine 74, which converts the primitives
`
`into pixel data information. Id. at 5:63-6:1.
`
`Shader 62 contains a general-purpose register 92 for storing pixel and vertex
`
`information output from multiplexer 66. See id. at 4:34-37.
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`Patent No. 8,760,454
`Petition for Inter Partes Review
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`Ex. 1001, FIG. 5
`
`Shader 62 also includes a sequencer 99 that contains instructions for the
`
`vertex and pixel data stored in register 92. Id. at 5:6-18, 5:19-21. A sequencer
`
`determines the type of processing that needs to be performed and sends data to
`
`source registers (93, 95, 97) for subsequent execution. Id. at 5:6-18. Because
`
`general purpose register 92 stores both vertex and pixel data and the sequencer
`
`stores both vertex and pixel instructions to be executed by processor 96, shader 62
`
`can “perform both vertex and pixel operations.” Id. at 5:21-23.
`
`C.
`
`Prosecution History of the ’454 Patent
`
`The application leading to the ’454 patent was filed on May 17, 2011, and
`
`issued on June 24, 2014. The ’454 patent claims priority to an application filed
`
`November 20, 2003. Accordingly, Lindholm qualifies as prior art under 35 U.S.C.
`
`§ 102(e). Stuttard and OpenGL qualify as prior art under 35 U.S.C. § 102(b).
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Neither Stuttard nor OpenGL was considered during prosecution of the ’454
`
`patent.
`
`During prosecution, the Examiner used Lindholm to reject the claims of the
`
`’454 patent. E.g., Ex. 1002, 103-14, 262-73. Patent Owner ATI was not able to
`
`overcome this rejection on the merits of Lindholm. Id. at 411, ¶4. Indeed, ATI
`
`never addressed this Lindholm rejection on its merits, and instead argued that
`
`Lindholm was not prior art based on the same swear-behind arguments this Board
`
`would later reject in IPR2015-00325 and -00326.1 See id. at 127-29, 356-61, 458-
`
`59.
`
`Thus, claims 2-11 are unpatentable, as ATI all but admitted by not
`
`challenging the Examiner’s Lindholm rejection on the merits.
`
`VI. CLAIM CONSTRUCTION
`A claim subject to inter partes review is given its “broadest reasonable
`
`construction in light of the specification of the patent in which it appears.” 37
`
`C.F.R. §42.100(b). This means that the words of the claim are given their plain
`
`meaning from the perspective of one of ordinary skill in the art unless that meaning
`
`1 In IPR2015-00325 and IPR2015-00326, the Board ruled that the ’454 patent’s
`
`parent patent (the ’871 patent) is not entitled to a priority date that would antedate
`
`Lindholm. See Ex. 1007, 4.
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`is inconsistent with the specification. In re Zletz, 893 F.2d 319, 321 (Fed. Cir.
`
`1989). Petitioner submits, for the purposes of inter partes review only, that the
`
`claim terms are presumed to take on their broadest reasonable interpretation in
`
`light of the specification of the ’454 patent.2
`
`VII. COLLATERAL ESTOPPEL
`
`The issue of whether ATI is entitled to a priority date earlier than its earliest
`
`effective filing date for the ’454 patent family was fully litigated and resolved in
`
`Petitioner’s favor in IPR2015-00325 and -00326. There is no need to consider that
`
`issue again.
`
`Thus, ATI is collaterally estopped from rearguing these determinations in
`
`the present proceeding. See Ohio Willow Wood v. Alps South, 735 F.3d 1333, 1342
`
`(Fed. Cir. 2013) (“Our precedent does not limit collateral estoppel to patent claims
`
`2 Inter partes review is limited to evaluating invalidity issues arising from the
`
`consideration of certain prior-art issues, i.e., 35 U.S.C. §§ 102-103; and, therefore,
`
`excludes consideration of indefiniteness, enablement, and numerous other grounds
`
`for invalidity. Petitioner thus files this inter partes review without prejudice to its
`
`right to challenge the validity of the subject patent in other forums and proceedings
`
`on any and all bases recognized by law and equity, including, but not limited to,
`
`the basis that any of the claim terms at issue are indefinite.
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`that are identical. Rather it is the identity of the issues that were litigated that
`
`determines whether collateral estoppel should apply.”).
`
`“Collateral estoppel protects a party from having to litigate issues that have
`
`been fully and fairly tried in a previous action and adversely resolved against a
`
`party-opponent.” Id. at 1342. Collateral estoppel is applicable in a later proceeding
`
`when: (1) the issues in the first action are identical to those in the second; (2) the
`
`same issues were actually litigated; (3) resolution of those issues was essential to
`
`the final judgment in the first action; and (4) the party against whom preclusion is
`
`being applied had a full, fair opportunity to litigate those issues. In re Freeman, 30
`
`F.3d 1459, 1465 (Fed. Cir. 1994).
`
`Moreover, collateral estoppel attaches upon the entry of the final judgment,
`
`even before all appeals are exhausted. See Pharmacia v. Mylan, 170 F.3d 1373,
`
`1381 (Fed. Cir. 1999) (pending appeal does not preclude application of collateral
`
`estoppel).
`
`This proceeding is related to IPR2015-00326 involving the ’871 patent, to
`
`which the ’454 patent claims priority. In that proceeding, the Board found that ATI
`
`did not antedate U.S. Patent 7,015,913 (“Lindholm ’913”) based on another related
`
`final written decision in IPR2015-00325, Paper 62 (Ex. 1006). Ex. 1007, IPR2015-
`
`00326, Paper 49 at 4.
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Thus, This proceeding involves the same issue that was fully litigated in
`
`IPR2015-00326, and which resulted in a final written decision, namely, whether
`
`ATI could claim priority prior for the ’454 patent’s parent prior to June 2003,
`
`thereby antedating both Lindholm references. The antedating issue was essential to
`
`the final written decision finding claims unpatentable over Lindholm ’913, and
`
`ATI had a full, fair opportunity to litigate that issue.
`
`Thus, collateral estoppel applies based on the final written decisions in
`
`IPR2015-00326 and IPR2015-00325. See B&B Hardware v. Hargis, 135 S. Ct.
`
`1293, 1302-05 (2015) (applying collateral estoppel to a final judgment by an
`
`administrative agency acting in an adjudicative capacity).
`
`This would not be the first panel of the Board to apply collateral estoppel. In
`
`CBM2016-0081, the petitioner argued that the identified issues for disqualification
`
`were raised in a Federal Circuit appeal, and that collateral estoppel barred the
`
`patent owner from re-litigating those issues. SAP America, Inc. v. Lakshmi
`
`Arunachalam, CBM2016-00081, Paper 12 at 3 (P.T.A.B. Nov. 18, 2016). The
`
`panel agreed: “[t]he arguments proffered by Patent Owner in its Motion are
`
`generally the same as those raised in the similar motion made to the Federal
`
`Circuit” and that “all of the aspects required for collateral estoppel to apply have
`
`been met.” Id. at 4-5 (citing Dana v. E.S. Originals, Inc., 342 F.3d 1320, 1323
`
`(Fed. Cir. 2003)).
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`The decision in IPR2015-00326 adopted the decision and reasoning from the
`
`prior decision in IPR2015-00325 involving the same parties, same issue, and same
`
`evidence. Specifically, the Board found that “Patent Owner relies [on] the same
`
`evidence and substantially the same arguments in the present review and in
`
`IPR2015-00325 in support of its efforts to antedate Lindholm [’913].” Ex. 1007 at
`
`3. The Board noted that the final written decision in IPR2015-00325 found that
`
`ATI had not antedated Lindholm ’913 and that the claims challenged in IPR2015-
`
`00326 were unpatentable over Lindholm ’913. Id. at 4.
`
`For the same reasons, collateral estoppel applies in this case. ATI should not
`
`be permitted to relitigate the issue of whether it can antedate the Lindholm
`
`reference used here. See, e.g., Finjan, Inc. v. Proofpoint, Inc., Case No. 13-cv-
`
`05808-HSG, 2016 WL 1427462, at *7-8 (N.D. Cal. Apr. 12, 2016) (applying
`
`collateral estoppel to preclude the plaintiff from rearguing the priority date of an
`
`asserted patent).
`
`The Board considered ATI’s antedating arguments before; it need not do so
`
`again.
`
`VIII. GROUNDS FOR UNPATENTABILITY
`
`Ground Claims
`1
`2-11
`2
`2-11
`
`Statutory Basis
`Anticipated under 35 U.S.C. § 102(e) by Lindholm
`Obvious Under 35 U.S.C. § 103(a) over Lindholm,
`Alone or in Combination with OpenGL
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ground Claims
`3
`2, 11
`4
`2-11
`
`Statutory Basis
`Anticipated under 35 U.S.C. § 102(b) by Stuttard
`Obvious Under 35 U.S.C. § 103(a) over Stuttard
`
`As explained in further detail by Petitioner’s expert, Dr. Nader Bagherzadeh,
`
`each of claims 2-11 is unpatentable as being anticipated by the prior art. Dr.
`
`Bagherzadeh also explains that these claims would have been obvious to a person
`
`of ordinary skill in the art at the time of the alleged invention (a “POSA”)3 based
`
`on the teachings of the prior art.
`
`A.
`
`Ground 1: Lindholm Anticipates Claims 2-11.
`
`Lindholm discloses a graphics processing system capable of multithreaded
`
`processing. Ex. 1003, Abstract. Lindholm’s graphics processing system includes a
`
`dedicated graphics processor 105 having a Programmable Graphics Processing
`
`Pipeline 150. Id. at FIG. 1. Pipeline 150 is made up of a plurality of Execution
`
`Pipelines 240 each having at least one Multithreaded Processing Unit 400, which
`
`processes samples from either a Vertex Input Buffer 220 or a Pixel Input Buffer
`
`215. Id. at 4:22-41, 5:11-22, FIG. 2. As will be discussed, Lindholm’s Execution
`
`3 A POSA at the time of the alleged invention of the ’454 patent would have had a
`
`Master’s Degree in Electrical or Computer Engineering, or equivalent thereof, and
`
`two or more years of practical working experience in the relevant field. Ex. 1005,
`
`¶48.
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`Patent No. 8,760,454
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`Pipeline 240 includes components that correspond to the claimed “unified shader”;
`
`the pipeline performs both vertex and pixel operations.
`
`For the Board’s convenience, the following table and annotated figure
`
`summarize non-limiting, exemplary structures in Lindholm that correspond to
`
`certain claim terms:
`
`Claim Term
`“unified shader”
`
`“general purpose register block”
`“shared resources”
`“store”
`“processor unit”
`“sequencer”
`
`“instruction store”
`“circuitry operative to fetch data”
`“selection circuit”
`“arbiter”
`
`Exemplary Structure in Lindholm
`Execution Pipeline 240 and/or certain
`components thereof
`Register File 350 and memory locations
`(registers) therein, as well as other
`memory locations in Lindholm
`
`Execution Unit 470
`Circuitry including Instruction
`Scheduler 430, Instruction Dispatcher
`440, and Instruction Cache 410
`Instruction Cache 410
`Instruction Dispatcher 440
`Thread Selection Unit 415
`Thread Control Unit 420
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`Patent No. 8,760,454
`Petition for Inter Partes Review
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`“instruction store”
`
`“sequencer”
`
`“circuitry … to
`fetch”
`
`“processor unit”
`
`“selection
`circuit”
`
`“arbiter”
`
`“general purpose
`register block” /
`“shared resources”
`/ “store”
`
`Ex. 1003, FIG. 4 (annotated)
`
`1.
`
`“unified shader” (claims 2-11)
`
`As illustrated in Figure 2 of Lindholm, samples from the Vertex Input Buffer
`
`220 are directed to and processed by the Execution Pipeline 240 and stored in a
`
`Vertex Output Buffer 260 in a cache. Id. at 4:65-5:1, FIG. 2.
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`
`Ex. 1003, FIG. 2
`
`The processed vertices from Vertex Output Buffer 260 are then sent to a
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`Primitive Assembly/Setup 205 followed by a Raster Unit 210 to “calculate[]
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`parameters” and to “perform[] scan conversion on samples,” respectively. Id. at
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`4:65-5:10. Output samples from Raster Unit 210 are received by Pixel Input Buffer
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`215, which then sends the samples to be processed by Execution Pipeline 240. Id.
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`at 5:11-22.
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`Each Execution Pipeline 240 can perform both vertex functions, such as
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`transforming samples from one coordinates space to another (id. at 4:44-49), and
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`pixel functions such as texture mapping, shading, and blending (id. at 5:25-33).
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`Thus, although these claims’ preambles are not limiting when given their
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`broadest reasonable interpretation, Execution Pipeline 240 (and/or components
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`thereof) corresponds to the “unified shader.”
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`2.
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`“general purpose register block” (claim 2) / “shared
`resources” (claims 3, 4) / “store” (claim 5)
`Locations (registers) in Register File 350 correspond to the claimed “general
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`purpose register block,” “shared resources,” and “store.” 4 Register File 350
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`contains source data, including “intermediate data generated during processing of
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`the sample” that entails both vertex data and pixel data. Ex. 1003, 5:64-66; see also
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`id. at 8:49-58 (further discussion of source data storage in Register File 350), 7:37-
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`40 (explaining that Register File 350 is used “to retain intermediate data generated
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`during execution of program instructions”).
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`Lindholm uses the term sample broadly “to refer to graphics data such as
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`surfaces, primitives, vertices, pixels, fragments, or the like”—thus including both
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`pixel and vertex data. Id. at 3:62-64; see also id. at 4:42-44.
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`4 Lindholm also discloses that, in addition to Register File 350, source data may
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`also be stored in “Local Memory 140, locations in Host Memory 112, and the
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`like.” Ex. 1003, 7:41-43. Any of these locations may also constitute the claimed
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`“general purpose register block,” “shared resources,” and “store.”
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`During the pending ITC proceeding (337-TA-1044) involving the ’454
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`patent, ATI’s affiliate AMD pointed to “registers” in the accused products as
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`satisfying the claimed “shared resources.” Ex. 1011, pp. 22, 35.
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`3.
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`“processor unit” (claims 2-5, 8, 9, 11)
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`Lindholm’s Execution Unit 470 constitutes
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`the
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`“processor unit.”
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`Specifically, Execution Unit 470 executes pixel calculation operations (such as
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`instructions that generate a pixel color) and vertex calculation operations (such as
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`instructions that generate vertex position and appearance data). Id. at 3:57-64
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`(explaining that Pipeline 150, which includes Execution Unit 470, “is programmed
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`to operate on surface, primitive, vertex, fragment, pixel, sample or any other
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`data”), 9:33-37, 9:47-49.
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`Lindholm’s “samples” include both pixel and vertex operations. Id. at 3:59-
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`64; see also id. at 5:23-29 (“programmable computation units (PCUs) within an
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`Execution Pipeline 240 … perform operations such as tessellation, perspective
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`correction, texture mapping, shading, blending, and the like”).
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`A POSA would have recognized that the ability to operate on pixel data and
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`perform operations like shading and blending, as described in Lindholm, would
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`necessarily entail executing instructions that generate a pixel color, as recited by
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`claim 8. Ex. 1005, ¶104. Execution Unit 470 is operatively coupled to Register File
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`350, as well as the other memory locations discussed in Lindholm. See Ex. 1003,
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`FIGS. 1, 4.
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`Execution Unit 470 processes a variety of instructions to operate on both
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`pixel and vertex data, thus carrying out both pixel and vertex calculation operations
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`using data contained in Register File 350 (and the other memory locations
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`mentioned previously) and instructions in Instruction Cache 410. See id. at 3:57-
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`64, FIG. 4. Execution Unit 470 performs these operations according to thread
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`allocation and execution priorities. Id. at 6:61-7:11.
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`Lindholm flexibly specifies a variety of priority schemes for performing
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`pixel/vertex operations, including those that will “achieve maximum utilization of
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`the computation resources in Execution Pipelines 240” (id. at 8:10-14), as well as
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`those based on the amount of resources available (id. at 12:20-28, 12:61-66, 16:19-
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`24).
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`Lindholm also executes threads based on vertex or pixel workload. For
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`example, Resource Scoreboard 460 keeps track of the availability of resources for
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`processing the samples. E.g., id. at 9:2-4, 9:50-56. Lindholm also tracks the space
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`available in Register File 350, which is used to store vertex data and pixel
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`information. Id. at 9:57-62. Lindholm further bases thread execution decisions on
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`“the amount of storage for intermediate data generated during processing of a
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`sample.” See id. at 12:9-14, 12:34-36, 16:19-24.
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`Patent No. 8,760,454
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`Further, Lindholm discloses the functional language recited by claims 3-11,
`
`as discussed in the following sections.
`
`(i)
`
`“the processor unit operative to … perform pixel calculation
`operations until enough shared resources become available and
`then use the shared resources to perform vertex calculation
`operations” (claim 3)
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`Execution Unit 470 executes threads in an order determined by the disclosed
`
`thread execution priorities. Id. at 10:17-11:14, FIGS. 5B. For example, as
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`illustrated in Figure 5B, Lindholm determines in step 535 whether a pixel thread
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`may be allocated based on “thread allocation priority” and then performs the pixel
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`operations associated with that pixel thread. Id. at 10:40-45. Thus, Lindholm will
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`perform pixel calculation operations. See id.
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`After performing one or more pixel calculation operations, when a pixel
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`thread may not be allocated (for example, when the thread allocation priority is
`
`based on resource availability of Register File 350, and not enough resources are
`
`available in Register File 350 for performing the selected pixel operation), the
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`process will return to step 510, which will assign a new pointer to a program, such
`
`as a vertex program, which will then be executed in accordance with the resource-
`
`based priority scheme, because enough resources are now available for performing
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`vertex calculation operations. See id. at 10:20-54, FIG. 5B.
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`Patent No. 8,760,454
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`Ex. 1003, FIG. 5B
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`Accordingly, Lindholm describes performing pixel calculation operations
`
`until enough shared resources become available and then using the shared
`
`resources to perform vertex calculation operations. Ex. 1005, ¶¶117-40.
`
`(ii)
`
`“the processor unit operative to … perform vertex calculation
`operations until enough share resources become available and
`then use the shared resources to perform pixel calculation
`operations” (claim 4)
`
`Similarly, as also shown in Figure 5B, Lindholm determines in step 520
`
`whether a vertex thread may be allocated based on “thread allocation priority” and
`
`then performs the vertex operations associated with that vertex thread. Ex. 1003,
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`10:25-30. Thus, Lindholm will perform vertex calculation operations. See id.
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`Patent No. 8,760,454
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`After performing one or more vertex calculation operations, when a vertex
`
`thread may not be allocated (for example, when the thread allocation priority is
`
`based on resource availability of Register File 350 as described previously, and not
`
`enough resources are available in Register File 350 for performing the selected
`
`vertex operation), the process will return to step 510, which will assign a new
`
`pointer to a program, such as a pixel program, which will then be executed in
`
`accordance with the resource-based priority scheme, because enough resources are
`
`now available for performing pixel calculation operatoins. See id. at 10:20-54, FIG.
`
`5B.
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`Accordingly, Lindholm describes performing vertex calculation operations
`
`until enough shared resources become available and then using the shared
`
`resources to perform pixel calculation operations. Ex. 1005, ¶¶141-51.
`
`(iii) “the processor unit to execute vertex calculation and pixel
`calculation operations on selected data maintained in a store
`depending upon an amount of space available in the store”
`(claim 5)
`
`Lindholm also describes more generally the ability to execute vertex
`
`calculation and pixel calculation operations on selected data maintained in a store
`
`depending upon an amount of space available in the store. Ex. 1003, 10:20-54,
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`12:9-14, 12:34-36, 15:7-13, 16:19-24, FIGS. 5B, 8B. Lindholm’s threads are
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`“allocated storage resources such as locations in Register File 350 to retain
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`intermediate data generated during execution of program instructions associated
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`with the thread.” Id. at 7:37-40.
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`A POSA would understand that Lindholm’s “dynamically determined thread
`
`allocation priority,” which Lindholm teaches may be based on the size and amount
`
`of data to be processed (id. at 7:21-31), would necessarily depend on the amount of
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`space available in Register File 350. Ex. 1005, ¶¶152-66.
`
`For example, if there were not enough resources in Register File 350 to
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`“retain intermediate data generated during execution” of the instructions, Lindholm
`
`would seek to further
`
`its goal of achiev