PC SDRAM Unbuffered DIMM Specification
`
`PC SDRAM UNBUFFERED DIMM SPECIFICATION
`
`REVISION 1.0
`
`Feb., 1998
`
` 1 of 47
`
` Revision 1.0
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`KINGSTON 1008
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`THIS DOCUMENT IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER,
`INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY
`PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY
`PROPOSAL, SPECIFICATION, OR SAMPLE.
`No other license, express or implied, by estoppel or otherwise, to any other intellectual
`property rights is granted herein. Intel disclaims all liability, including liability for
`infringement of any proprietary rights, relating to implementation of information in this
`specification. Intel does not warrant or represent that such implementation(s) will not
`infringe such rights.
`
`* Other brands and names are the property of their respective owners.
`
`Copyright Intel Corporation, 1997
`
`Feb., 1998
`
` 2 of 47
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` Revision 1.0
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` PC SDRAM Unbuffered DIMM Specification
`
`Changes:
`
`Revision 0.9 Oct., 1997
`
`Changed example stackup spacing to 7-11-7-11-7 with 0.5 oz. Copper
`Added Section for DIMM PCB and Assembly labeling requirements.
`Changed topology diagram notes to allow additional vias.
`Modified mechanicals to include heat sink notches.
`
`Revision 1.0 Feb., 1998
`
`Changed example stackup spacing to 7-10-9-10-7.
`Removed specifications relating to 64Mbit / 2-bank SDRAM components.
`Increased max overall thickness to 4.33mm to account for height of SOIC EEPROM.
`Changed topology diagrams to allow additional vias.
`Added note to mechanicals to indicate that heat sink notches are optional.
`Increased max interval between vias connecting ground rings to 0.7”.
`Included specifications for outer layer clock trace lengths for x16 based designs.
`Removed outer layer clock trace length placeholder for x8 based designs.
`Modified mixed mode DIMM wiring diagrams and clock loading table to indicate that the
`higher density DRAMs must always be placed on the primary side of the DIMM.
`Added information on Intel clock simulation assumptions to allow independent
`simulation of scenarios for which specific lengths are not specified.
`Added configuration listings for 256MB and 512MB DIMMs based on 128Mbit and
`256Mbit components respectively.
`Removed the requirement that the vendor name and part number be provided in etch
`or silkscreen on the DIMM.
`
`Feb., 1998
`
` 3 of 47
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`

` PC SDRAM Unbuffered DIMM Specification
`
`TABLE OF CONTENTS
`
`LIST OF TABLES
`
`LIST OF FIGURES
`
`1.0 INTRODUCTION
`
`2.0 ENVIRONMENTAL REQUIREMENTS
`
`3.0 MECHANICAL DESIGN
`
`4.0 MODULE PINOUT
`
`5.0 SDRAM DIMM BLOCK DIAGRAMS
`
`6.0 DIMM PCB LAYOUT AND SIGNAL ROUTING
`
`7.0 DIMM PCB AND FINAL ASSEMBLY LABELING REQUIREMENTS
`
`8.0 SDRAM COMPONENT SPECIFICATIONS
`
`9.0 EEPROM COMPONENT SPECIFICATIONS
`
`5
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`6
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` PC SDRAM Unbuffered DIMM Specification
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`LIST OF TABLES
`7
`TABLE 1: RELATED DOCUMENTS
`8
`TABLE 2: SDRAM NON MIXED-MODE MODULE CONFIGURATIONS
`9
`TABLE 3: SDRAM MIXED-MODE MODULE CONFIGURATIONS
`TABLE 4: DIMM TEMPERATURE, HUMIDITY & BAROMETRIC PRESSURE REQUIREMENTS 10
`TABLE 5: DIMM DIMENSIONS AND TOLERANCES
`11
`TABLE 6: DIMM DIMENSIONS AND TOLERANCES (CONTINUED)
`12
`TABLE 7: SDRAM DIMM PINOUT
`18
`TABLE 8: PCB CALCULATED PARAMETERS
`32
`TABLE 9: SIGNAL TOPOLOGY CATEGORIES
`35
`TABLE 10: TRACE LENGTH TABLE FOR CLOCK TOPOLOGIES
`39
`TABLE 11: TRACE LENGTH TABLE FOR DATA TOPOLOGIES
`40
`TABLE 12: TRACE LENGTH TABLE FOR DATA MASK TOPOLOGIES (1/2 LOADS)
`41
`TABLE 13: TRACE LENGTH TABLE FOR DATA MASK TOPOLOGIES (1/2/3 LOADS)
`42
`TABLE 14: TRACE LENGTH TABLE FOR CHIP SELECT TOPOLOGIES
`43
`TABLE 15: TRACE LENGTH TABLES FOR CLOCK ENABLE TOPOLOGIES
`44
`TABLE 16: TRACE LENGTH TABLE FOR DOUBLE CYCLE SIGNAL TOPOLOGIES
`45
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` PC SDRAM Unbuffered DIMM Specification
`
`LIST OF FIGURES
`FIGURE 1: DIMM MECHANICAL DRAWING (1 OF 5)
`FIGURE 2: DIMM MECHANICAL DRAWING (2 OF 5)
`FIGURE 3: DIMM MECHANICAL DRAWING (3 OF 5)
`FIGURE 4: DIMM MECHANICAL DRAWING (4 OF 5)
`FIGURE 5: DIMM MECHANICAL DRAWING (5 OF 5)
`FIGURE 6: 64-BIT NON-ECC DIMM BLOCK DIAGRAM (1 ROW, X16 SDRAMS)
`FIGURE 7: 64-BIT NON-ECC DIMM BLOCK DIAGRAM (2 ROWS, X16 SDRAMS)
`FIGURE 8: 64 BIT NON-ECC DIMM BLOCK DIAGRAM (1 ROW X8 SDRAMS)
`FIGURE 9: 64-BIT NON-ECC DIMM BLOCK DIAGRAM (2 ROWS X8 SDRAMS)
`FIGURE 10: 64 BIT NON-ECC BLOCK DIAGRAM (1 ROW X 32 SDRAMS)
`FIGURE 11: 64-BIT NON-ECC BLOCK DIAGRAM (2 ROWS X32 SDRAMS)
`FIGURE 12: 72-BIT ECC SDRAM DIMM BLOCK DIAGRAM (1 ROW X8 SDRAMS)
`FIGURE 13: 72-BIT ECC SDRAM DIMM BLOCK DIAGRAM (2 ROWS X8 SDRAMS)
`FIGURE 14: 72-BIT ECC SDRAM DIMM BLOCK DIAGRAM (1 ROW X16 SDRAMS)
`FIGURE 15: 72-BIT ECC SDRAM DIMM BLOCK DIAGRAM (2 ROWS X16 SDRAMS)
`FIGURE 16: 64-BIT NON-ECC DIMM BLOCK DIAGRAM (1 ROW X8 + 1 ROW X16 SDRAMS)
`FIGURE 17: 72-BIT ECC SDRAM DIMM BLOCK DIAGRAM (1 ROW X8 + 1 ROW X16)
`FIGURE 18: CLOCK LOADING TABLE & WIRING DIAGRAM
`FIGURE 19: EXAMPLE 6-LAYER PCB STACKUP
`FIGURE 20: EXAMPLE TOPOLOGY
`FIGURE 21: SIGNAL ROUTING TOPOLOGIES FOR CLOCKS
`FIGURE 22: SIGNAL ROUTING TOPOLOGIES FOR DATA
`FIGURE 23: SIGNAL ROUTING TOPOLOGIES FOR DATA MASK (1/2 LOADS)
`FIGURE 24: SIGNAL ROUTING TOPOLOGIES FOR DATA MASK (1/2/3 LOADS)
`FIGURE 25: SIGNAL ROUTING TOPOLOGIES FOR CHIP SELECT
`FIGURE 26: SIGNAL ROUTING TOPOLOGIES FOR CLOCK ENABLE
`FIGURE 27: SIGNAL ROUTING TOPOLOGIES FOR DOUBLE CYCLE SIGNALS
`
`13
`14
`15
`16
`17
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`20
`21
`22
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`24
`25
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`27
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` PC SDRAM Unbuffered DIMM Specification
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`1.0 Introduction
`
`This specification defines the electrical and mechanical requirements for 168-pin, 3.3 volt, 64-bit and 72-
`bit wide, 4 clock, unbuffered Synchronous DRAM Dual In-Line Memory Modules (SDRAM DIMMs).
`These SDRAM DIMMs are intended for use as main memory installed on personal computer
`motherboards.
`
`1
`
`This specification largely follows the JEDEC defined 168-pin unbuffered SDRAM DIMM as of JEDEC
`committee meeting of December 1996.
`
`This specification focuses on six layer double-sided assembly PCB designs. Other cost optimized designs
`may be possible; however, careful adherence to the contents of this spec as well as clock flight time and
`skew requirements on the DIMM is necessary. See section 6 below for information on clock flight time
`requirements for defining clock trace lengths.
`
`Related Documents
`
`Table 1: Related Documents
`
`TITLE
`Intel PC SDRAM Specification
`Intel SDRAM SPD Data Structure Specification
`
`REV
`Current
`Current
`
`The related documents contain information that is critical to this specification. See the Intel Developer’s
`web site at http://developer.intel.com for the latest revision of each spec.
`
`Feb., 1998
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` PC SDRAM Unbuffered DIMM Specification
`
`DIMM Configurations
`
`SDRAM DIMM configurations are defined in the following tables:
`Table 2: SDRAM Non Mixed-Mode Module Configurations
`
`Config #
`
`1
`
`2
`
`3
`
`4
`
`5
`
`DIMM
`Capacity
`8 MB
`
`DIMM
`Organization
`1M X 64
`
`SDRAM
`density
`16 Mbit
`
`SDRAM
`Organization
`1MX16
`
`# of
`SDRAMs
`4
`
`# Rows of
`SDRAM
`1
`
`# Banks in
`SDRAM
`2
`
`# Address bits
`row/bank/col
`11/1/8
`
`16 MB
`
`2M X 64
`
`16 Mbit
`
`1MX16
`
`16 MB
`
`2M X 64
`
`16 Mbit
`
`32 MB
`
`4M X 64
`
`16 Mbit
`
`2MX8
`
`2MX8
`
`16 MB
`
`2M X 64
`
`64 Mbit
`
`2MX32
`
`8
`
`8
`
`16
`
`2
`
`2
`
`1
`
`2
`
`1
`
`2
`
`2
`
`2
`
`2
`
`4
`
`4
`
`11/1/8
`
`11/1/9
`
`11/1/9
`
`11/2/8
`
`11/2/8
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`32 MB
`
`4M X 64
`
`64 Mbit
`
`2MX32
`
`32 MB
`
`4M X 64
`
`64 Mbit
`
`4MX16
`
`64 MB
`
`8M X 64
`
`64 Mbit
`
`4MX16
`
`64 MB
`
`8M X 64
`
`64 Mbit
`
`128 MB
`
`16M X 64
`
`64 Mbit
`
`16 MB
`
`2M X 72
`
`16 Mbit
`
`8MX8
`
`8MX8
`
`2MX8
`
`4
`
`4
`
`8
`
`8
`
`16
`
`9
`
`1
`
`2
`
`1
`
`2
`
`1
`
`4
`
`4
`
`4
`
`4
`
`2
`
`12/2/8
`
`12/2/8
`
`12/2/9
`
`12/2/9
`
`11/1/9
`
`12
`
`13
`
`14
`
`15
`
`16
`
`32 MB
`
`4M X 72
`
`16 Mbit
`
`64 MB
`
`8M X 72
`
`64 Mbit
`
`128 MB
`
`16M X 72
`
`64 Mbit
`
`2MX8
`
`8MX8
`
`8MX8
`
`8 MB
`
`1M X 72
`
`16 Mbit
`
`1MX16
`
`16 MB
`
`2M X 72
`
`16 Mbit
`
`1MX16
`
`4M X 72
`
`64 Mbit
`
`4MX16
`
`18
`
`9
`
`18
`
`5
`
`10
`
`5
`
`2
`
`1
`
`2
`
`1
`
`2
`
`1
`
`2
`
`4
`
`4
`
`2
`
`2
`
`4
`
`11/1/9
`
`12/2/9
`
`12/2/9
`
`11/1/8
`
`11/1/8
`
`12/2/8
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`32 MB
`
`64 MB
`
`8M X 72
`
`64 Mbit
`
`4MX16
`
`256 MB
`
`32M X 64
`
`128 Mbit
`
`16MX8
`
`256 MB
`
`32M X 72
`
`128 Mbit
`
`16MX8
`
`512 MB
`
`64M X 64
`
`256 Mbit
`
`32MX8
`
`512 MB
`
`64M X 72
`
`256 Mbit
`
`32MX8
`
`10
`
`16
`
`18
`
`16
`
`18
`
`2
`
`2
`
`2
`
`2
`
`2
`
`4
`
`4
`
`4
`
`4
`
`4
`
`12/2/8
`
`12/2/10
`
`12/2/10
`
`13/2/10
`
`13/2/10
`
`Note 1: Modules constructed using x 4 bit SDRAMs are not supported (due to loading on select signals).
`Note 2: Modules constructed using x 32 bit SDRAMs are still under investigation. Additional information will be released when
`
`it becomes available.
`
`Feb., 1998
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` PC SDRAM Unbuffered DIMM Specification
`
`Table 3: SDRAM Mixed-Mode Module Configurations
`
`DIMM
`Capacity
`24 MB
`
`48 MB
`
`24 MB
`
`48 MB
`
`96 MB
`
`Config #
`
`1
`
`2
`
`3
`
`4
`
`5
`
`Note:
`Note:
`
`# of
`SDRAM
`SDRAM
`DIMM
`SDRAMs
`Organization
`density
`Organization
`8
`2MX8
`16 Mbit
`2M X 64 +
`4
`1MX16
`16 Mbit
`1M X 64
`4
`4MX16
`64 Mbit
`4M X 64 +
`8
`2MX8
`16 Mbit
`2M X 64
`9
`2MX8
`16 Mbit
`2M X 72 +
`5
`1MX16
`16 Mbit
`1M X72
`5
`4MX16
`64 Mbit
`4M X 72 +
`9
`2MX8
`16 Mbit
`2M X72
`9
`8MX8
`64 Mbit
`8M X 72 +
`5
`4MX16
`64 Mbit
`4M X 72
`Modules constructed using x 4 bit SDRAMs are not supported (due to loading on select signals).
`Modules constructed using mixed configurations of x8 and x16 SDRAMs are still under investigation. Additional
`information will be released when it becomes available.
`
`# of Rows
`of SDRAM
`2
`
`2
`
`2
`
`2
`
`2
`
`Banks in
`SDRAM
`2
`2
`4
`2
`2
`2
`4
`2
`4
`4
`
`# Address bits
`row/bank/col
`11/1/9
`11/1/8
`12/2/8
`11/1/9
`11/1/9
`11/1/8
`12/2/8
`11/1/9
`12/2/9
`12/2/8
`
`Design Stuffing Options
`
`For the purpose of minimizing the total number of card designs that need to be generated, most Intel
`reference designs are being done double-sided in 6 layers and using this specification with the intent that
`these PCB designs will also work for single sided population and with or without stuffing the ECC
`devices. Therefore, there will be one card each designed for non-mixed mode configuration sets
`(1,2,15,16) (7,8,17,18) (3,4,11,12) (9,10,13,14). DIMM designs generated outside of Intel using the
`DIMM specification may opt not to do the same if cost or other considerations make it undesirable.
`
`Distinction between “banks”
`
`This document refers to two types of “banks”. One type relates to the banks of memory internal to the
`SDRAM component (two or four). The other type relates to the banks of SDRAM on a DIMM, also
`referred to as “rows”. The number of rows is the number of sets of SDRAMs on the DIMM that
`collectively make up 64 or 72 bits wide of data. When reading this document, please be aware of this
`distinction.
`
`Feb., 1998
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`

` PC SDRAM Unbuffered DIMM Specification
`
`2.0 Environmental Requirements
`
`The SDRAM DIMM shall be designed to operate within a personal computer cabinet in an office
`environment with limited capacity for heating and air conditioning. The temperature and humidity limits
`are listed below.
`Table 4: DIMM Temperature, Humidity & Barometric Pressure Requirements
`0 oC to +65 oC ambient
`Operating Temperature
`Operating Humidity
`10% to 90% relative humidity
`-50 oC to + 100 oC
`Storage Temperature
`Storage Humidity
`5% to 95% without condensation
`Barometric Pressure (operating & storage)
`105K - 69K Pascal (up to 9,850 ft.)
`
`Safety - UL Rating
`
`Printed circuit board to have a flammability rating of 94V-O Markings to include UL tractability
`requirements per UL Recognized Component Directory.
`
`Feb., 1998
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`

` PC SDRAM Unbuffered DIMM Specification
`
`3.0 Mechanical Design
`The following table and mechanical drawings give the specific dimensions and tolerances for a 168-pin
`DIMM.
`
`Table 5: DIMM Dimensions and Tolerances
`
`SYMBOL
`A
`
`DEFINITION
`Overall module height measured
`from Datum -B-.
`
`MIN
`25.27 mm
`
`NOM
`
`MAX
`38.23 mm
`
`The distance from Datum -B- to
`the centerline of the PWB
`alignment holes.
`
`3.00 mm BASIC
`
`NOTES
`Range is 25.4 mm (1.0”) to
`38.10 mm. (1.5”)
`These holes are not used by the
`next level of assembly. The
`dimensions are supplied for
`information only. If the holes
`are used in manufacturing they
`should be tightly toleranced.
`The recommended positional
`tolerance is 0.10 mm.
`
`A1
`
`A2
`
`A4
`
`A5
`
`A6
`A7
`
`A8
`
`b
`
`D1
`
`D2
`
`The distance from Datum -B- to
`the centerline of the latch holes.
`The distance from Datum -B- to
`the lower edge of the Component
`Area on the front side of the
`PWB.
`The distance from Datum -B- to
`the lower edge of the Component
`Area on the back side of the
`PWB.
`The distance from Datum -B- to
`the leading edge of the contact.
`The distance from the top of the
`module (DATUM B + height A)
`to the centerline of the top
`heatsink notch arc.
`The distance from the top of the
`module (DATUM B + height A)
`to the centerline of the bottom
`heatsink notch arc.
`The width of the plated
`input/output contact measured at
`the lateral midpoint of the
`contact.
`The overall length of the PWB.
`
`The longitudinal distance
`between the PWB machining
`alignment hole centers.
`
`17.80 mm BASIC
`
`4.00 mm
`
`4.00 mm
`
`0.05 mm
`
`0.35 mm
`
`The minimum distance prevents
`contact edge burrs.
`
`4.45mm
`BASIC
`
`8.25mm
`
`11.43mm
`
`0.95 mm
`
`1.00 mm
`
`1.05 mm
`
`133.22 mm
`
`133.37 mm
`
`133.52 mm
`
`126.20 mm
`
`127.35
`
`128.50 mm
`
`These holes are optional and
`may or may not be present. If
`they are present, they must be
`located as defined.
`
`Feb., 1998
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`

` PC SDRAM Unbuffered DIMM Specification
`
`Table 6: DIMM Dimensions and Tolerances (continued)
`
`SYMBOL
`e
`
`e1
`
`e2
`
`e3
`
`e4
`
`e5
`
`H
`
`L
`N
`
`T
`
`T1
`
`aaa
`
`bbb
`
`ccc
`
`ddd
`
`DEFINITION
`The pitch or distance between
`centerlines of the contacts
`The distance between the
`centerlines of Contact 1 and 84.
`
`The distance between the
`centerlines of Contact 85 and
`168.
`The distance between the
`centerlines of Contact 1 and the
`contact located at the immediate
`left of the left key zone when
`viewing contact 1 side.
`The distance between the
`centerlines of the contact at the
`immediate right of the left key
`zone and the contact at the
`immediate left of the center key
`zone when viewing contact 1
`side.
`The distance between the
`centerlines of the contact located
`at the immediate right of the
`center key zone and contact 84.
`The diameter of the PWB
`machined alignment holes.
`The distance from Datum -B- to
`the top edge of the plated contact.
`The total number of contacts.
`The thickness of the PCB
`including the contact metalization
`and plating.
`The overall thickness of the PWB
`with the components mounted.
`The overall thickness is measured
`from the highest component on
`the front side to the highest
`component on the backside.
`The positional tolerance for the
`overall body length D1.
`The straightness tolerance for the
`card thickness including the
`metalized contacts. This callout
`applies to the zone defined by
`A4, A5 and D1.
`The positional tolerance for the
`pattern of contacts with regard to
`primary Datum -A-.
`The positional tolerance for the
`individual contact width b with
`regard to the theoretical
`centerline of the contact defined
`by basic dimension e.
`
`MIN
`
`NOM
`1.27 mm BASIC
`
`MAX
`
`NOTES
`
`115.57 mm
`
`115.57 mm
`
`11.43 mm
`
`36.83 mm
`
`54.61 mm
`
`2.90 mm
`
`3.00 mm
`
`3.10 mm
`
`2.30 mm
`
`2.50 mm
`168
`
`2.70 mm
`
`1.17 mm
`
`1.27 mm
`
`1.37 mm
`
`4.33 mm
`
`The distance between the
`centerlines of contact 1 and
`10.
`
`The distance between the
`centerlines of contact 11
`and 40.
`
`The distance between the
`centerlines of contact 41
`and 84.
`The machined alignment
`holes are optional.
`
`aaa = 0.15 mm @ Maximum Material Condition
`
`0.40 mm
`
`bbb = 0.3% x D1 rounded
`to a two decimal place hard
`metric value.
`
`ccc = 0.10 mm @ Least Material Condition
`
`ddd = 0.05 mm @ Least Material Condition
`
`Feb., 1998
`
` 12 of 47
`
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`
`

`

`A8
`2X
`
`A
`
`A7
`2X
`
`A2
`2X
`
`- B -
`
`A1
`2X
`CONTACT 1 ID
`
`CONTACT 1
`
` PC SDRAM Unbuffered DIMM Specification
`
`D1
`M
`aaa
`
`SABC
`
`2.26 TYP
`
`3.00 TYP
`
`4
`
`(DATUM -A-)
`
`2.26 TYP
`3.00 TYP
`
`4
`
`COMPONENT AREA
`(FRONT)
`
`1
`
`DETAIL A
`DETAIL D
`LEFT KEY ZONE
`
`DETAIL C
`CENTER KEY ZONE
`
`CONTACT 84
`2X
`SEE DETAIL B
`
`D2 / 2
`
`CONTACT 85
`
`D2
`
`OPTIONAL HOLES
`H
`2X
`M
`B
`0.10
`MA
`C
`CONTACT 168
`
`10
`
`2X
`SEE DETAIL E
`
`COMPONENT AREA
`(BACK)
`
`(DATUM -A-)
`
`Figure 1: DIMM Mechanical Drawing (1 of 5)
`
`Feb., 1998
`
` 13 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`(DATUM -A-)
`
`1
`
`e3
`
`LEFT KEY
` ZONE
`6.35
`
`e4
`
`CENTER KEY ZONE
`3.175
`6.35
`
`e5
`
`e1
`
`e2
`FRONT AND BACK CONTACT
`CENTERLINES ARE COINCIDENT
`
`Figure 2: DIMM Mechanical Drawing (2 of 5)
`
`(DATUM -A-)
`
`Feb., 1998
`
` 14 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`T1
`
`5
`
`9
`
`(2.26)
`
`RADIUS
`1.27 + 0.10
`
`A4
`
`A5
`
`5
`
`0.10
`
`M
`
`AC
`
`M B
`
`Note: No chamfer
`on leading edge
`
`- C -
`
`T
`
`6Mbbb
`
`END VIEW
`
`DETAIL E
`
`(3.00)
`
`FULL
`RADIUS
`
`4.00 + 0.10
`0.10
`M
`AC
`
`M B
`
`L
`
`162 X e
`
`168 X b
`L
`SABC
`L B
`
`ccc
`ddd
`
`DETAIL A
`
`A6
`
`8
`
`11
`
`Figure 3: DIMM Mechanical Drawing (3 of 5)
`
`DETAIL B
`
`Feb., 1998
`
` 15 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`CONTACT 40
`
`3.175
`(DATUM -A-)
`FULL R
`
`3.00
`3.25
`
`KEYWAY
`ZONE
`
`1.00
`
`CONTACT 41
`
`2.00 + 0.10
`L
`0.10
`SABC
`
`DETAIL C - CENTER KEY ZONE
`
`CONTACT 10
`
`KEYWAY
`ZONE
`
`1.00
`
`4.175
`
`FULL R
`
`3.00
`3.25
`
`CONTACT 11
`
`2.00 + 0.10
`L
`0.10
`SABC
`
`DETAIL D - LEFT KEY ZONE
`
`Figure 4: DIMM Mechanical Drawing (4 of 5)
`
`Feb., 1998
`
` 16 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`NOTES
`1 ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1994.
`2 TOLERANCES ON ALL DIMENSIONS +/- 0.13 UNLESS OTHERWISE
` SPECIFIED.
`
`3 ALL DIMENSIONS ARE IN MILLIMETERS.
`
`4 3.00 mm TYPICAL APPLIES TO BOTH 4.00 mm WIDE NOTCH LENGTH
` AND COMPONENT KEEPOUT AREA.
`
`5 DIMENSION APPLICABLE WHEN COMPONENTS MOUNTED ON BOTH
` SIDES.
`
`6 CARD THICKNESS APPLIES ACROSS THE CONTACTS AND INCLUDES
` PLATING AND/OR METALIZATION. STRAIGHTNESS CALLOUT APPLIES
` TO ZONE DEFINED BY A4, A5, AND D1.
`
`7 N IS THE TOTAL NUMBER OF CIRCUIT CONTACTS (PINS, LEADS,
` TABS OR PADS).
`8 LEADING EDGE OF CONTACT ZONE SHALL BE FREE OF BURRS AND
` EXTERNAL TIE BARS.
`
`9 THE MAXIMUM THICKNESS SHALL NOT EXCEED 4.33 mm.
`
`10 HEATSINK NOTCHES ARE OPTIONAL. DIMENSIONS ARE PROVIDED
` FOR REFERENCE IN CASE THEY ARE DESIRED.
`
`APPLICATION NOTES:
`11 PLATING FOR CONTACT PADS: GOLD PLATING 0.75 MICROMETER
` MINIMUM OVER NI PLATING 2 MICROMETERS MINIMUM.
`
`12 FOR OPTIMUM PERFORMANCE, IT IS RECOMMENDED THAT THE TIEBAR
` BE OFFSET FROM THE CENTERLINE OF THE PAD. ALSO, THE TIEBAR
` MAY BE AN INTERNAL LAYER, SO THE REMNANT CANNOT CAUSE
` CONTACT DAMAGE.
`
`Figure 5: DIMM Mechanical Drawing (5 of 5)
`
`Explanation of DIMM Keying
`
`All DIMMs generated from this spec should have two notches cut into the edge connection that convey
`information on the voltage of the DIMM and whether it is buffered or unbuffered. One notch should be
`positioned between DIMM pins 10 and 11 and should be closer in proximity to pin 11. This signifies that
`the DIMM is Unbuffered SDRAM/DRAM. The other notch should be positioned between DIMM pins 40
`and 41 and should be centered between the two pins. This signifies that the DIMM operates using a Vddq
`voltage of 3.3 Volts. Please see the mechanical drawings above for exact dimensions and placement of
`these notches.
`
`Feb., 1998
`
` 17 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`4.0 Module Pinout
`The following table provides the 168-pin 64-bit and 72-bit unbuffered DIMM module connector pinouts.
`Note that the eight error detection and correction bits CB(0:7) are actually NC for the 64-bit pinout.
`Table 7: SDRAM DIMM pinout
`Pin#
`Signal
`Pin#
`Name
`Vss
`DQ0
`DQ1
`DQ2
`DQ3
`Vdd
`DQ4
`DQ5
`DQ6
`DQ7
`DQ8
`Vss
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`Vdd
`DQ14
`DQ15
`CB0
`CB1
`Vss
`NC
`NC
`Vdd
`/WE0
`DQMB0
`DQMB1
`/S0
`NC
`Vss
`A0
`A2
`A4
`A6
`A8
`A10 (AP)
`BA1
`Vdd
`Vdd
`CK0
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`
`43
`44
`45
`46
`47
`48
`49
`50
`51
`52
`53
`54
`55
`56
`57
`58
`59
`60
`61
`62
`63
`64
`65
`66
`67
`68
`69
`70
`71
`72
`73
`74
`75
`76
`77
`78
`79
`80
`81
`82
`83
`84
`
`Signal
` Name
`Vss
`NC
`/S2
`DQMB2
`DQMB3
`NC
`Vdd
`NC
`NC
`CB2
`CB3
`Vss
`DQ16
`DQ17
`DQ18
`DQ19
`Vdd
`DQ20
`NC
`NC
`CKE1
`Vss
`DQ21
`DQ22
`DQ23
`Vss
`DQ24
`DQ25
`DQ26
`DQ27
`Vdd
`DQ28
`DQ29
`DQ30
`DQ31
`Vss
`CK2
`NC
`WP
`SDA
`SCL
`Vdd
`
`Pin#
`
`85
`86
`87
`88
`89
`90
`91
`92
`93
`94
`95
`96
`97
`98
`99
`100
`101
`102
`103
`104
`105
`106
`107
`108
`109
`110
`111
`112
`113
`114
`115
`116
`117
`118
`119
`120
`121
`122
`123
`124
`125
`126
`
`Signal
`Name
`Vss
`DQ32
`DQ33
`DQ34
`DQ35
`Vdd
`DQ36
`DQ37
`DQ38
`DQ39
`DQ40
`Vss
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`Vdd
`DQ46
`DQ47
`CB4
`CB5
`Vss
`NC
`NC
`Vdd
`/CAS
`DQMB4
`DQMB5
`/S1
`/RAS
`Vss
`A1
`A3
`A5
`A7
`A9
`BA0
`A11
`Vdd
`CK1
`A12
`
`Pin#
`
`Signal Name
`
`127
`128
`129
`130
`131
`132
`133
`134
`135
`136
`137
`138
`139
`140
`141
`142
`143
`144
`145
`146
`147
`148
`149
`150
`151
`152
`153
`154
`155
`156
`157
`158
`159
`160
`161
`162
`163
`164
`165
`166
`167
`168
`
`Vss
`CKE0
`/S3
`DQMB6
`DQMB7
`A13
`Vdd
`NC
`NC
`CB6
`CB7
`Vss
`DQ48
`DQ49
`DQ50
`DQ51
`Vdd
`DQ52
`NC
`NC
`NC
`Vss
`DQ53
`DQ54
`DQ55
`Vss
`DQ56
`DQ57
`DQ58
`DQ59
`Vdd
`DQ60
`DQ61
`DQ62
`DQ63
`Vss
`CK3
`NC
`SA0
`SA1
`SA2
`Vdd
`
` Note: NC = Not Connected
`
`Feb., 1998
`
` 18 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`5.0 SDRAM DIMM Block Diagrams
`
`DQM4
`DQ(39:32)
`
`DQM5
`DQ(47:40)
`
`DQM6
`DQ(55:48)
`
`DQM7
`DQ(63:56)
`
`CKE0
`
`/RAS
`/CAS
`/WE
`A(10:0)
`
`D2
`
`D3
`
`10
`
`10
`
`10
`
`10
`
`CKE: SDRAM D0 - D3
`
`/RAS: SDRAM D0 - D3
`/CAS: SDRAM D0 - D3
`/WE: SDRAM D0 - D3
`A(10:0): SDRAM D0 - D3
`
`BA0, BA1, A11, A12 WIRING TABLE
`DIMM
`Connector
`Signal
`BA0
`BA1
`A11
`A12
`
`SDRAM D0- D3
`Signal
`
`BA0/A11
`not used
`not used
`not used
`
`SDRAM
`TYPE
`
`16 Mbit
`
`/S0
`
`DQM0
`DQ(7:0)
`
`DQM1
`DQ(15:8)
`
`/S2
`
`DQM2
`DQ(23:16)
`
`DQM3
`DQ(31:24)
`
`SCL
`
`SA2
`SA1
`SA0
`
`D0
`
`D1
`
`10
`
`10
`
`10
`
`10
`
`SERIAL PD
`
`SDA
`
`WP
`
`47K
`
`* CLOCK WIRING
`
`LOAD
`
`2 SDRAMS + 15pF cap
`TERMINATION
`2 SDRAMS + 15pF cap
`TERMINATION
`
`CLOCK
`INPUT
`
`CK0
`CK1
`CK2
`CK3
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`VDD
`
`VSS
`
`SDRAM D0 - D3
`Recommended bypass:
`two 0.33uF and one 0.1uF
`per SDRAM device
`SDRAM D0 - D3
`
`64 Mbit
`4 Bank
`
`BA0
`BA1
`A11
`A12
`
`BA0/A13
`BA1/A12
`A11
`not used
`
`Alternately, DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6, and 3 with 7 in x16 SDRAMs to obtain most
`advantagous board layout (i.e. to obtain minimum DQ(63:0) trace lengths).
`
`Figure 6: 64-bit non-ECC DIMM Block Diagram (1 Row, x16 SDRAMs)
`
`Feb., 1998
`
` 19 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`DQM4
`DQ(39:32)
`
`DQM5
`DQ(47:40)
`
`DQM6
`DQ(55:48)
`
`DQM7
`DQ(63:56)
`
`CKE1
`CKE0
`
`/RAS
`/CAS
`/WE
`A(10:0)
`
`D2
`
`D6
`
`10
`
`10
`
`10
`
`D3
`
`D7
`
`10
`
`Vcc
`
`10K
`
`CKE: SDRAM D4 - D7
`CKE: SDRAM D0 - D3
`
`/RAS: SDRAM D0 - D7
`/CAS: SDRAM D0 - D7
`/WE: SDRAM D0 - D7
`A(10:0): SDRAM D0 - D7
`
`BA0, BA1, A11, A12 WIRING TABLE
`DIMM
`Connector
`Signal
`BA0
`BA1
`A11
`A12
`
`SDRAM D0- D7
`Signal
`
`BA0/A11
`not used
`not used
`not used
`
`SDRAM
`TYPE
`
`16 Mbit
`
`/S0
`
`DQM0
`DQ(7:0)
`
`DQM1
`DQ(15:8)
`
`/S2
`
`DQM2
`DQ(23:16)
`
`DQM3
`DQ(31:24)
`
`SCL
`
`SA2
`SA1
`SA0
`
`/S1
`
`D0
`
`D4
`
`/S3
`
`D1
`
`D5
`
`10
`
`10
`
`10
`
`10
`
`SERIAL PD
`
`SDA
`
`WP
`
`47K
`
`* CLOCK WIRING
`
`LOAD
`
`2 SDRAMS + 15pF cap
`2 SDRAMS + 15pF cap
`2 SDRAMS + 15pF cap
`2 SDRAMS + 15pF cap
`
`CLOCK
`INPUT
`
`CK0
`CK1
`CK2
`CK3
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`VDD
`
`VSS
`
`SDRAM D0 - D7
`Recommended bypass:
`two 0.33uF and one 0.1uF
`per SDRAM device
`SDRAM D0 - D7
`
`64 Mbit
`4 Bank
`
`BA0
`BA1
`A11
`A12
`
`BA0/A13
`BA1/A12
`A11
`not used
`
`Alternately, DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6, and 3 with 7 in x16 SDRAM devices to obtain
`most advantagous board layout (i.e. to obtain minimum DQ(63:0) trace lengths).
`
`Figure 7: 64-bit non-ECC DIMM Block Diagram (2 Rows, x16 SDRAMs)
`
`Feb., 1998
`
` 20 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`10
`
`10
`
`10
`
`10
`
`D0
`
`D1
`
`D2
`
`D3
`
`SERIAL PD
`
`/S0
`
`DQM0
`DQ(7:0)
`
`DQM1
`DQ(15:8)
`
`/S2
`
`DQM2
`DQ(23:16)
`
`DQM3
`DQ(31:24)
`
`SCL
`
`SA2
`SA1
`SA0
`
`DQM4
`DQ(39:32)
`
`DQM5
`DQ(47:40)
`
`DQM6
`DQ(55:48)
`
`DQM7
`DQ(63:56)
`
`10
`
`10
`
`10
`
`10
`
`D4
`
`D5
`
`D6
`
`D7
`
`SDA
`
`WP
`
`47K
`
`CKE0
`
`/RAS
`/CAS
`/WE
`A(10:0)
`
`CKE: SDRAM D0 - D7
`
`/RAS: SDRAM D0 - D7
`/CAS: SDRAM D0 - D7
`/WE: SDRAM D0 - D7
`A(10:0): SDRAM D0 - D7
`
`BA0, BA1, A11, A12 WIRING TABLE
`DIMM
`Connector
`Signal
`BA0
`BA1
`A11
`A12
`
`SDRAM D0-D7
`Signal
`
`BA0/A11
`not used
`not used
`not used
`
`SDRAM
`TYPE
`
`16 Mbit
`
`* CLOCK WIRING
`
`LOAD
`
`4 SDRAMs + 3.3pF cap
`TERMINATION
`4 SDRAMs + 3.3pF cap
`TERMINATION
`
`CLOCK
`INPUT
`
`CK0
`CK1
`CK2
`CK3
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`VDD
`
`VSS
`
`SDRAM D0 - D7
`Recommended bypass:
`One 0.33uF and one 0.1uF
`per SDRAM device
`SDRAM D0 - D7
`
`64 Mbit
`4 Bank
`
`BA0
`BA1
`A11
`A12
`
`BA0/A13
`BA1/A12
`A11
`not used
`
`Figure 8: 64 bit non-ECC DIMM Block Diagram (1 Row x8 SDRAMs)
`
`Feb., 1998
`
` 21 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`/S0
`
`DQM0
`DQ(7:0)
`
`DQM1
`DQ(15:8)
`
`/S2
`
`DQM2
`DQ(23:16)
`
`DQM3
`DQ(31:24)
`
`SCL
`
`SA2
`SA1
`SA0
`
`D0
`
`D1
`
`/S1
`
`/S3
`
`D8
`
`D9
`
`DQM4
`DQ(39:32)
`
`DQM5
`DQ(47:40)
`
`D2
`
`D10
`
`D3
`
`D11
`
`DQM6
`DQ(55:48)
`
`DQM7
`DQ(63:56)
`
`SERIAL PD
`
`10
`
`10
`
`10
`
`10
`
`10
`
`10
`
`10
`
`10
`
`Vcc
`
`10K
`
`D4
`
`D12
`
`D5
`
`D13
`
`D6
`
`D7
`
`D14
`
`D15
`
`SDA
`
`WP
`
`47K
`
`CKE1
`CKE0
`
`/RAS
`/CAS
`/WE
`A(10:0)
`
`CKE: SDRAM D8 - D15
`CKE: SDRAM D0 - D7
`
`/RAS: SDRAM D0 - D15
`/CAS: SDRAM D0 - D15
`/WE: SDRAM D0 - D15
`A(10:0): SDRAM D0 - D15
`
`BA0, BA1, A11, A12 WIRING TABLE
`DIMM
`Connector
`Signal
`BA0
`BA1
`A11
`A12
`
`SDRAM D0-D15
`Signal
`
`BA0/A11
`not used
`not used
`not used
`
`SDRAM
`TYPE
`
`16 Mbit
`
`* CLOCK WIRING
`
`LOAD
`
`4 SDRAMs + 3.3pF cap
`4 SDRAMs + 3.3pF cap
`4 SDRAMs + 3.3pF cap
`4 SDRAMs + 3.3pF cap
`
`CLOCK
`INPUT
`
`CK0
`CK1
`CK2
`CK3
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`VDD
`
`VSS
`
`SDRAM D0 - D15
`Recommended bypass:
`One 0.33uF and one 0.1uF
`per SDRAM device
`SDRAM D0 - D15
`
`64 Mbit
`4 Bank
`
`BA0
`BA1
`A11
`A12
`
`BA0/A13
`BA1
`A11
`A12
`
`Figure 9: 64-bit non-ECC DIMM Block Diagram (2 Rows x8 SDRAMs)
`
`Feb., 1998
`
` 22 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`DQM2
`DQ(23:16)
`
`DQM3
`DQ(31:24)
`
`DQM6
`DQ(55:48)
`
`DQM7
`DQ(63:56)
`
`CKE0
`
`/RAS
`/CAS
`/WE
`A(10:0)
`
`D1
`
`10
`
`10
`
`10
`
`10
`
`CKE: SDRAM D0 - D1
`
`/RAS: SDRAM D0 - D1
`/CAS: SDRAM D0 - D1
`/WE: SDRAM D0 - D1
`A(10:0): SDRAM D0 - D1
`
`/S2
`
`/S0
`
`DQM0
`DQ(7:0)
`
`DQM1
`DQ(15:8)
`
`DQM4
`DQ(39:32)
`
`DQM5
`DQ(47:40)
`
`SCL
`
`SA2
`SA1
`SA0
`
`D0
`
`10
`
`10
`
`10
`
`10
`
`SERIAL PD
`
`SDA
`
`WP
`
`47K
`
`* CLOCK WIRING
`
`LOAD
`
`2 SDRAMS + TBD pF cap
`TERMINATION
`TERMINATION
`TERMINATION
`
`CLOCK
`INPUT
`
`CK0
`CK1
`CK2
`CK3
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`VDD
`
`VSS
`
`SDRAM D0 - D1
`Recommended bypass:
`two 0.33uF and one 0.1uF
`per SDRAM device
`SDRAM D0 - D1
`
`BA0, BA1, A11, A12 WIRING TABLE
`DIMM
`Connector
`Signal
`BA0
`BA1
`A11
`A12
`
`SDRAM D0- D1
`Signal
`
`BA0/A12
`BA1/A11
`not used
`not used
`
`SDRAM
`TYPE
`
`64 Mbit
`4 Bank
`
`Figure 10: 64 bit non-ECC Block Diagram (1 Row x 32 SDRAMs)
`Note:
`Modules constructed using x 32 bit SDRAMs are still under investigation. Additional information will be released when
`
`it becomes available.
`
`Feb., 1998
`
` 23 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`10
`
`10
`
`10
`
`10
`
`Vcc
`
`/S3
`/S2
`
`DQM2
`DQ(23:16)
`
`DQM3
`DQ(31:24)
`
`DQM6
`DQ(55:48)
`
`DQM7
`DQ(63:56)
`
`CKE1
`CKE0
`
`/RAS
`/CAS
`/WE
`A(10:0)
`
`D1
`
`D3
`
`CKE: SDRAM D2 - D3
`CKE: SDRAM D0 - D1
`
`/RAS: SDRAM D0 - D1
`/CAS: SDRAM D0 - D1
`/WE: SDRAM D0 - D1
`A(10:0): SDRAM D0 - D1
`
`/S1
`/S0
`
`DQM0
`DQ(7:0)
`
`DQM1
`DQ(15:8)
`
`DQM4
`DQ(39:32)
`
`DQM5
`DQ(47:40)
`
`SCL
`
`SA2
`SA1
`SA0
`
`D0
`
`D2
`
`10
`
`10
`
`10
`
`10
`
`SERIAL PD
`
`SDA
`
`WP
`
`47K
`
`* CLOCK WIRING
`
`LOAD
`
`2 SDRAMS + TBD pF cap
`2 SDRAMS + TBD pF cap
`TERMINATION
`TERMINATION
`
`CLOCK
`INPUT
`
`CK0
`CK1
`CK2
`CK3
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`VDD
`
`VSS
`
`SDRAM D0 - D3
`Recommended bypass:
`two 0.33uF and one 0.1uF
`per SDRAM device
`SDRAM D0 - D3
`
`BA0, BA1, A11, A12 WIRING TABLE
`DIMM
`Connector
`Signal
`BA0
`BA1
`A11
`A12
`
`SDRAM D0- D1
`Signal
`
`BA0/A12
`BA1/A11
`not used
`not used
`
`SDRAM
`TYPE
`
`64 Mbit
`4 Bank
`
`Figure 11: 64-bit non-ECC Block Diagram (2 Rows x32 SDRAMs)
`Note:
`Modules constructed using x 32 bit SDRAMs are still under investigation. Additional information will be released when
`
`it becomes available.
`
`Feb., 1998
`
` 24 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`D0
`
`D1
`
`D2
`
`D3
`
`D4
`
`10
`
`10
`
`10
`
`10
`
`10
`
`DQM4
`DQ(39:32)
`
`DQM5
`DQ(47:40)
`
`DQM6
`DQ(55:48)
`
`DQM7
`DQ(63:56)
`
`10
`
`10
`
`10
`
`10
`
`D5
`
`D6
`
`D7
`
`D8
`
`SERIAL PD
`
`SDA
`
`WP
`
`47K
`
`CKE0
`
`/RAS
`/CAS
`/WE
`A(10:0)
`
`CKE: SDRAM D0 - D8
`
`/RAS: SDRAM D0 - D8
`/CAS: SDRAM D0 - D8
`/WE: SDRAM D0 - D8
`A(10:0): SDRAM D0 - D8
`
`/S0
`
`DQM0
`DQ(7:0)
`
`DQM1
`DQ(15:8)
`
`CB(7:0)
`
`/S2
`
`DQ(23:16)
`DQM2
`
`DQ(31:24)
`DQM3
`
`SCL
`
`SA2
`SA1
`SA0
`
`BA0, BA1, A11, A12 WIRING TABLE
`DIMM
`Connector
`Signal
`BA0
`BA1
`A11
`A12
`
`SDRAM D0-D8
`Signal
`
`BA0/A11
`not used
`not used
`not used
`
`SDRAM
`TYPE
`
`16 Mbit
`
`* CLOCK WIRING
`
`LOAD
`
`5 SDRAMs
`TERMINATION
`4 SDRAMs + 3.3pF cap
`TERMINATION
`
`CLOCK
`INPUT
`
`CK0
`CK1
`CK2
`CK3
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`VDD
`
`VSS
`
`SDRAM D0 - D8
`Recommended bypass:
`One 0.33uF and one 0.1uF
`per SDRAM device
`SDRAM D0 - D8
`
`64 Mbit
`4 Bank
`
`BA0
`BA1
`A11
`A12
`
`BA0/A13
`BA1/A12
`A11
`not used
`
`Figure 12: 72-Bit ECC SDRAM DIMM Block Diagram (1 row x8 SDRAMs)
`
`Feb., 1998
`
` 25 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`10
`
`10
`
`10
`
`10
`
`10
`
`/S0
`
`DQM0
`DQ(7:0)
`
`DQM1
`DQ(15:8)
`
`CB(7:0)
`
`/S2
`
`DQM2
`DQ(23:16)
`
`DQM3
`DQ(31:24)
`
`SCL
`
`SA2
`SA1
`SA0
`
`/S1
`
`D0
`
`D1
`
`D2
`
`D9
`
`DQM4
`DQ(39:32)
`
`DQM5
`DQ(47:40)
`
`D10
`
`D11
`
`D5
`
`D14
`
`D6
`
`D15
`
`10
`
`10
`
`Note: SDRAM D11 DQM input MUST
`be wired to DQM5.
`
`/S3
`
`D3
`
`D12
`
`D4
`
`D13
`
`DQM6
`DQ(55:48)
`
`DQM7
`DQ(63:56)
`
`D7
`
`D8
`
`D16
`
`D17
`
`10
`
`10
`Vcc
`
`10K
`
`SERIAL PD
`
`SDA
`
`WP
`
`47K
`
`CKE1
`CKE0
`
`/RAS
`/CAS
`/WE
`A(10:0)
`
`CKE: SDRAM D9 - D17
`CKE: SDRAM D0 - D8
`
`/RAS: SDRAM D0 - D17
`/CAS: SDRAM D0 - D17
`/WE: SDRAM D0 - D17
`A(10:0): SDRAM D0 - D17
`
`BA0, BA1, A11, A12 WIRING TABLE
`DIMM
`Connector
`Signal
`BA0
`BA1
`A11
`A12
`
`SDRAM D0-D17
`Signal
`
`BA0/A11
`not used
`not used
`not used
`
`SDRAM
`TYPE
`
`16 Mbit
`
`* CLOCK WIRING
`
`LOAD
`
`5 SDRAMs
`5 SDRAMs
`4 SDRAMs + 3.3pF cap
`4 SDRAMs + 3.3pF cap
`
`CLOCK
`INPUT
`
`CK0
`CK1
`CK2
`CK3
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`VDD
`
`VSS
`
`SDRAM D0 - D17
`Recommended bypass:
`One 0.33uF and one 0.1uF
`per SDRAM device
`SDRAM D0 - D17
`
`64 Mbit
`4 Bank
`
`BA0
`BA1
`A11
`A12
`
`BA0/A13
`BA1
`A11
`A12
`
`Figure 13: 72-Bit ECC SDRAM DIMM Block Diagram (2 rows x8 SDRAMs)
`
`Feb., 1998
`
` 26 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`/S0
`
`DQM0
`DQ(7:0)
`
`DQM1
`DQ(15:8)
`
`CB(7:0)
`
`/S2
`
`DQM2
`DQ(23:16)
`
`DQM3
`DQ(31:24)
`
`10
`
`10
`
`10
`
`D0
`
`D1
`
`10
`
`D2
`
`DQM4
`DQ(39:32)
`
`DQM5
`DQ(47:40)
`
`DQM6
`DQ(55:48)
`
`DQM7
`DQ(63:56)
`
`10
`
`10
`
`10
`
`10
`
`D3
`
`D4
`
`10
`SERIAL PD
`
`SCL
`
`SA2
`SA1
`SA0
`
`SDA
`
`WP
`
`47K
`
`CKE0
`
`/RAS
`/CAS
`/WE
`A(10:0)
`
`CKE: SDRAM D0 - D4
`
`/RAS: SDRAM D0 - D4
`/CAS: SDRAM D0 - D4
`/WE: SDRAM D0 - D4
`A(10:0): SDRAM D0 - D4
`
`* CLOCK WIRING
`
`LOAD
`
`3 SDRAMS + 10pF cap
`TERMINATION
`2 SDRAMS + 15pF cap
`TERMINATION
`
`CLOCK
`INPUT
`
`CK0
`CK1
`CK2
`CK3
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`VDD
`
`VSS
`
`SDRAM D0 - D4
`Recommended bypass:
`two 0.33uF and one 0.1uF
`per SDRAM device
`SDRAM D0 - D4
`
`BA0, BA1, A11, A12 WIRING TABLE
`DIMM
`Connector
`Signal
`BA0
`BA1
`A11
`A12
`
`SDRAM D0- D4
`Signal
`
`BA0/A11
`not used
`not used
`not used
`
`SDRAM
`TYPE
`
`16 Mbit
`
`64 Mbit
`4 Bank
`
`BA0
`BA1
`A11
`A12
`
`BA0/A13
`BA1/A12
`A11
`not used
`
`Alternately, DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6, and 3 with 7 in x16 SDRAMs to
`obtain most advantagous board layout (i.e. to obtain minimum DQ(63:0) trace lengths).
`
`Figure 14: 72-Bit ECC SDRAM DIMM Block Diagram (1 row x16 SDRAMs)
`
`Feb., 1998
`
` 27 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`/S1
`
`D0
`
`D5
`
`DQM4
`DQ(39:32)
`
`DQM5
`DQ(47:40)
`
`10
`
`10
`
`D3
`
`D8
`
`D1
`
`D6
`
`Note: SDRAM D6 DQM input MUST
`be wired to DQM5.
`
`/S3
`
`D2
`
`D7
`
`DQM6
`DQ(55:48)
`
`DQM7
`DQ(63:56)
`
`CKE1
`CKE0
`
`/RAS
`/CAS
`/WE
`A(10:0)
`
`10
`
`D4
`
`D9
`
`10
`Vcc
`
`10K
`
`CKE: SDRAM D5 - D9
`CKE: SDRAM D0 - D4
`
`/RAS: SDRAM D0 - D9
`/CAS: SDRAM D0 - D9
`/WE: SDRAM D0 - D9
`A(10:0): SDRAM D0 - D9
`
`BA0, BA1, A11, A12 WIRING TABLE
`DIMM
`Connector
`Signal
`BA0
`BA1
`A11
`A12
`
`SDRAM D0- D7
`Signal
`
`BA0/A11
`not used
`not used
`not used
`
`SDRAM
`TYPE
`
`16 Mbit
`
`64 Mbit
`4 Bank
`
`BA0
`BA1
`A11
`A12
`
`BA0/A13
`BA1/A12
`A11
`not used
`
`10
`
`10
`
`10
`
`10
`
`10
`
`/S0
`
`DQM0
`DQ(7:0)
`
`DQM1
`DQ(15:8)
`
`CB(7:0)
`
`/S2
`
`DQM2
`DQ(23:16)
`
`DQM3
`DQ(31:24)
`
`SCL
`
`SA2
`SA1
`SA0
`
`SERIAL PD
`
`SDA
`
`WP
`
`47K
`
`* CLOCK WIRING
`
`LOAD
`
`3 SDRAMS + 10pF cap
`3 SDRAMS + 10pF cap
`2 SDRAMS + 15pF cap
`2 SDRAMS + 15pF cap
`
`CLOCK
`INPUT
`
`CK0
`CK1
`CK2
`CK3
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`VDD
`
`VSS
`
`SDRAM D0 - D9
`Recommended bypass:
`two 0.33uF and one 0.1uF
`per SDRAM device
`SDRAM D0 - D9
`
`Alternately, DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6, and 3 with 7 in x16 SDRAM devices
`to obtain most advantagous board layout (i.e. to obtain minimum DQ(63:0) trace lengths).
`
`Figure 15: 72-Bit ECC SDRAM DIMM Block Diagram (2 rows x16 SDRAMs)
`
`Feb., 1998
`
` 28 of 47
`
` Revision 1.0
`
`

`

` PC SDRAM Unbuffered DIMM Specification
`
`/S1
`
`/S3
`
`D0
`
`D1
`
`SERIAL PD
`
`10
`
`10
`
`10
`
`10
`
`/S0
`
`DQM0
`DQ(7:0)
`
`DQM1
`DQ(15:8)
`
`/S2
`
`DQM2
`DQ(23:16)
`
`DQM3
`DQ(31:24)
`
`SCL
`
`SA2
`SA1
`SA0
`
`D4
`
`D5
`
`D6
`
`D7
`
`DQM4
`DQ(39:32)
`
`DQM5
`DQ(47:40)
`
`DQM6
`DQ(55:48)
`
`DQM7
`DQ(63