`Bechtolsheim et al.
`
`11»
`
`US005973951A
`
`(11) Patent Number:
`
`[45] Date of Patent:
`
`S97S901
`*Oct. 26, 1999
`
`[54] SINGLE IN-LINE MEMORY MODULE
`
`FOREIGN PATENT DOCUMENTS
`
`[75]
`
`Inventors: Andreas Bechtolsheim, Stanford;
`Edward Frank, Portola Valley; James
`Testa, Mountain View; Shawn Storm,
`Mt. View, all of Calif.
`
`[73] Assignee: Sun Microsystems, Inc., Palo Alto,
`Calif.
`
`(188 828 A2
`.
`European Pat. Off.
`7/1986
`11/1987
`0 246 025 Bl
`.
`European Pat. Off.
`10/1988
`0 287 274 A2
`European Pat. Off. .
`10/1990
`0 394 935 A2
`European Pat. Off.
`.
`11/1990
`0398 188 A2
`European Pat. Off. .
`6/1991
`0 434 543 AQ
`European Pat. Off. .
`10/1991
`0484062 Al
`European Pat. OF,
`.
`3/1992
`0476 685 A2
`European Pat. Off. .
`0571092 A2
`4/1993
`European Pat. Off,
`.
`59-144155
`6/1984
`Japan .
`[*] Notice:—This patent issued on a continued pros-
`62-155546
`7/1987
`Japan .
`ecution application filed under 37 CFR
`63-1970835
` 8/L9RS
`Japan.
`1,53(d), and is subject to the twenty year
`63-137957
`9/1988
`Japan .
`patent
`term provisions of 35 U.S.C.
`1258466
`10/1989
`Japan .
`1305562
`12/1989
`154(a)(2).
`Japan .
`02310644
`12/1990
`Japan .
`3248896
`11/1991
`Japan.
`Japan .
`3262055
`11/1991
`2 223 335
`4/1990 United Kingdom .
`OTHER PUBLICATIONS
`
`This patent is subject to a terminal dis-
`claimer.
`
`[21] Appl. No.: 08/878,705
`
`[22]
`
`Filed:
`
`Jun. 19, 1997
`
`Related U.S, Application Data
`
`[63] Continuation of application No. 08/643,094, May2, 1996,
`abandoned, which is a continuation of application No.
`08/473,073, Jun. 7, 1995, Pat. No. 5,532,954, which is a
`continuation of application No, 08/345,477, Nov. 28, 1994,
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`No. 08/279,824, Jul. 25, 1994, Pat. No. 5,383,148, which is
`a continuation of application No. 08/115,438, Sep. 1, 1993,
`abandoned, which is a continuation of application No.
`07/886,413, May 19, 1992, Pat. No, 5,270,964,
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`[SL] Unt. Cho cccccsecsveecnsusersnennmneaene GLC 13/00
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`ABSTRACT
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`Top, bottom and side views of Atari CX853 Memory Mod-
`ule (color copy), (1 page).
`Top and bottom views Printed Circuit Board of Atari CX853
`(color copy), (1 page).
`Sams Computerfacts Technical Service Data, Atari Model
`800 Computer, (41 pages).
`Rockwell R650X% and R651X% Microprocessors (CPU) Data
`Sheet, (16 pages).
`S54ACQ/74.ACQ244-54.ACTOQO/
`National Semiconductor
`7T4ACTQ244 Quiet Series Octal Buffer/Line Driver with
`Tri-State Outputs, (10 pages).
`Texas Instruments, SN54157 Data Sheet, (8 pages).
`Texas Instruments, SN5410 Data Sheet, (1 page).
`Texas Instruments, TMS4116 16, 348—Bit Dynamic Ran-
`dom—Access Memory Data Sheet, (14 pages),
`Top and bottom views of Commodore VIC-1111 16K RAM
`Cartridge, (1 page).
`Top and bottom views of printed circuit board of Commo-
`dore VIC-1111 16K RAM Cartridge, (1 page).
`Sams Computerfacts Commodore Model VIC20, 1984, (22
`pages).
`Sams Computerfacts Commodore Model VIC 20 (Early
`Version), 1985, (17 pages).
`National Semiconductor 54.8138 Decoders/Demultiplexers
`Data Sheet, (8 pages).
`Hitachi HM6116 Series Data Sheet, (5 pages).
`Front and back views of DEC MS44—AA memory module
`(color copy), (1 page).
`Texas Instruments SN54ALS1034 Hex Drivers Data Sheet,
`(6 pages).
`Siemens HYB 51L000BJ—50/60/70 Data Sheet, (22 pages).
`Digital DECdirect Desktop Edition, Winter/Spring 1991
`(excerpts), (14 pages).
`Front and back views of Kingston Technology memory
`boards for HP Apollo 9000 Series 700 computers, (2 pages).
`Kingston Technology KTH700/16, /32, ‘64 & /128 memory
`upgrade kits, documentation, (3 pages).
`CE Handbook HP Apollo 9000 Series 700 Workstation/
`Servers, (247 pages).
`
`4
`
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`U.S. Patent
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`Oct. 26, 1999
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`Sheet 1 of 6
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`5,973,951
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`Oct. 26, 1999
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`Sheet 3 of 6
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`5,973,951
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`U.S. Patent
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`Oct. 26, 1999
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`Sheet 4 of 6
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`U.S. Patent
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`Oct. 26, 1999
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`Sheet 6 of 6
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`5,973,951
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`5,973,951
`
`1
`SINGLE IN-LINE MEMORY MODULE
`
`‘This 1s a continuation application of Ser. No, 08/643,094,
`filed May 2, 1996 now abandoned whichis a continuation of
`Ser. No. 08/473,073, filed Jun. 7, 1995, now US. Pat. No.
`5,532,954 issued Jul. 2, 1996, whichis a continuation ofSer.
`No. 08/345,477 filed Nov. 28, 1994, now U.S. Pat. No.
`5,465,229 issued Nov. 7, 1995, which is a continuation of
`Ser. No. 08/279,824, filed Jul. 25, 1994, now U.S, Pat. No.
`5,383,148 issued Jan. 17, 1995, which a continuation ofSer.
`No, 08/115,438, filed Sep. 1, 1993, now abandoned, which
`is a continuation of Ser. No. 07/886,413,filed May 19, 1992,
`now U.S. Pat. No. 5,270,964, issued on Dec. 14, 1993,
`
`BACKGROUND OF THE INVENTION
`
`15
`
`1. Related Applications
`This application is related to U.S. Pat. No, 5,260,892,
`entitled “High Speed Electrical Signal Interconnect
`Structure”, issued Nov. 9, 1993 and U.S, Pat. No. 5,265,218,
`entitled “Bus Architecture for Integrated Data and Video
`Memory’, issued Nov. 23, 1993.
`2. Field of the Invention
`
`2
`a memory increment forthe entire data path. Instead the user
`must obtain and install multiple SIMMs,
`in combination
`with performing any additional configuration requirements
`necessary to make the separate SIMMs modules function as
`a single memory unit, such as setting base addresses for the
`SIMM modules installed.
`
`As a result, a user seeking to increase his usable main
`memory by adding SIMMs constructed according to the
`priorart, typically must insert multiple SIMMsto achieve a
`memoryexpansion for the entire data path of his computer.
`The foregoing is a consequence of typical prior art SIMM
`architecture, wherein the SIMM is arranged around DRAM
`parts which comprise one byte wide memory increments.
`Thus in a data path having a width of 32 bits, there being
`eight bits per byte, a 1 megabyte expansion of main memory
`using SIMMs constructed according to the prior art would
`require four SIMM modules each of one megabyte capacity
`in order to obtain a full data path expansion of one mega-
`byte.
`in the following
`As will be described in more detail
`detailed description, the present invention provides, among
`other attributes, facility for providing memory expansion in
`full data path widths, thereby relieving the user of config-
`uring and installing multiple SIMMs modules to obtain any
`desired memory increment.
`SUMMARY OF THE INVENTION
`
`A full width single in-line memory module (SIMM) for
`dynamic random access memory (ORAM) memory expan-
`sions is disclosed. A printed circwit board having a multi-
`plicity of DRAM memory elements mounted thereto is
`arranged in a data path having a width of 144 bits. The
`SIMM of the present invention further includes on-board
`drivers to buffer and drive signals in close proximity to the
`memoryelements. In addition, electrically conductive traces
`are routed on the circuit board in such a manner to reduce
`loading and trace capacitance to minimize signal skew to the
`distributed memory elements. The SIMM further includes a
`high pin density dual read-out connector structure receiving,
`electrical traces from both sides of the circuit board for
`enhanced functionality. The SIMMis installed in comple-
`mentary sockets one SIMM at a time to provide memory
`expansion in full width increments. Finally, symmetrical
`powerand ground routings to the connector structure insure
`that
`the SIMM cannot be inserted incorrectly, wherein
`physically reversing the SIMM in the connectorslot will not
`reverse power the SIMM.
`BRIEP DESCRIPTION OF THE DRAWINGS
`
`The objects, features and advantages ofthe present inven-
`tion will be apparent from the following detailed description
`given below and from the accompanying drawings of the
`preferred embodiment of the invention in which:
`FIG. la illustrates the electrical schematic ofa first side
`ofthe single in-line memory module (SIMM)according to
`the teachings of the present invention.
`FIG. 16 illustrates the electrical schematic for a left-to-
`right mirror image layout of memory elements on a second
`side of the SIMM.
`
`FIG. 2a@ illustrates the physical layout of the memory
`elements and drivers placed on the SIMM.
`FIG. 25 is a magnified view of the dual read-out connector
`structure on the SIMM.
`
`FIG. 3 illustrates the stacked conductive layers separated
`by insulating dielectric necessary to build up the intercon-
`nections for the electrical schematic shown in FIGS. 1a and
`Ib.
`
`25
`
`30
`
`invention relates to the field of computer
`The present
`systems and memory hardware. More particularly,
`the
`present invention relates to modular circuit boards which
`may be combined to form a memory structure within a
`computer system.
`3. Art Background
`Single In-Line Memory Modules (“SIMMs”) are compact
`circuit boards designed to accommodate surface mount
`memory chips. SIMMs were developed to provide compact
`and easy to manage modular memory components for user
`installation in computer systems designed to accept such
`SIMMs. SIMMsgenerally are easily inserted into a connec-
`tor within the computer system, the SIMM thereby deriving
`all necessary power, ground, and logic signals therefrom.
`A SIMM typically comprises a multiplicity of random
`access memory (“RAM”) chips mounted to a printed circuit
`board. Depending on the user’s needs, the RAM memory
`chips may be dynamic RAM (DRAM), non volatile static
`RAM (SRAM) or video RAM (WRAM). Because DRAM
`memories are larger and cheaper than memory cells for
`SRAMs, DRAMsare widely used as the principal building
`block for main memories in computer systems, SRAM and
`VRAM SIMMshave more limited application for special
`purposes such as extremely fast cache memories and video
`frame buffers, respectively. Because DRAMsform the larg-
`est portion of a computer system memory,
`it
`is therefore
`desirable that memory modules flexibly accommodate the 5
`computation needs of a user as the users’ requirements
`change over time. Moreover, it is desirable that the SIMM
`modules may be added to the computer system with a
`minimum user difficulty, specifically in terms of configura-
`tion of a SIMM within a particular memory structure. In the 5:
`past, SIMMs have generally been designed to provide
`memory increments of one or more megabytes (MB), but
`where the memory addition comprises only a portion of the
`full data path used in the computer system. A leading
`example of the prior art organization and structure is that
`disclosed in U.S. Pat. No. 4,656,605, issued Apr. 7, 1987 to
`Clayton. Clayton discloses a compact modular memory
`circuit board to which are mounted nine memory chips
`whichare arranged to provide memory increments in eight
`bit (one byte) data widths, plus parity bits. Thus, because
`most computer systems use data paths of 32, 6+ or more bits,
`the SIMM constructed according to Clayton cannot provide
`
`3
`
`60
`
`11
`11
`
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`
`5,973,951
`
`3
`FIGS. 4@ and 46 are a connector diagram illustrating data,
`address and control signals routed to a SIMM.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`4
`one WE signal and one reset line. The routing for all control
`signals 20, address signals 21 and data signals 25 minimize
`conductive trace capacitance and loading in accordance with
`US. Pat. No, 5,260,892, entitled ‘High Speed Electrical
`Signal Interconnect Structure’, assigned to the assignee of
`the present invention, and which is incorporated herein by
`A bus architecture for integrated data and video memory
`reference. The trace routing control for all control signals 20
`are taken from driver 15 to the central DRAM 10 for each
`is disclosed. In the following description, for purposes of
`explanation, specific numbers, times, signals etc., are set
`DRAM cluster 10a, 105, 10c, and 10¢. DRAMssurrounding
`forth in order to provide a thorough understanding of the
`the central DRAM 10 are coupled to contro! signals 20 via
`present invention. However,it will be apparent to one skilled
`short sub traces (not shown),
`thereby minimizing total
`in the art that the present invention may be practiced without
`capacitance, and increasing signal rise times.
`these specific details. In other instances, well knowncircuits
`With brief reference to FIG. 3, the stack up used to route
`and devices are shownin block diagram form in order not to
`all control, addresses, data, and power and ground signals is
`obscure the present invention unnecessarily.
`illustrated. In the embodiment shown in FIG, 3, the printed
`The preferred embodiment of the SIMM described herein
`circuit board is a multi-layered board including several
`signal layers.
`is designed and intended to be used with the integrated data
`and video memory bus disclosed in copending U.S. patent
`With brief reference to PIG. Lb, a second, reverse side of
`SIMM 5 is shown.
`In FIG. 15,
`two additional DR