United States Patent [19]
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`Testa et al.
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`US005383148A
`5,383,148
`[11] Patent Number:
`[45] Date of Patent:
`Jan. 17, 1995
`
`[54] SINGLE IN-LINE MEMORY MODULE
`[75] Inventors: James Testa, Mountain View;
`Andreas Bechtolsheim, Stanford;
`Edward Frank, Portola Valley;
`Shawn Storm, Mt. View, all of Calif.
`[73] Assignee: Sun Microsystems, Inc., Mountain
`View, Calif.
`[21] Appl. No.: 279,824
`[22] Filed:
`Jul. 25, 1994
`
`[63)
`
`Related U.S. Application Data
`Continuation of Ser. No. 115,438, Sep. 1, 1993, aban
`doned, which is a continuation of Ser. No. 886,413,
`May 19, 1992, Pat. No. 5,270,964.
`[51] Int. Cl." .............................................. G11C 13/00
`[52] U.S. Cl. ....................................... 365/52; 365/244
`[58] Field of Search ................ 365/52, 189.01, 230.01,
`365/244
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,850,892 7/1989 Clayton et al. ..................... 439/326
`4,891,789 1/1990 Quattrini ............................... 365/63
`5,270,964. 12/1993 Bezhtolsheim et al. .............. 365/52
`Primary Examiner—Terrell W. Fears
`
`Attorney, Agent, or Firm—Blakely Sokoloff Taylor &
`Zafman
`ABSTRACT
`[57]
`A full width single in-line memory module (SIMM) for
`dynamic random access memory (DRAM) memory
`expansions is disclosed. A printed circuit board having
`a multiplicity of DRAM memory elements mounted
`thereto is arranged in a data path having a width of 144
`bits. The SIMM of the present invention further in
`cludes on-board drivers to buffer and drive signals in
`close proximity to the memory elements. In addition,
`electrically conductive traces are routed on the circuit
`board in such a manner to reduce loading and trace
`capacitance to minimize signal skew to the distributed
`memory elements. The SIMM further includes a high
`pin density dual readout connector structure receiving
`electrical traces from both sides of the circuit board for
`enhanced functionality. The SIMM is installed in com
`plementary sockets one SIMM at a time to provide
`memory expansion in full width increments. Finally,
`symmetrical power and ground routings to the connec
`tor structure insure that the SIMM cannot be inserted
`incorrectly, wherein physically reversing the SIMM in
`the connector slot will not reverse power the SIMM.
`
`11 Claims, 6 Drawing Sheets
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`U.S. Patent
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`Jan. 17, 1995
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`Sheet 1 of 6
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`5,383,148
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`U.S. Patent
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`Jan. 17,
`1995
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`Sheet 2 of 6
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`5,383,148
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`U.S. Patent
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`Jan. 17, 1995
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`Sheet 3 of 6
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`5,383,148
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`[ ] D
`J D - DT] [T] [T]
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`U.S. Patent
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`Jan. 17, 1995
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`Sheet 4 of 6
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`5,383,148
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`5,383,148
`3
`4
`FIGS. 4a and 4b are a connector diagram illustrating
`ently preferred, SIMM 5 embodies a 144 bit data path,
`comprising 128 data lines (DATA[127:0]), 16 error
`the data, address and control signals routed to the
`correction lines (CBWI15:0]) which implement a
`SIMM.
`known error correction code, one RAS-, two CAS
`DETAILED DESCRIPTION OF THE
`signals, one WE signal and one reset line. The routing
`INVENTION
`for all control signals 20, address signals 21 and data
`signals 25 minimize conductive trace capacitance and
`A bus architecture for integrated data and video
`memory is disclosed. In the following description, for
`loading in accordance with above referenced U.S. pat.
`purposes of explanation, specific numbers, times, signals
`appl. entitled “High Speed Electric Signal Interconnect
`etc., are set forth in order to provide a thorough under
`Structure,” assigned to the assignee of the present in
`10
`standing of the present invention. However, it will be
`vention, and which is incorporated herein by reference.
`apparent to one skilled in the art that the present inven
`The trace routing control for all control signals 20 are
`tion may be practiced without these specific details. In
`taken from driver 15 to the central DRAM 10 for each
`other instances, well known circuits and devices are
`DRAM cluster 10a, 10b, 10c, and 10d. DRAMs Sur
`rounding the central DRAM 10 are coupled to control
`shown in block diagram form in order not to obscure
`the present invention unnecessarily.
`signals 20 via short sub traces (not shown), thereby
`minimizing total capacitance, and increasing signal rise
`The preferred embodiment of the SIMM described
`herein is designed and intended to be used with the
`times.
`integrated data and video memory bus disclosed in
`With brief reference to FIG. 3, the stack up used to
`copending U.S. patent application Ser. No. 07/886,671,
`route all control, addresses, data, and power and
`20
`ground signals is illustrated.
`filed May 19, 1992, entitled “A Bus Architecture For
`Integrated Data and Video Memory”.
`With brief reference to FIG. 1b, a second, reverse
`It will be apparent, however, to those skilled in the
`side of SIMM 5 is shown. In FIG. 18, two additional
`art that the specifications disclosed herein can or may
`DRAM clusters 10c and 10d are shown arranged as
`be changed without departing from the scope of the
`DRAM clusters 10a and 10b on the obverse side. Each
`25
`present invention. Although the preferred embodiment
`DRAM 10 in DRAM clusters 10c and 10d similarly
`of the present invention is disclosed in terms of the data
`receives four input lines in addition to address and con
`path width matching that of the integrated data and
`trol lines passed from driver 15 on the obverse side
`through conductive vias to the mirror image reverse
`video memory bus disclosed in the above-referenced
`U.S. patent application, it will be appreciated that
`side of SIMM 5, thereby doubling the available surface
`changing the design of the bus is within the scope of the
`area to which DRAMs 10 may be mounted. Moreover,
`SIMM 5 as presently preferred utilized thin small out
`present invention, wherein the SIMM may be matched
`to the data path width of the integrated memory bus.
`line package (TSOP) DRAMs 10 to reduce overall
`thickness of SIMMs 5. When thus constructed, the dou
`Reference is now made to FIG. 1a wherein an electri
`cal block diagram of memory elements mounted to a
`ble sided SIMM 5 of the present invention is no thicker
`35
`than prior art single sided SIMMs (e.g., as taught by
`first, obverse side of the SIMM is shown. In FIG. 1a, a
`Clayton).
`multiplicity of dynamic RAM (DRAMs) 10 are
`Briefly referring to FIG. 4, the high number density
`grouped into two clusters 10a and 10b. There are nine
`DRAMs 10 in each cluster. A driver 15 receives control
`connector 30 used to connect SIMM 5 to the memory
`signals, and address signals from an external bus ar
`module socket (not shown) is illustrated. In FIG. 4,
`rangement (not shown) through a dual sided connector
`connector 30 is seen to have 200 pin terminations, there
`30. A multiplicity of control lines 20 route RAS- (row
`fore permitting a large number of signals to be routed to
`access strobe), CAS- (column access strobe), WE
`and from SIMM 5. In the preferred embodiment of
`(write enable), and OE- (output enable), control signals
`SIMM 5, it is intended that SIMM 5 specifically incor
`porate the data path architecture consistent with an
`from driver 15 to all the DRAMs 10 mounted to SIMM
`45
`5. Moreover, driver 15 buffers and subsequently distrib
`integrated data and video memory bus such as that
`utes address signals 21 to all DRAMs 10 mounted to
`described in above referenced copending U.S. patent
`SIMM 5. For purposes of clarity in the present figure,
`applications assigned to Sun Microsystems, Inc., Moun
`the specific routing of data, address and control lines to
`tain View, Calif., which is hereby incorporated herein
`by reference. In particular, the data path architecture
`all the DRAMs 10 is omitted. However, as can be seen
`from FIG. 1a, all DRAMs 10 have four data lines,
`implemented on SIMM 5 includes 128 data lines, 16
`DRAMs 10 being any of several commercially available
`error correction code lines (referred to CBW [15:0] in
`DRAMs arranged in a “by-four” configuration. As will
`FIGS. 1-6), in addition to a multiplicity of control sig
`mals necessary to accomplish DRAM memory accesses.
`be seen below in connection with FIG. 15, DRAMs 10
`Such control signals, collectively referred to control
`each of DRAM clusters 10a and 10b are matched with
`55
`mirror image DRAMs 10 mounted to the opposite side
`lines 20 in FIGS. 1a and 1b, include one RAS- signal,
`of SIMM 5 and placed in electrical communication by
`two CAS- signals, one WE- signal, and one reset line
`electrical traces passing through a multiplicity of vias
`per SIMM 5. Thus, not including the control signals 20
`which are used for controlling operation of DRAMs 10,
`(not shown).
`The specific routing of the electrical traces on SIMM
`the data path used for transmission of data to and from
`60
`5 are dependent upon the specific architecture of the
`DRAMs 10 is seen to be 144 bites wide. Disregarding
`memory chips chosen for a specific implementation of
`the error correction code signal, referred to in FIGS.
`SIMM 5. However, all SIMMs 5 constructed according
`1–4 as CBW [15:0], the actual data path width of SIMM
`to the teachings of the present invention have a full
`5 for writing and reading data to and from memory is
`width data path extending from connector 30 to all
`128 bits wide, or 16 bytes, identical to that of the inte
`65
`devices operating on SIMM 5, including all DRAMs
`grated data and video memory bus. Accordingly,
`10, driver 15, and any other logic elements necessary to
`SIMM5 of the present invention may be installed into
`implement the desired function of SIMM 5. As pres
`the memory bus in full width increments.
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`Disclaimer
`5,383.148 - James Testa, Mountain View; Andreas Bechtolsheim, Stanford, Edward Frank, Portola
`Valley; Shawn Storm, Mt. View, all of Calif. SINGLE IN-LINE MEMORY MODULE. Patent dated
`January 17, 1995. Disclaimer filed July 2, 1999, by the assignee, Sun Microsystems Inc.
`Hereby enters this disclaimer to claims 1, 2, 4, 5, 8, 9 and 11 of said patent.
`(Official Gazette, September 21, 1999)
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`Disclaimer
`5,383,148—James Testa, Mountain View; Andreas Bechtolsheim, Stanford; Edward Frank, Portola Valley;
`Shawn Storm, Mt. View, all of Calif. SINGLE IN-LINE MEMORY MODULE. Patent dated January 17,
`1995. Disclaimer filed May 21, 2001, by the assignee, Sun Microsystems Inc.
`Hereby enters this disclaimer to all claims of said patent.
`(Official Gazette, August 14, 2001)
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