`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Global Foundaries US v. Godo Kaisha
`Global Ex. 1013
`
`Page 1 of 29
`
`

`

`6,165,826
`Page 2
`
`
`
`
`
`........................ .. 438/301
`4/1997 Hwang et al.
`
`
`
`
`
`
`
`
`
`
`
`............................. 257/344
`1/1998 Chau etal.
`
`
`
`
`
`
`
`3/1998 Segawa 6‘ a1~
`~~
`6/1998 Chen etal.
`........................... .. 438/305
`
`
`
`
`
`
`
`5,620,912
`
`5,710,450
`5926971
`5,770,507
`
`
`
`U.S. PATENT DOCUMENTS
`
`
`
`5,478,776
`12/1995 Luflman em. ......................N 4377163
`
`
`
`
`
`
`
`5,538,909
`7/1996 Hsu .......... ..
`437/35
`
`
`
`
`
`5,569,624 10/1996 Weiner .................................. .. 437/200
`
`
`
`
`
`
`Page 2 0f 29
`
`Page 2 of 29
`
`

`

`
`U.S. Patent
`
`
`
`Dec. 26,2000
`
`
`
`
`
`Sheet 1 of 13
`
`
`
`
`
`
`6,165,826
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 1 (PRIOR ART)
`
`
`
`Page 3 of 29
`
`Page 3 of 29
`
`

`

`
`U.S. Patent
`
`
`
`Dec. 26,2000
`
`
`
`
`
`Sheet 2 of 13
`
`
`
`
`
`
`6,165,826
`
`
`
`
`
`N.9".
`
`
`
`
`
`
`
`
`
`
`
`_..__.._E_.__.__.._H
`.,.u.aw..
`
`
`
`
`
`
`
`
`
`
`
`
`Page 4 of 29
`
`Page 4 of 29
`
`
`

`

`
`U.S. Patent
`
`
`
`Dec. 26,2000
`
`
`
`
`
`Sheet 3 of 13
`
`
`
`
`
`
`6,165,826
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 5 of 29
`
`Page 5 of 29
`
`

`

`
`U.S. Patent
`
`
`
`Dec. 26, 2000
`
`
`
`
`
`Sheet 4 of 13
`
`
`
`
`
`
`6,165,826
`
`
`
`A
`
`\‘
`
`VI
`
`90)
`I03
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`318
`
`
`
`
`
`
`
`
`
`
`314
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Q
`Q
`
`
`§
`§
`
`
`
`
`
`E
`S
`
`
`
`
`
`
`
`
`
`
`IIIII“IIIII
`—-— ——.
`3016
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`335
`
`
`
`E
`
`
`
`
`
`
`‘
`:
`‘ \
`§
`\
`‘In
`:
`in ‘uFA‘ M:
`
`\\\\\\\\\\\\~1jx \\\\\\\\j 6
`
`
`3.05
`
`
`
`\
`
`
`
`
`
`
`
`FIG. 3F
`
`Page 6 of 29
`
`324
`
`
`
`22
`
`
`
`Page 6 of 29
`
`

`

`
`U.S. Patent
`
`
`
`Dec. 26,2000
`
`
`
`
`
`Sheet 5 of 13
`
`
`
`
`
`
`6,165,826
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`llIlI§"‘§IIIIl
`d 303
`336
`301 34°:
`
`I
`
`{ S
`
`L
`
`\‘ \
`
`L
`
`
`
`
`305
`
`:
`
`:
`336
`
`
`I
`4
`
`
`
`
`
`H H19
`
`317-» I~ -
`
`
`
`
`
`.
`
`I
`
`
`
`
`
`FIG. 3H
`
`Page 7 of 29
`
`Page 7 of 29
`
`

`

`
`U.S. Patent
`
`
`
`Dec. 26, 2000
`
`
`
`
`
`Sheet 6 of 13
`
`
`
`
`
`
`6,165,826
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`I
`
`
`
`
`4’
`
`III
`
`
`
`
`
`
`
`
`
`
`
`
`305
`
`
`
`
`
`
`
`
`
`
`
`M
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`IIIII4\.
`03 O.§\\\\\
`
`
`
`
`
`Viillz.
`
`
`
`
`
`
`
`
`*3‘K
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 4C
`
`Page 8 of 29
`
`' 11111
`
`I,
`5
`
`I
`I
`I
`I
`
`I
`I
`314
`
`
`I
`I
`
`IIIIIIIIZ
`111/1/[Ill/111511’
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 8 of 29
`
`
`
`
`
`
`

`

`
`U.S. Patent
`
`
`
`Dec. 26, 2000
`
`
`
`
`
`Sheet 7 of 13
`
`
`
`
`
`
`6,165,826
`
`
`
`
`
`
`416
`4[1s
`314
`
`
`\\\\\ ‘
`
`‘x
`§
`
`
`
`
`
`\
`K
`
`
`a
`3
`
`
`
`
`
`
`
`
`
`
`
`
`
`301
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`\
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`VIIIIII;..\\\\\\\‘
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
` yK\\\\\\\llllllll
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`"L\\\\\\\IIIIIIIZ
`
`VIIIIIIJ.S\\\\\\‘
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`301
`
`
`
`
`
`
`
`
`
`FIG. 4F
`
`Page 9 of 29
`
`Page 9 of 29
`
`

`

`
`U.S. Patent
`
`
`
`Dec. 26,2000
`
`
`
`
`
`Sheet 8 of 13
`
`
`
`
`
`
`6,165,826
`
`
`
`\
`
`
`
`
`
`\\\\\\\\\\\\\\\\
`
`\
`
`
`
`\
`
`
`
`
`
`
`\\Ҥ~
`
`“E
`
`
`
`
`
`
`
`w\§“L
`
`
`
`fl
`
`
`
`
`
`\\\\\\\\
`
`
`
`
`
`
`
`
`
`
`
`\w‘~35“m“E
`
`
`
`
`
`31 4
`
`\\\\\\\\
`
`3%
`
`
`5
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`314
`
`
`
`
`
`
`
`
`
`
`
`FIG. 5A
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`84|
`3’
`
`
`-1“‘§‘n
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 5C
`
`Page 10 of 29
`
`Page 10 of 29
`
`
`
`
`
`
`
`

`

`
`U.S. Patent
`
`
`
`Dec. 26, 2000
`
`
`
`
`
`Sheet 9 of 13
`
`
`
`
`
`
`6,165,826
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 11 of 29
`
`Page 11 of 29
`
`

`

`
`U.S. Patent
`
`
`
`Dec. 26,2000
`
`
`
`
`
`Sheet 10 of 13
`
`
`
`
`
`
`6,165,826
`
`
`
`
`
` 3111115Ila30’~.
`7111111..
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`§II|§
`Aw\
`IIIII*‘—"'*IIIII
`
`
`
`
`
`6_
`
`.1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`.
`
` .77
`
`|E2F;IIIl*"—~Il II
`
`
`
`
`
`
`
`
`
`
`FIG. 6C
`
`Page 12 of 29
`
`Page 12 of 29
`
`

`

`
`U.S. Patent
`
`
`
`
`
`Dec. 26, 2000
`
`
`
`Sheet 11 of 13
`
`
`
`
`
`
`6,165,826
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`..6_.0I-3
`
`...\\\\\\.
`\\\\\\w
`
`
`
`
`
`
`
`1
`
`It
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 6D
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 13 of 29
`
`Page 13 of 29
`
`
`

`

`
`U.S. Patent
`
`
`
`Dec. 26,2000
`
`
`
`
`
`Sheet 12 0f 13
`
`
`
`
`
`
`6,165,826
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`”"”
`
`
`
`
`
`
`IIIIIIIII
`\\\\\\\\\
`
`
`
`
`
`410
`
`3.05
`
`
`
`30
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`””’Au\VS‘.L
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`S“~
`
`
`
`
`
`"I’"L
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`_"””A_"”’I
`
`
`
`
`
`
`
`
`
`
`
`FIG. 7A
`
`
`
`
`
`
`
`
`
`
`
`FIG. 7B
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 7C
`
`Page 14 of 29
`
`Page 14 of 29
`
`
`
`
`
`
`
`
`

`

`.
`
`
`
`
`
`
`
`
`
`
`
`1teehS
`
`
`
`
`
`
`3
`
`
`
`6,165,826
`
`
`
`x\\\.\\\\0I..H7/I//I..3IIII!
`
`
`
`3
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1nofu\\\\\\4\.
`
` n/..V\4VVV..76I32...M
`4M.
`
`
`
`417
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`0H0p0u2197...6mm2..VI/I//A7.VIII/IA7%...”.
`...”.5DM..w_W...7””’.I.Q..H.\\\\\.\x
`......7I...7JW.I..‘L0f.7..4nDEMm7W777aIIPnluG
`
`ab.FF
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 7F
`
`Page 15 of 29
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 15 of 29
`
`
`
`
`

`

`6,165,826
`
`
`
`
`1
`TRANSISTOR WITH LOW RESISTANCE TIP
`
`
`
`
`AND METHOD OF FABRICATION IN A
`
`
`
`
`
`
`CMOS PROCESS
`
`
`
`
`
`
`
`This application is a Continuation-in-Part of U.S. patent
`
`
`
`
`
`
`
`application Ser. No. 08/363,749, filed Dec. 23, 1994 now
`
`
`
`
`
`
`
`
`U.S. Pat. No. 5,710,450 and assigned to the present
`
`
`
`
`
`
`
`
`Assignee.
`
`BACKGROUND OF THE INVENTION
`
`
`
`1. Field of the Invention
`
`
`
`
`
`The present invention relates to the field of semiconductor
`
`
`
`
`
`
`
`
`integrated circuits, and more specifically, to the ultra large-
`
`
`
`
`
`
`
`
`scale fabrication of submicron transistors.
`
`
`
`
`
`2. Discussion of Relates Art
`
`
`
`
`
`transistors are
`Today literally millions of individual
`
`
`
`
`
`
`coupled together to form very large-scale integrated (VLSI)
`
`
`
`
`
`
`
`circuits, such as microprocessors, memories, and applica-
`
`
`
`
`
`
`tions specific integrated circuits (ICs). Presently, the most
`
`
`
`
`
`
`
`
`advanced ICs are made up of approximately three million
`
`
`
`
`
`
`
`
`
`transistors, such as metal oxide semiconductor (MOS) field
`
`
`
`
`
`
`
`
`effect transistors having gate lengths on the order of 0.5 gm.
`
`
`
`
`
`
`
`
`
`
`
`In order to continue to increase the complexity and compu-
`
`
`
`
`
`
`
`
`
`tational power of future integrated circuits, more transistors
`
`
`
`
`
`
`
`
`must be packed into a single IC (i.e., transistor density must
`
`
`
`
`
`
`
`
`
`
`
`increase). Thus, future ultra large-scale integrated (ULSI)
`
`
`
`
`
`
`
`circuits will require very short channel
`transistors with
`
`
`
`
`
`
`
`
`effective gate lengths less than 0.1 gm. Unfortunately, the
`
`
`
`
`
`
`
`
`
`structure and method of fabrication of conventional MOS
`
`
`
`
`
`
`
`
`transistors cannot be simply “scaled down” to produce
`
`
`
`
`
`
`
`
`smaller transistors for higher density integration.
`
`
`
`
`
`
`The structure of a conventional MOS transistor 100 is
`
`
`
`
`
`
`
`
`
`shown in FIG. 1. Transistor 100 comprises a gate electrode
`
`
`
`
`
`
`
`
`
`
`102, typically polysilicon, formed on a gate dielectric layer
`
`
`
`
`
`
`
`
`
`104 which in turn is formed on a silicon substrate 106. Apair
`
`
`
`
`
`
`
`
`
`
`
`
`of source/drain extensions or tip regions 110 are formed in
`
`
`
`
`
`
`
`
`
`
`the top surface of substrate 106 in alignment with outside
`
`
`
`
`
`
`
`
`
`
`edges of gate electrode 102. Tip regions 110 are typically
`
`
`
`
`
`
`
`
`
`
`formed by well-known ion implantation techniques and
`
`
`
`
`
`
`
`extend beneath gate electrode 102. Formed adjacent
`to
`
`
`
`
`
`
`
`
`opposite sides of gate electrode 102 and over tip regions 110
`
`
`
`
`
`
`
`
`
`
`
`are a pair of sidewall spacers 108. A pair of source/drain
`
`
`
`
`
`
`
`
`
`
`
`regions 120 are then formed, by ion implantation, in sub-
`
`
`
`
`
`
`
`
`
`strate 106 substantially in alignment with the outside edges
`
`
`
`
`
`
`
`
`of sidewall spacers 108.
`
`
`
`
`As the gate length of transistor 100 is scaled down in
`
`
`
`
`
`
`
`
`
`
`
`order to fabricate a smaller transistor, the depth at which tip
`
`
`
`
`
`
`
`
`
`
`
`region 110 extends into substrate 106 must also be scaled
`
`
`
`
`
`
`
`
`
`
`down (i.e., decreased) in order to improve punchthrough
`
`
`
`
`
`
`
`
`characteristics of the fabricated transistor. Unfortunately, the
`
`
`
`
`
`
`
`length of tip region 110, however, must be larger than 0.07
`
`
`
`
`
`
`
`
`
`
`
`pm to insure that the later, heavy dose, deep source/drain
`
`
`
`
`
`
`
`
`
`
`implant does not swamp and overwhelm tip region 110.
`
`
`
`
`
`
`
`
`
`in the fabrication of a small scale transistor with
`Thus,
`
`
`
`
`
`
`
`
`
`
`conventional methods, as shown in FIG. 1, the tip region 110
`
`
`
`
`
`
`
`
`
`
`
`is both shallow and long. Because tip region 110 is both
`
`
`
`
`
`
`
`
`
`
`
`shallow and long, tip region 110 exhibits substantial para-
`
`
`
`
`
`
`
`
`sitic resistance. Parasitic resistance adversely effects
`
`
`
`
`
`(reduces) the transistors drive current.
`
`
`
`
`
`Thus, what is needed is a novel transistor with a low
`
`
`
`
`
`
`
`
`
`
`resistance ultra shallow tip region with a VLSI manufactur-
`
`
`
`
`
`
`
`
`able method of fabrication in a CMOS process.
`
`
`
`
`
`
`
`
`SUMMARY OF THE INVENTION
`
`
`
`
`A novel transistor with a low resistance ultra shallow tip
`
`
`
`
`
`
`
`
`
`
`region and its method of fabrication in a complementary
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`2
`
`
`metal oxide semiconductor process (CMOS) is described.
`
`
`
`
`
`
`
`According to a preferred method of the present invention, a
`
`
`
`
`
`
`
`
`
`
`first gate dielectric and a first gate electrode are formed on
`
`
`
`
`
`
`
`
`
`
`
`a first portion of a semiconductor substrate having a first
`
`
`
`
`
`
`
`
`
`
`conductivity type, and a second gate dielectric and a second
`
`
`
`
`
`
`
`
`
`
`gate electrode are formed on a second portion of a semi-
`
`
`
`
`
`
`
`
`
`
`conductor substrate having a second conductivity type.
`
`
`
`
`
`
`
`Next, ions of a second conductivity type are implanted into
`
`
`
`
`
`
`
`
`
`the first portion of the semiconductor substrate in alignment
`
`
`
`
`
`
`
`
`
`with the outside edges of the first gate electrode. A silicon
`
`
`
`
`
`
`
`
`
`
`
`nitride layer is then formed over the first portion of the
`
`
`
`
`
`
`
`
`
`
`
`semiconductor substrate including the first gate electrode
`
`
`
`
`
`
`
`and over the second portion of the semiconductor substrate
`
`
`
`
`
`
`
`
`
`including the second gate electrode. The silicon nitride layer
`
`
`
`
`
`
`
`
`
`is then removed from the second portion of the silicon
`
`
`
`
`
`
`
`
`
`
`substrate and from the top of the second gate electrode to
`
`
`
`
`
`
`
`
`
`
`
`thereby form a first pair of silicon nitride spacers adjacent to
`
`
`
`
`
`
`
`
`
`
`
`opposite sides of the second gate electrode. A pair of
`
`
`
`
`
`
`
`
`
`
`recesses are then formed in the second portion of the
`
`
`
`
`
`
`
`
`
`
`semiconductor substrate in alignment with the first pair of
`
`
`
`
`
`
`
`
`
`silicon nitride spacers. A selectively deposited semiconduc-
`
`
`
`
`
`
`tor material is then formed in the recesses. Dopants are then
`
`
`
`
`
`
`
`
`
`
`diffused from the selectively deposited semiconductor mate-
`
`
`
`
`
`
`rial into the substrate beneath the first pair of silicon nitride
`
`
`
`
`
`
`
`
`
`
`
`spacers. Next, a first pair of sidewall spacers are formed
`
`
`
`
`
`
`
`
`
`
`adjacent to opposite sides of the first gate electrode and a
`
`
`
`
`
`
`
`
`
`
`
`second pair of sidewall spacers are formed on the deposited
`
`
`
`
`
`
`
`
`
`
`semiconductor material adjacent to the outside edge of the
`
`
`
`
`
`
`
`
`
`first pair of silicon nitride spacers. Ions of a second con-
`
`
`
`
`
`
`
`
`
`
`ductivity type are then implanted into the first portion of the
`
`
`
`
`
`
`
`
`
`
`
`semiconductor substrate in alignment with the outside edges
`
`
`
`
`
`
`
`
`of the first pair of sidewall spacers adjacent to the first gate
`
`
`
`
`
`
`
`
`
`
`
`
`electrode to thereby form a first pair of source/drain contact
`
`
`
`
`
`
`
`
`
`
`regions in the first portion of the semiconductor substrate.
`
`
`
`
`
`
`
`
`
`Silicide is then formed on the source/drain contact regions
`
`
`
`
`
`
`
`
`
`and on the first gate electrode and on the deposited semi-
`
`
`
`
`
`
`
`
`
`
`conductor material in alignment with the outside edges of
`
`
`
`
`
`
`
`
`
`the second pair of sidewall spacers are on the second gate
`
`
`
`
`
`
`
`
`
`
`
`electrode.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`
`
`
`
`FIG. 1 is an illustration of a cross-sectional view of a
`
`
`
`
`
`
`
`
`
`
`conventional transistor.
`
`
`FIG. 2 is an illustration of a cross-sectional view of a low
`
`
`
`
`
`
`
`
`
`resistance ultra shallow tip transistor of the present inven-
`
`
`
`
`
`
`
`
`tion.
`
`FIG. 3a is an illustration of a cross-sectional view of the
`
`
`
`
`
`
`
`
`
`formation of a first gate electrode on a p-well and the
`
`
`
`
`
`
`
`
`
`
`formation of a second gate electrode on a n-well.
`
`
`
`
`
`
`
`
`FIG. 3b is an illustration of a cross-sectional view of the
`
`
`
`
`
`
`
`
`
`formation of a N— tip region in the p-well in alignment with
`
`
`
`
`
`
`
`
`
`opposite sidewalls of the first gate electrode of the substrate
`
`
`
`
`
`
`
`
`
`of FIG. 3a.
`
`
`
`FIG. 3c is an illustration of a cross-sectional view of the
`
`
`
`
`
`
`
`
`
`formation of a silicon nitride layer over the substrate of FIG.
`
`
`
`
`
`
`
`
`
`3b.
`
`FIG. 3d is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a first pair of sidewall spacers on
`
`
`
`
`
`
`
`
`
`
`opposite sides of a gate electrode formed on a substrate and
`
`
`
`
`
`
`
`
`the formation of recess regions in the n-well of the substrate
`
`
`
`
`
`
`
`
`
`
`of FIG. 3c.
`
`
`
`FIG. 36 is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the deposition of semiconductor material on the sub-
`
`
`
`
`
`
`
`
`strate of FIG. 3d.
`
`
`
`
`
`FIG. 3f is an illustration of a cross-sectional view showing
`
`
`
`
`
`
`the formation of an oxide layer and a silicon nitride layer
`
`
`
`
`
`
`
`
`
`
`over the substrate of FIG. 36.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`30
`
`
`
`35
`
`
`
`40
`
`
`
`45
`
`
`50
`
`
`
`55
`
`
`
`60
`
`
`
`65
`
`
`Page 16 of 29
`
`Page 16 of 29
`
`

`

`6,165,826
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`3
`FIG. 3g is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a first pair of sidewall spacers adjacent
`
`
`
`
`
`
`
`
`
`to the first gate electrode and a second pair of sidewall
`
`
`
`
`
`
`
`
`
`
`spacers adjacent to the first pair of silicon nitride spacers on
`
`
`
`
`
`
`
`
`
`
`the substrate of FIG. 3f.
`
`
`
`
`
`FIG. 3k is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of silicide in the source/drain contact
`
`
`
`
`
`
`
`
`
`regions and on the deposited semiconductor material of FIG.
`
`
`
`
`
`
`
`
`
`3g.
`
`FIG. 4a is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a boron doped glass layer and the
`
`
`
`
`
`
`
`
`
`
`formation of N— tip regions in the substrate of FIG. 3a.
`
`
`
`
`
`
`
`
`
`
`FIG. 4b is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a silicon nitride layer over the substrate
`
`
`
`
`
`
`
`
`
`of FIG. 4a.
`
`
`
`FIG. 4c is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a first pair of composite sidewall
`
`
`
`
`
`
`
`
`
`
`spacers adjacent to the gate electrode over the n-well of the
`
`
`
`
`
`
`
`
`
`
`
`substrate of FIG. 4b.
`
`
`
`
`FIG. 4d is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of semiconductor material on the substrate
`
`
`
`
`
`
`
`
`of FIG. 4c.
`
`
`
`FIG. 4e is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a first pair of spacers adjacent to the gate
`
`
`
`
`
`
`
`
`
`
`
`
`electrode formed over the p-well and the formation of a
`
`
`
`
`
`
`
`
`
`
`second pair of spacers adjacent to the first pair of composite
`
`
`
`
`
`
`
`
`
`
`
`spacers formed adjacent to the gate electrode over the n-well
`
`
`
`
`
`
`
`
`
`of the substrate of FIG. 4d.
`
`
`
`
`
`
`FIG. 4f is an illustration of a cross-sectional view showing
`
`
`
`
`
`
`
`
`the out diffusion of impurities from deposited semiconductor
`
`
`
`
`
`
`
`
`material and the formation of silicide on the substrate of
`
`
`
`
`
`
`
`
`
`
`FIG. 4e.
`
`
`FIG. 5a is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a silicon nitride layer over the substrate
`
`
`
`
`
`
`
`
`
`of FIG. 3a.
`
`
`
`FIG. 5b is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of spacers and recesses on the substrate of
`
`
`
`
`
`
`
`
`
`
`FIG. 5a.
`
`
`FIG. 5c is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the masking of the n-well and the formation of semi-
`
`
`
`
`
`
`
`
`
`
`conductor material on the p-well of the substrate of FIG. 5b.
`
`
`
`
`
`
`
`
`
`
`
`FIG. 5d is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a mask over the p-well and the
`
`
`
`
`
`
`
`
`
`
`
`formation of semiconductor material on the n-well of the
`
`
`
`
`
`
`
`
`
`substrate of FIG. 5c.
`
`
`
`
`FIG. Se is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a thin oxide layer and the formation of
`
`
`
`
`
`
`
`
`
`
`a thicker silicon nitride layer over the substrate of FIG. 5a’.
`
`
`
`
`
`
`
`
`
`
`
`FIG. 5f is an illustration of a cross-sectional view showing
`
`
`
`
`
`
`
`
`the formation of a second pair of spacers and the out
`
`
`
`
`
`
`
`
`
`
`
`diffusion of dopants from semiconductor material on the
`
`
`
`
`
`
`
`
`substrate of FIG. 5e.
`
`
`
`
`FIG. 6a is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of p-type semiconductor material on a
`
`
`
`
`
`
`
`
`n-well, and the formation of undoped semiconductor mate-
`
`
`
`
`
`
`
`rial on a p-well of a substrate.
`
`
`
`
`
`
`FIG. 6b is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a mask and the ion implantation of the
`
`
`
`
`
`
`
`
`
`
`substrate of FIG. 6a.
`
`
`
`
`FIG. 6c is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of sidewall spacers and the implantation of
`
`
`
`
`
`
`
`
`
`the substrate of FIG. 6b.
`
`
`
`
`
`FIG. 6a’ is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the diffusion of impurities from semiconductor material
`
`
`
`
`
`
`
`and the formation of silicide of the substrate of FIG. 6c.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`30
`
`
`
`35
`
`
`
`40
`
`
`
`45
`
`
`50
`
`
`
`55
`
`
`
`60
`
`
`
`65
`
`
`Page 17 of 29
`
`
`
`
`
`
`
`
`
`
`4
`FIG. 7a is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation and patterning of a boron doped glass layer
`
`
`
`
`
`
`
`
`
`on the substrate of FIG. 3a.
`
`
`
`
`
`
`FIG. 7b is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a silicon nitride layer over the substrate
`
`
`
`
`
`
`
`
`
`of FIG. 7a.
`
`
`
`FIG. 7c is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of spacers and recesses in the substrate of
`
`
`
`
`
`
`
`
`
`
`FIG. 7b.
`
`
`FIG. 7a’ is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of semiconductor material over the sub-
`
`
`
`
`
`
`
`
`strate of FIG. 7c.
`
`
`
`
`FIG. 7e is an illustration of a cross-sectional view show-
`
`
`
`
`
`
`
`
`ing the formation of a second pair of spacers over the
`
`
`
`
`
`
`
`
`
`
`substrate of FIG. 7d.
`
`
`
`
`FIG. 7f is an illustration of a cross-sectional view showing
`
`
`
`
`
`
`
`
`the out diffusion of impurities from deposited semiconductor
`
`
`
`
`
`
`
`
`material and the formation of silicide on the substrate of
`
`
`
`
`
`
`
`
`
`
`FIG. 7e.
`
`
`DETAILED DESCRIPTION OF THE PRESENT
`
`
`
`
`INVENTION
`
`
`
`
`A novel transistor with a low resistance ultra shallow tip
`
`
`
`
`
`
`
`
`
`
`and its method of fabrication in a complementary metal
`
`
`
`
`
`
`
`
`
`oxide semiconductor (CMOS) process is described. In the
`
`
`
`
`
`
`
`
`following description numerous specific details are set forth,
`
`
`
`
`
`
`
`
`such as specific materials, dimensions, and processes, etc.,
`
`
`
`
`
`
`
`
`in order to provide a thorough understanding of the present
`
`
`
`
`
`
`
`
`
`
`invention. It will be obvious, however, to one skilled in the
`
`
`
`
`
`
`
`
`
`
`
`that
`the invention may be practiced without
`these
`art,
`
`
`
`
`
`
`
`
`
`specific details. In other instances, well-known semiconduc-
`
`
`
`
`
`
`tor equipment and processes have not been described in
`
`
`
`
`
`
`
`
`
`particular detail in order to avoid unnecessarily obscuring
`
`
`
`
`
`
`
`
`the present invention.
`
`
`
`A preferred embodiment of a novel transistor 200 with
`
`
`
`
`
`
`
`
`
`low resistivity, ultra shallow tip of the present invention is
`
`
`
`
`
`
`
`
`
`
`shown in FIG. 2. Transistor 200 is formed on a silicon
`
`
`
`
`
`
`
`
`
`
`
`substrate or well 201. A gate dielectric layer 202 is formed
`
`
`
`
`
`
`
`
`
`
`
`on a surface 203 of substrate 201 and a gate electrode 204
`
`
`
`
`
`
`
`
`
`
`
`
`is in turn formed on gate dielectric layer 202. A first pair of
`
`
`
`
`
`
`
`
`
`
`
`
`
`thin sidewall spacers 206 are formed on opposite sides of
`
`
`
`
`
`
`
`
`
`
`
`
`gate electrode 204 (spacers 206 run along the “width” of
`
`
`
`
`
`
`
`
`
`
`gate electrode 204). Transistor 200 also includes a second
`
`
`
`
`
`
`
`pair of substantially thicker sidewall spacers 208 formed
`
`
`
`
`
`
`
`
`adjacent to the outside edges of the first pair of sidewall
`
`
`
`
`
`
`
`
`
`
`
`spacers 206. Transistor 200 includes a pair of source/drain
`
`
`
`
`
`
`
`
`
`regions 211 each comprising a pair of tips or source/drain
`
`
`
`
`
`
`
`
`
`
`extensions 210 and a source/drain contact region 212.
`
`
`
`
`
`
`
`
`Tip or source/drain extension 210 is defined as the source/
`
`
`
`
`
`
`
`
`
`
`drain region located beneath second sidewall spacer 208,
`
`
`
`
`
`
`
`
`first sidewall spacer 206, and the outside edge of gate
`
`
`
`
`
`
`
`
`
`
`electrode 204. Tip 210 comprises an ultra shallow tip portion
`
`
`
`
`
`
`
`
`
`
`214 and a raised tip portion 216. Ultra shallow tip portion
`
`
`
`
`
`
`
`
`
`
`
`214 is comprised of a doped semiconductor substrate 215
`
`
`
`
`
`
`
`
`formed by “out diffusing” dopants from selectively depos-
`
`
`
`
`
`
`
`ited semiconductor material 217 into substrate 201. Ultra
`
`
`
`
`
`
`
`
`shallow tip 214 extends from beneath first sidewall spacer
`
`
`
`
`
`
`
`
`
`206 to the outside edges of gate electrode 204. Ultra shallow
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`tip 214 preferably extends at least 100 A beneath (laterally)
`
`
`
`
`
`
`
`
`
`
`
`gate electrode 204 and preferably 500 A for a transistor with
`an effective gate length of approximately 0.10 microns (or
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1000
`and a drawn gate length of 0.2 gm. Additionally,
`
`
`
`
`
`
`
`
`
`
`ultra shallow tip 214 preferably extends less than 1000 A
`deep into substrate 201 beneath substrate surface 203 for a
`
`
`
`
`
`
`
`
`
`
`0.10 pm effective gate length. It is to be appreciated that
`
`
`
`
`
`
`
`
`
`
`
`because novel methods of fabrication are employed in the
`
`
`
`
`
`
`
`
`
`
`Page 17 of 29
`
`

`

`6,165,826
`
`
`
`
`
`
`5
`present invention, ultra shallow tip 214 can be characterized
`
`
`
`
`
`
`
`
`by a very abrupt junction.
`
`
`
`
`
`Tip 210 of transistor 200 also includes a raised tip portion
`
`
`
`
`
`
`
`
`
`
`216. Raised tip portion 216 is located beneath second
`
`
`
`
`
`
`
`
`
`sidewall spacer 208 and is adjacent to the outside edges of
`
`
`
`
`
`
`
`
`
`
`
`first sidewall spacer 206. Raised tip 216 is preferably formed
`
`
`
`
`
`
`
`
`
`
`of doped semiconductor material 217 selectively deposited
`
`
`
`
`
`
`
`both above and below surface 203 of semiconductor sub-
`
`
`
`
`
`
`
`
`strate 201. Raised tip portion 216 also includes a portion 215
`
`
`
`
`
`
`
`
`
`
`doped by “out diffusing” dopants from selectively deposited
`
`
`
`
`
`
`
`
`semiconductor material 217 into substrate 201. Because a
`
`
`
`
`
`
`
`
`portion of raised tip 216 is formed above semiconductor
`
`
`
`
`
`
`
`
`
`substrate surface 203, raised tip 216 is said to be “raised”. A
`
`
`
`
`
`
`
`
`
`
`
`
`raised tip significantly reduces the parasitic resistance of
`
`
`
`
`
`
`
`
`transistor 200 and thereby improves its performance.
`
`
`
`
`
`
`
`A pair of source/drain contact regions 212 are formed
`
`
`
`
`
`
`
`
`
`adjacent to the outside edge of second sidewall spacer 208.
`
`
`
`
`
`
`
`
`
`
`Source/drain contact regions 212 comprise selectively
`
`
`
`
`
`
`deposited semiconductor material 217 and “out diffused”
`
`
`
`
`
`
`
`doped semiconductor substrate 215. Source/drain contact
`
`
`
`
`
`
`regions 212 are partially raised source/drain regions. Silicide
`
`
`
`
`
`
`
`
`218 is preferably formed on source/drain regions 212 in
`
`
`
`
`
`
`
`
`
`order to reduce the contact resistance of transistor 200.
`
`
`
`
`
`
`
`
`
`Additionally, according to the present invention, first semi-
`
`
`
`
`
`
`
`conductor material 217 is preferably deposited onto the top
`
`
`
`
`
`
`
`
`
`surface of gate electrode 204. Silicide 218 is also preferably
`
`
`
`
`
`
`
`
`
`
`formed on deposited semiconductor material 217 on gate
`
`
`
`
`
`
`
`
`electrode 204 to help improve contact resistance.
`
`
`
`
`
`
`
`Additionally, if desired, source/drain contact regions 212
`
`
`
`
`
`
`
`can be made into deep junction source/drain contacts by ion
`
`
`
`
`
`
`
`
`
`
`implanting or diffusing additional dopants into a region 220
`
`
`
`
`
`
`
`
`
`in substrate 201 in alignment with the outside edges of
`
`
`
`
`
`
`
`
`
`
`second sidewall spacers 208.
`
`
`
`
`It is to be appreciated that a valuable feature of the present
`
`
`
`
`
`
`
`
`
`invention is the fact that transistor 200 includes a tip or
`
`
`
`
`
`
`
`
`
`
`source/drain extension 210 which is both ultra shallow and
`
`
`
`
`
`
`
`
`raised. In this way, transistor 200 has a shallow tip with a
`
`
`
`
`
`
`
`
`
`
`
`very low parasitic resistance. The novel structure of tran-
`
`
`
`
`
`
`
`
`sistor 200 allows for tip scaling necessary for the fabrication
`
`
`
`
`
`
`
`
`
`
`of transistor 200 with effective gate length less than 0.12 gm.
`
`
`
`
`
`
`
`
`
`
`
`Because of the novel
`tip structure 210 of the present
`
`
`
`
`
`
`
`
`
`
`invention,
`transistor 200 has good punchthrough perfor-
`
`
`
`
`
`
`mance and reduced VT roll-off. Additionally, because of tip
`
`
`
`
`
`
`
`
`
`210, transistor 200 has a low parasitic resistance, resulting in
`
`
`
`
`
`
`
`
`
`good drive current.
`
`
`
`The present invention describes several methods of inte-
`
`
`
`
`
`
`
`grating the fabrication of a transistor with a low resistance
`
`
`
`
`
`
`
`
`
`ultra shallow tip into a CMOS process (i.e. into a process
`
`
`
`
`
`
`
`
`
`
`
`where both n-type and p-type transistors are formed).
`
`
`
`
`
`
`
`
`According to a first preferred method of the present
`
`
`
`
`
`
`
`
`
`invention, as illustrated in FIGS. 3a—3h, a PMOS transistor
`
`
`
`
`
`
`
`
`
`having a low resistance ultra shallow tip is fabricated with
`
`
`
`
`
`
`
`
`
`
`a conventional NMOS transistor. According to the preferred
`
`
`
`
`
`
`
`
`method of the present invention, a silicon substrate 300 is
`
`
`
`
`
`
`
`
`
`
`provided. A plurality of field isolation regions 305 are
`
`
`
`
`
`
`
`
`
`formed in substrate 300 to isolate wells of different conduc-
`
`
`
`
`
`
`
`
`
`tivity types and to isolate adjacent transistors. Field isolation
`
`
`
`
`
`
`
`
`
`
`regions 305 are preferably shallow trench isolation (STI)
`
`
`
`
`
`
`
`regions formed by etching a trench into substrate 300 and
`
`
`
`
`
`
`
`
`
`
`then filling the trench with a deposited oxide. Although STI
`
`
`
`
`
`
`
`
`
`
`isolation regions are preferred because of their ability to be
`
`
`
`
`
`
`
`
`
`
`formed to small dimensions with a high degree of planarity,
`
`
`
`
`
`
`
`
`
`
`other methods can be used such as, but not
`limited to,
`
`
`
`
`
`
`
`
`
`
`
`LOCOS, recessed LOCOS, or silicon on insulator (SOI),
`
`
`
`
`
`
`
`
`and suitable insulators, other than oxides, such as nitrides
`
`
`
`
`
`
`
`
`
`may be used if desired.
`
`
`
`
`
`
`
`
`
`
`
`5
`
`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`30
`
`
`
`35
`
`
`
`40
`
`
`
`45
`
`
`50
`
`
`
`55
`
`
`
`60
`
`
`
`65
`
`
`Page 18 of 29
`
`
`6
`Silicon substrate 300 includes a first region 302 of p-type
`
`
`
`
`
`
`
`
`
`
`conductivity in the range of 1><1017/cm3—1><1019/cm3 and a
`
`
`
`
`
`
`
`second region 304 of n-type conductivity in the range of
`
`
`
`
`
`
`
`
`
`
`1><1017/cm3—1><1019/cm3. According to the preferred
`
`
`
`
`
`embodiment, n-type conductivity region 304 is a n-well
`
`
`
`
`
`
`
`
`formed by a first implant of phosphorous atoms at a dose of
`
`
`
`
`
`
`
`
`
`
`
`
`4><1013/cm2 and an energy of 475 keV, a second implant of
`
`
`
`
`
`
`
`
`
`
`
`phosphorous atoms at a dose of 2.5><1012/cm2 at an energy
`
`
`
`
`
`
`
`
`
`of 60 keV, and a final implant of arsenic atoms at a dose of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1><1013/cm2 at an energy of 180 keV into a silicon substrate
`
`
`
`
`
`
`
`
`
`
`
`
`
`300 having a concentration of 1><1016/cm3 in order to
`
`
`
`
`
`
`
`produce a n-well 304 having a n-type concentration of
`
`
`
`
`
`
`
`
`
`approximately 7.0><1017/cm3. Additionally, according to the
`
`
`
`
`
`
`preferred embodiment of the present invention, p-type con-
`
`
`
`
`
`
`
`ductivity region 302 is a p-well formed by a first implant of
`
`
`
`
`
`
`
`
`
`
`
`
`boron atoms at a dose of 3.0><1013/cm2 at an energy of 230
`
`
`
`
`
`
`
`
`
`
`
`keV followed by a second implant of boron ions at a dose of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`4.2><1013/cm3 and an energy of 50 keV into substrate 300 in
`
`
`
`
`
`
`
`
`
`
`order to produce a p-well 302 having a p-concentration of
`
`
`
`
`
`
`
`
`
`
`7.0><1017/cm3. It is to be appreciated that p-type conductivity
`
`
`
`
`
`
`
`
`region 302 and n-type conductivity 304 may be formed by
`
`
`
`
`
`
`
`
`
`
`other means including providing an initially doped substrate,
`
`
`
`
`
`
`
`
`or depositing an insitu doped semiconductor material with a
`
`
`
`
`
`
`
`
`
`desired conductivity. According to the present invention, a
`
`
`
`
`
`
`
`
`substrate is defined as the starting material on which the
`
`
`
`
`
`
`
`
`
`
`transistors of t