111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US007126174B2
`
`c12) United States Patent
`Segawa et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,126,174 B2
`Oct. 24, 2006
`
`(54) SEMICONDUCTOR DEVICE AND METHOD
`OF MANUFACTURING THE SAME
`
`(75)
`
`Inventors: Mizuki Segawa, Osaka (JP); Isao
`Miyanaga, Osaka (JP); Toshiki Yabu,
`Osaka (JP); Takashi Nakabayashi,
`Osaka (JP); Takashi Uehara, Osaka
`(JP); Kyoji Yamashita, Osaka (JP);
`Takaaki Ukeda, Osaka (JP); Masatoshi
`Arai, Osaka (JP); Takayuki Yamada,
`Osaka (JP); Michikazu Matsumoto,
`Osaka (JP)
`
`(73) Assignee: Matsushita Electric Industrial Co.,
`Ltd., Osaka (JP)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 10/995,283
`
`(22) Filed:
`
`Nov. 24, 2004
`
`(65)
`
`Prior Publication Data
`
`US 2005/0093089 Al May 5, 2005
`
`Related U.S. Application Data
`
`(62) Division of application No. 10/454,682, filed on Jun.
`5, 2003, now Pat. No. 6,967,409, which is a division
`of application No. 09/902,157, filed on Jul. 11,2001,
`now Pat. No. 6,709,950, which is a division of
`application No. 08/685,726, filed on Jul. 24, 1996,
`now Pat. No. 6,281,562.
`
`(30)
`
`Foreign Application Priority Data
`
`Jul. 27, 1995
`Dec. 19, 1995
`
`(JP)
`(JP)
`
`................................... 7-192181
`................................... 7-330112
`
`(51)
`
`Int. Cl.
`HOJL 29176
`(2006.01)
`(52) U.S. Cl. ................ 257/288; 257/336; 257/E23.001
`
`(58) Field of Classification Search ................ 257/384,
`257/336,288,333,386,389,401,396
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,578,128 A
`4,966,870 A
`
`3/1986 Mundt et a!.
`10/1990 Barber et al.
`
`(Continued)
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`
`0234988 A1
`
`7/1987
`
`(Continued)
`
`Primary Examiner-Roy Potter
`(74) Attorney, Agent, or Firm-McDermott Will & Emery
`LLP
`
`(57)
`
`ABSTRACT
`
`An isolation which is higher in a stepwise manner than an
`active area of a silicon substrate is formed. On the active
`area, an FET including a gate oxide film, a gate electrode, a
`gate protection film, sidewalls and the like is formed. An
`insulating film is deposited on the entire top surface of the
`substrate, and a resist film for exposing an area stretching
`over the active area, a part of the isolation and the gate
`protection film is formed on the insulating film. There is no
`need to provide an alignment margin for avoiding interfer(cid:173)
`ence with the isolation and the like to a region where a
`connection hole is formed. Since the isolation is higher in a
`stepwise manner than the active area, the isolation is pre(cid:173)
`vented from being removed by over-etch in the formation of
`a connection hole to come in contact with a portion where
`an impurity concentration is low in the active area. In this
`manner, the integration of a semiconductor device can be
`improved and an area occupied by the semiconductor device
`can be decreased without causing degradation of junction
`voltage resistance and increase of a junction leakage current
`in the semiconductor device.
`
`20 Claims, 21 Drawing Sheets
`
`34a
`
`7b
`
`Global Foundaries US v. Godo Kaisha
`Global Ex. 1001
`
`Page 1 of 38
`
`

`

`US 7,126,174 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`111993 Manning
`5,177,028 A
`3/1993 Moriuchi et a!.
`5,196,910 A
`2/1994 Roth eta!.
`5,286,674 A
`6/1994 Kihara eta!.
`5,319,235 A
`111995 Kenney et al.
`5,384,281 A
`2/1995 Hsia eta!.
`5,393,708 A
`3/1995 Ishimaru
`5,397,910 A
`3/1995 Urayama
`5,401,673 A
`5/1995 Kim
`5,413,961 A
`7/1995 Fazan et al.
`5,433,794 A
`3/1996 Koh
`5,497,016 A
`5/1996 Mandelman et a!.
`5,521,422 A
`10/1996 Hamamoto et a!.
`5,561,311 A
`7/1998 Omid-Zohoor eta!.
`5,777,370 A
`9/1998 Matumoto
`5,804,862 A
`5,817,562 A * 10/1998 Chang eta!. ............... 438/305
`212000 Noble, Jr.
`6,022,781 A
`6,077,344 A
`6/2000 Shoup eta!.
`6,278,138 B1
`8/2001 Suzuki
`6,281,562 B1
`8/2001 Segawa et al.
`
`EP
`EP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`
`0 513 639
`0 706 206 A2
`59181062 A
`62-85461
`03079033 A
`4-48647
`4-68564
`4-305922
`06-21208
`6-45432
`6-163843
`06-177237
`08-196495
`07-142726
`07-153939
`7-273330
`09162392 A
`
`1111992
`4/1996
`10/1984
`4/1987
`4/1991
`2/1992
`3/1992
`10/1992
`111994
`2/1994
`6/1994
`6/1994
`7/1994
`6/1995
`6/1995
`10/1995
`6/1997
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`
`0 243 988
`
`1111987
`
`* cited by examiner
`
`Page 2 of 38
`
`

`

`U.S. Patent
`
`Oct. 24,2006
`
`Sheet 1 of 21
`
`US 7,126,174 B2
`
`50 a
`
`2x
`
`2b
`
`2b
`
`FIG. l(b)
`
`FIG. l(c)
`
`1
`
`FIG. l(d)
`
`Page 3 of 38
`
`

`

`U.S. Patent
`
`Oct. 24,2006
`
`Sheet 2 of 21
`
`US 7,126,174 B2
`
`2b
`
`FIG. 2(a)
`
`FIG.2(b)
`
`FIG.2(c)
`
`FIG.2(d)
`
`FIG.2(e)
`
`Page 4 of 38
`
`

`

`U.S. Patent
`
`Oct. 24,2006
`
`Sheet 3 of 21
`
`US 7,126,174 B2
`
`FIG. 3(a)
`
`FIG. 3(b)
`
`FIG. 3(c)
`
`FIG. 3(d)
`
`FIG. 3(e)
`
`FIG. 3(f)
`
`2b
`
`t.x
`
`2Sa
`
`13
`
`Page 5 of 38
`
`

`

`U.S. Patent
`
`Oct. 24,2006
`
`Sheet 4 of 21
`
`US 7,126,174 B2
`
`7b
`
`FIG. 4(a)
`
`8 6 3 6
`
`FIG.4(c)
`
`2b
`
`25b
`
`13
`
`Page 6 of 38
`
`

`

`U.S. Patent
`
`Oct. 24, 2006
`
`Sheets of 21
`
`US 7,126,174 B2
`
`L.b
`
`Sc
`
`FIG. 5(a)
`
`FIG.5(b)
`
`FIG.5(c)
`
`Page 7 of 38
`
`

`

`U.S. Patent
`
`Oct. 24,2006
`
`Sheet 6 of 21
`
`US 7,126,174 B2
`
`2b
`
`4x
`
`2b
`1
`
`25d
`
`1
`
`FIG. 6(a)
`
`FIG. 6(b)
`
`FIG.6(c)
`
`FIG.6(F)
`
`Page 8 of 38
`
`

`

`U.S. Patent
`
`Oct. 24, 2006
`
`Sheet 7 of 21
`
`US 7,126,174 B2
`
`15a
`
`t.a
`
`7c
`
`l.b
`
`b
`
`25e
`
`13
`
`FIG. 7(a)
`
`FIG. 7(b)
`
`FIG. 7(c)
`
`Page 9 of 38
`
`

`

`U.S. Patent
`
`Oct. 24, 2006
`
`Sheet 8 of 21
`
`US 7,126,174 B2
`
`25a
`1 1
`
`20
`
`25a
`
`23
`
`FIG.8(a)
`
`1
`
`FIG.8(b)
`
`FIG. 8(c)
`
`Page 10 of 38
`
`

`

`U.S. Patent
`
`Oct. 24,2006
`
`Sheet 9 of 21
`
`US 7,126,174 B2
`
`FIG. 9(a)
`
`FIG. 9(b)
`
`FIG.9(c)
`
`25a
`
`1 1
`
`2b
`
`25a
`
`11
`
`23
`
`Page 11 of 38
`
`

`

`U.S. Patent
`
`Oct. 24, 2006
`
`Sheet 10 of 21
`
`US 7,126,174 B2
`
`FIG. lO(b)
`
`25c
`
`11
`
`23
`
`Page 12 of 38
`
`

`

`U.S. Patent
`
`Oct. 24,2006
`
`Sheet 11 of 21
`
`US 7,126,174 B2
`
`1
`
`25d
`
`11
`
`25d
`11
`
`23
`
`Page 13 of 38
`
`

`

`U.S. Patent
`
`Oct. 24, 2006
`
`Sheet 12 of 21
`
`US 7,126,174 B2
`
`FIG. 12
`
`Rei so
`~
`
`Retet
`~
`
`1
`
`Page 14 of 38
`
`

`

`U.S. Patent
`
`Oct. 24, 2006
`
`Sheet 13 of 21
`
`US 7,126,174 B2
`
`Reiso
`~
`
`Refet
`~
`. . . . ~ . . ~
`. . . ..
`. . -:.
`.
`. . .
`
`.....
`.
`. .
`
`FIG. 13(a)
`
`1
`
`7
`
`4b
`
`Page 15 of 38
`
`

`

`U.S. Patent
`U.S. Patent
`
`Oct. 24,2006
`Oct. 24, 2006
`
`Sheet 14 of 21
`Sheet 14 of 21
`
`US 7,126,174 B2
`US 7,126,174 B2
`
`. . .
`..
`. .·
`.
`.. · ...
`
`. . . . .
`
`. ...
`
` 1
`
`FIG. 14(a)
`
`“G' W”
`
`‘mun:nu‘:\“‘\“\\\‘\\‘\“\“\‘\‘\u-nu‘:
`VIIIIA
`wlllltllltlz
`:‘——“¥'
`
`2b
`
`LZCZCZCZKZCCCT»J‘
`Wllll
`' I-I-'-
`—mm
`\\\\\\“
`
`6
`
`._4___—__.4 —:.——
`h‘“CCjC:CKZCC‘ h
`wltn
`
`iii
`_,
`‘vii
`—;,,,.,, w,,,..j
`‘\\\\\\V‘
`\\V
`
`
`
`
`\\\‘
`
`Page 16 of 38
`
`Page 16 of 38
`
`

`

`U.S. Patent
`
`Oct. 24, 2006
`
`Sheet 15 of 21
`
`US 7,126,174 B2
`
`Refet
`~
`
`4a
`
`~~lF.~~{Lill~-- 31
`FIG. 15(a) ~~~~
`2b
`60
`L---------~"' 1
`c~33b
`
`FIG. 15(c)
`
`FIG. 15(d)
`
`FIG. 15(e)
`
`FIG. 15(f)
`
`Page 17 of 38
`
`

`

`U.S. Patent
`
`Oct. 24,2006
`
`Sheet 16 of 21
`
`US 7,126,174 B2
`
`Refet
`
`~ 4a
`
`15a
`
`FIG. 16(b)
`
`FIG. 16(c)
`
`FIG. 16(d)
`
`FIG. 16(e)
`
`Page 18 of 38
`
`

`

`U.S. Patent
`
`Oct. 24,2006
`
`Sheet 17 of 21
`
`US 7,126,174 B2
`
`FIG. 17
`PRIOR ART
`
`7b
`
`La
`
`1
`
`Page 19 of 38
`
`

`

`U.S. Patent
`
`Oct. 24,2006
`
`Sheet 18 of 21
`
`US 7,126,174 B2
`
`DIAMETER
`OF HOLE
`
`END OF ISOLASION
`
`25a
`
`FIG. 18(a)
`PRIOR ART
`
`FIG. 18(b)
`PRIOR ART
`
`FIG. 18(c)
`PRIOR ART
`
`Page 20 of 38
`
`

`

`U.S. Patent
`
`Oct. 24, 2006
`
`Sheet 19 of 21
`
`US 7,126,174 B2
`
`FIG. 19
`PRIOR ART
`
`112
`
`111
`
`106a 1030 106b
`
`Page 21 of 38
`
`

`

`U.S. Patent
`
`Oct. 24, 2006
`
`Sheet 20 of 21
`
`US 7,126,174 B2
`
`Rei so
`~
`
`Refet
`~
`... . .
`·.·· ....
`
`Refet
`~
`~:-:-:-:--. --=-.• -•• -. - -.. .,.........
`·· .. ··... . ...... · ... .
`.... - · .... · · ... · ...... .
`. . . -. . . -. . .. . - . . : ... .
`
`Reiso ' 120
`
`Rei so
`~
`10L.
`
`FIG. 20(b) ~
`PRIOR ART
`
`116
`
`FIG. 20 (c) ~t=====~....I.......L..~~~~.L.L..L-4
`PRIOR ART
`
`FIG. 20(d) ~
`PRIOR ART
`
`FIG. 20(e) ~
`PRIOR ART
`
`106b
`
`Page 22 of 38
`
`

`

`U.S. Patent
`
`Oct. 24, 2006
`
`Sheet 21 of 21
`
`US 7,126,174 B2
`
`FIG.21(a)
`PRIOR ART
`107a
`
`~....-....
`
`IMPURITY ION
`
`108a Ill
`
`105a
`115
`101
`
`FIG.2l(b)
`PRIOR ART
`
`Page 23 of 38
`
`

`

`US 7,126,174 B2
`
`1
`SEMICONDUCTOR DEVICE AND METHOD
`OF MANUFACTURING THE SAME
`
`This application is a divisional of application Ser. No.
`10/454,682 filed Jun. 5, 2003, now U.S. Pat. No. 6,967,409,
`which is a divisional of application Ser. No. 09/902,157 filed
`Jul. 11, 2001, now U.S. Pat. No. 6,709,950, which is a
`divisional of application Ser. No. 08/685,726 filed on Jul. 24,
`1996, which is now U.S. Pat. No. 6,281,562.
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a semiconductor device
`including transistors and connection between the transistors
`for constituting an LSI with high integration and a decreased
`area.
`With the recent development of a semiconductor device
`with high integration and high performance, there are
`increasing demands for more refinement of the semiconduc(cid:173)
`tor device. The improvement of the conventional techniques
`cannot follow these demands, and novel techniques are
`unavoidably
`introduced in some technical fields. For
`example, as a method of forming an isolation, the LOCOS
`isolation method is conventionally adopted in view of its
`simpleness and low cost. Recently, however, it is considered 25
`that a trench buried type isolation (hereinafter referred to as
`the trench isolation) is more advantageous for manufactur(cid:173)
`ing a refined semiconductor device.
`Specifically, in the LOCOS isolation method, since selec(cid:173)
`tive oxidation is conducted, the so-called bird's beak occurs 30
`in the boundary with a mask for preventing the oxidation. As
`a result, the dimension of a transistor is changed because an
`insulating film of the isolation invades a transistor region
`against the actually designed mask dimension. This dimen(cid:173)
`sional change is unallowable in the refinement of a semi- 35
`conductor device after the 0.5 f.tm generation. Therefore,
`even in the mass-production techniques, the isolation form(cid:173)
`ing method has started to be changed to the trench isolation
`method in which the dimensional change is very small. For
`example, IBM corporation has introduced the trench isola- 40
`tion structure as a 0.5 flill CMOS process for the mass(cid:173)
`production of an MPU (IBM Journal of Research and
`Development, VOL. 39, No. 1/2, 1995, pp. 33-42).
`Furthermore, in a semiconductor device mounting ele(cid:173)
`ments such as a MOSFET in an active area surrounded with 45
`an isolation, an insulating film is deposited on the active
`area, the isolation and a gate electrode, and a contact hole is
`formed by partly exposing the insulating film for connection
`between the active area and an interconnection member on
`a layer above the insulating film. This structure is known as
`a very common structure for the semiconductor device.
`FIG. 17 is a sectional view for showing the structure of a
`conventional semiconductor device. In FIG. 17, a reference
`numeral1 denotes a silicon substrate, a reference numeral 2b
`denotes an isolation with a trench isolation structure which 55
`is made of a silicon oxide film and whose top surface is
`flattened so as to be at the same level as the top surface of
`the silicon substrate 1, a reference numeral 3 denotes a gate
`oxide film made of a silicon oxide film, a reference numeral
`4a denotes a polysilicon electrode working as a gate elec(cid:173)
`trode, a reference numeral 4b denotes a polysilicon inter(cid:173)
`connection formed simultaneously with the polysilicon elec(cid:173)
`trode 4a, a reference numeral 6 denotes a low-concentration
`source/drain region formed by doping the silicon substrate
`with ann-type impurity at a low concentration, a reference 65
`numeral 7a denotes an electrode sidewall, a reference
`numeral 7b denotes an interconnection sidewall, a reference
`
`10
`
`2
`numeral 8 denotes a high-concentration source/drain region
`formed by doping the silicon substrate with an n-type
`impurity at a high concentration, a reference numeral 12
`denotes an insulating film made of a silicon oxide film, and
`a reference numeral13 denotes a local interconnection made
`of a polysilicon film formed on the insulating film 12.
`The local interconnection 13 is also filled within a con(cid:173)
`nection hole 14 formed in a part of the insulating film 12, so
`as to be contacted with the source/drain region in the active
`area through the connection hole 14. In this case, the
`connection hole 14 is formed apart from the isolation 2b by
`a predetermined distance. In other words, in the conven(cid:173)
`tional layout rule for such a semiconductor device, there is
`15 a rule that the edge of a connection hole is previously located
`away from the boundary between the active area and the
`isolation region so as to prevent a part of the connection hole
`14 from stretching over the isolation 2b even when a mask
`alignment shift is caused in photolithography (this distance
`20 between the connection hole and the isolation is designated
`as an alignment margin).
`However, in the structure of the semiconductor device as
`shown in FIG. 17, there arise problems in the attempts to
`further improve the integration for the following reason:
`A distance La between the polysilicon electrode 4a and
`the isolation 2b is estimated as an index of the integration.
`In order to prevent the connection hole 14 from interfering
`the isolation 2b as described above, the distance La is
`required to be 1.2 flill, namely, the sum of the diameter of the
`connection hole 14, that is, 0.5 f.tm, the width of the electrode
`sidewall 7a, that is, 0.1 f.tm, the alignment margin from the
`polysilicon electrode 4a, that is, 0.3 f.tm, and the alignment
`margin from the isolation 2b, that is, 0.3 f.tm. A connection
`hole has attained a more and more refined diameter with the
`development of processing techniques, and also a gate
`length has been decreased as small as 0.3 f.tm or less. Still,
`the alignment margin in consideration of the mask alignment
`shift in the photolithography is required to be approximately
`0.3 f.tm. Accordingly, as the gate length and the connection
`hole diameter are more refined, the proportion of the align(cid:173)
`ment margin is increased. This alignment margin has
`become an obstacle to the high integration.
`Therefore, attempts have been made to form the connec-
`tion hole 14 without considering the alignment margin in
`view of the alignment shift in the photolithography. Manu(cid:173)
`facturing procedures adopted in such a case will now be
`described by exemplifying an n-channel MOSFET referring
`50 to FIGS. 18(a) through 18(c).
`First, as is shown in FIG. 18(a), after forming an isolation
`2b having the trench structure in a silicon substrate 1 doped
`with a p-type impurity (or p-type well), etch back or the like
`is conducted for flattening so as to place the surfaces of the
`isolation 2b and the silicon substrate 1 at the same level. In
`an active area surrounded with the isolation 2b, a gate oxide
`film 3, a polysilicon electrode 4a serving as a gate electrode,
`an electrode sidewall 7a, a low-concentration source/drain
`region 6 and a high-concentration source/drain region 8 are
`60 formed. On the isolation 2b are disposed a polysilicon
`interconnection 4b formed simultaneously with the polysili(cid:173)
`con electrode 4a and an interconnection sidewall 7b. At this
`point, the top surface of the high-concentration source/drain
`region 8 in the active area is placed at the same level as the
`top surface of the isolation 2b. Then, an insulating film 12
`of a silicon oxide film is formed on the entire top surface of
`the substrate.
`
`Page 24 of 38
`
`

`

`US 7,126,174 B2
`
`3
`Next, as is shown in FIG. 18(b), a resist film 25a used as
`a mask for forming a connection hole is formed on the
`insulating film 12, and the connection hole 14 is formed by,
`for example, dry etching.
`Then, as is shown in FIG. 18(c), the resist film 25a is
`removed, and a polysilicon film is deposited on the insulat(cid:173)
`ing film 12 and within the connection hole 14. The poly(cid:173)
`silicon film is then made into a desired pattern, thereby
`forming a local interconnection 13.
`At this point, in the case where the alignment margin in
`view of the mask alignment shift in the formation of the
`connection hole 14 is not considered in estimating the
`distance La between the polysilicon electrode 4a and the
`isolation 2b, a part of the isolation 2b is included in the
`connection hole 14 when the exposing area of the resist film
`25a is shifted toward the isolation 2b due to the mask
`alignment shift in the photolithography. Through over-etch
`in conducting the dry etching of the insulating film 12,
`although the high-concentration source/drain region 8 made
`of the silicon substrate is not largely etched because of its 20
`small etching rate, the part of the isolation 2b included in the
`connection hole 14 is selectively removed, resulting in
`forming a recess 40 in part of the connection hole 14. When
`the recess 40 in the connection hole 14 has a depth exceed(cid:173)
`ing a given proportion to the depth of the high-concentration
`source/drain region 8, junction voltage resistance can be
`decreased and a junction leakage current can be increased
`because the concentration of the impurity in the high(cid:173)
`concentration source/drain region 8 is low at that depth.
`In order to prevent these phenomena, it is necessary to 30
`provide a predetermined alignment margin as is shown in the
`structure of FIG. 17 so as to prevent the connection hole 14
`from interfering the isolation 2b even when the alignment
`shift is caused in the lithography. In this manner, in the
`conventional layout rule for a semiconductor device, an 35
`alignment margin in view of the mask alignment shift in the
`photolithography is unavoidably provided.
`Furthermore, a distance between the polysilicon electrode
`4a and the connection hole 14 is also required to be provided
`with an alignment margin. Otherwise, the connection hole 40
`14 can interfere the polysilicon electrode 4a due to the
`fluctuation caused in the manufacturing procedures, result(cid:173)
`ing in causing electric short-circuit between an upper layer
`interconnection buried in the connection hole and the gate
`electrode.
`As described above, it is necessary to provide the con(cid:173)
`nection hole 14 with margins for preventing the interference
`with other elements around the connection hole, which has
`become a large obstacle to the high integration of an LSI.
`Also in the case where a semiconductor device having the
`so-called salicide structure is manufactured, the following
`problems are caused due to a recess formed in the isolation:
`FIG. 19 is a sectional view for showing an example of a
`semiconductor device including the conventional trench
`isolation and a MOSFET having the salicide structure. As is
`shown in FIG. 19, a trench isolation 105a is formed in a
`silicon substrate 101. In an active area surrounded with the
`isolation 105a, a gate insulating film 103a, a gate electrode
`107a, and electrode sidewalls 108a on both side surfaces of
`the gate electrode 107a are formed. Also in the active area,
`a low-concentration source/drain region 106a and a high(cid:173)
`concentration source/drain region 106b are formed on both
`sides of the gate electrode 107a. A channel stop region 115
`is formed below the isolation 105a. Furthermore, in areas of
`the silicon substrate 101 excluding the isolation 105a and
`the active area, a gate interconnection 107b made of the
`same polysilicon film as that for the gate electrode 107a is
`
`4
`formed with a gate insulating film 103b sandwiched, and the
`gate interconnection 107b is provided with interconnection
`sidewalls 108b on its both side surfaces. On the gate
`electrode 107a, the gate interconnection 107b and the high(cid:173)
`concentration source/drain region 106b, an upper gate elec(cid:173)
`trode 109a, an upper gate interconnection 109b and a
`source/drain electrode 1 09c each made of silicide are respec(cid:173)
`tively formed. Furthermore, this semiconductor device
`includes an interlayer insulating film 111 made of a silicon
`10 oxide film, a metallic interconnection 112 formed on the
`interlayer insulating film 111, and a contact member 113
`(buried conductive layer) filled in a connection hole formed
`in the interlayer insulating film 111 for connecting the
`metallic interconnection 112 with the source/drain electrode
`15 109c.
`Now, the manufacturing procedures for the semiconduc(cid:173)
`tor device including the conventional trench isolation and
`the MOSFET with the salicide structure shown in FIG. 19
`will be described referring to FIGS. 20(a) through 20(e).
`First, as is shown in FIG. 20(a), a silicon oxide film 116
`and a silicon nitride film 117 are successively deposited on
`a silicon substrate 101, and a resist film 120 for exposing an
`isolation region and masking a transistor region is formed on
`the silicon nitride film 117. Then, by using the resist film 120
`25 as a mask, etching is conducted, so as to selectively remove
`the silicon nitride film 116 and the silicon oxide film 117,
`and further etch the silicon substrate 101, thereby forming a
`trench 104. Then, impurity ions are injected into the bottom
`of the trench 104, thereby forming a channel stop region 115.
`Then, as is shown in FIG. 20(b), a silicon oxide film (not
`shown) is deposited, and the entire top surface is flattened
`until the surface of the silicon nitride film 117 is exposed.
`Through this procedure, a trench isolation 105a made of the
`silicon oxide film filled in the trench 104 is formed in the
`isolation region Reiso.
`Next, as is shown in FIG. 20(c), after the silicon nitride
`film 117 and the silicon oxide film 116 are removed, a gate
`oxide film 103 is formed on the silicon substrate 101, and a
`polysilicon film 107 is deposited thereon. Then, a photore(cid:173)
`sist film 121 for exposing areas excluding a region for
`forming a gate is formed on the polysilicon film 107.
`Then, as is shown in FIG. 20(d), by using the photoresist
`film 121 as a mask, dry etching is conducted, thereby
`selectively removing the polysilicon film 107 and the gate
`45 oxide film 103. Thus, a gate electrode 107a of the MOSFET
`in the transistor region Refet and a gate interconnection
`107b stretching over the isolation 105a and the silicon
`substrate 101 are formed. After removing the photoresist
`film 121, impurity ions are injected into the silicon substrate
`50 101 by using the gate electrode 107a as a mask, thereby
`forming a low-concentration source/drain region 106a.
`Then, a silicon oxide film 108 is deposited on the entire top
`surface of the substrate.
`Next, as is shown in FIG. 20(e), the silicon oxide film 108
`55 is anisotropically dry-etched, thereby forming electrode
`sidewalls 108a and interconnection sidewalls 108b on both
`side surfaces of the gate electrode 107a and the gate inter(cid:173)
`connection 107b, respectively. At this point, the gate oxide
`film 103 below the silicon oxide film 108 is simultaneously
`60 removed, and the gate oxide film 103 below the gate
`electrode 107a alone remains. Then, impurity ions are
`diagonally injected by using the gate electrode 107a and the
`electrode sidewalls 108a as masks, thereby forming a high(cid:173)
`concentration source/drain region 106b. Then, after a Ti film
`65 is deposited on the entire top surface, high temperature
`annealing is conducted, thereby causing a reaction between
`the Ti film and the components made of silicon directly in
`
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`

`5
`contact with the Ti film. Thus, an upper gate electrode 109a,
`an upper gate interconnection 109b and a source/drain
`electrode 109c made of silicide are formed. The procedures
`to be conducted thereafter are omitted, but the semiconduc-
`tor device including the MOSFET having the structure as
`shown in FIG. 19 can be ultimately manufactured. In FIG.
`19, the metallic interconnection 112 is formed on the inter(cid:173)
`layer insulating film 111, and the metallic interconnection
`112 is connected with the source/drain electrode 109c
`through the contact member 113 including a W plug and the 10
`like filled in the contact hole.
`When the aforementioned trench isolation structure is
`adopted, the dimensional change of the source/drain region
`can be suppressed because the bird's beak, that is, the oxide
`film invasion of an active area, which is caused in the
`LOCOS method where a thick silicon oxide film is formed
`by thermal oxidation, can be avoided. Furthermore, in the
`procedure shown in FIG. 20(c), the surfaces of the isolation
`105a and the silicon substrate 101 in the transistor region
`Refet are placed at the same level.
`In such a semiconductor device having the trench type
`isolation, however, there arise the following problems:
`When the procedures proceed from the state shown in
`FIG. 20(d) to the state shown in FIG. 20(e), the silicon oxide
`film 108 is anisotropically etched so as to form the sidewalls 25
`108a and 108b. At this point, over-etch is required. Through
`this over-etch, the surface of the isolation 1 05a is removed
`by some depth.
`FIGS. 21(a) and 21(b) are enlarged sectional views
`around the boundary between the high-concentration source/ 30
`drain region 1 06b and the isolation 1 05a after this over-etch.
`As is shown in FIG. 21(a), between the procedures shown
`in FIGS. 20(d) and 20(e), the impurity ions are diagonally
`injected so as to form the high-concentration source/drain
`region 106b. Through this ion injection, the high-concen- 35
`tration source/drain region 106b is formed also below the
`edge of the isolation 105a because the isolation 105a is
`previously etched by some depth. Accordingly, the high(cid:173)
`concentration source/drain region 106b is brought closer to
`the charmel stop region 115, resulting in causing the prob- 40
`!ems of degradation of the junction voltage resistance and
`increase of the junction leakage current.
`In addition, as is shown in FIG. 21(b), in the case where
`the Ti film or the like is deposited on the high-concentration
`source/drain region 106b so as to obtain the silicide layer 45
`through the reaction with the silicon below, the thus formed
`silicide layer can invade the interface between the silicon
`substrate 101 and the isolation 105a with ease. As a result,
`a short-circuit current can be caused between the source/
`drain electrode 109c made of silicide and the channel stop 50
`region 115.
`
`SUMMARY OF THE INVENTION
`
`The object of the present invention is improving the 55
`structure of an isolation, so as to prevent the problems
`caused because the edge of the isolation is trenched in
`etching for the formation of a connection hole or sidewalls.
`In order to achieve the object, the invention proposes first
`and second semiconductor devices and first through third 60
`methods of manufacturing a semiconductor device as
`described below.
`The first semiconductor device of this invention in which
`a semiconductor element is disposed in each of plural active
`areas in a semiconductor substrate comprises an isolation for
`surrounding and isolating each active area, the isolation
`having a top surface at a higher level than a surface of the
`
`US 7,126,174 B2
`
`6
`active area and having a step portion in a boundary with the
`active area; an insulating film formed so as to stretch over
`each active area and the isolation; plural holes each formed
`by removing a portion of the insulating film disposed at least
`on the active area; plural buried conductive layers filled in
`the respective holes; and plural interconnection members
`formed on the insulating film so as to be connected with the
`respective active areas through the respective buried con-
`ductive layers.
`Owing to this structure, in the case where a part of or all
`the holes are formed so as to stretch over the active areas and
`the isolation due to mask alignment shift in photolithogra(cid:173)
`phy, a part of the isolation is removed by over-etch for
`ensuring the formation of the holes. In such a case, even
`15 when the top surface of the isolation is trenched to be lower
`than the surface of the active area, the depth of the holes
`formed in the isolation is small in the boundary with the
`active area because of the level difference between the top
`surface of the isolation and the surface of the active area.
`20 Accordingly, degradation of the junction voltage resistance
`and increase of the junction leakage current can be sup(cid:173)
`pressed. Therefore, there is no need to provide a portion of
`the active area where each hole is formed with an alignment
`margin for avoiding the interference with the isolation
`caused by the mask alignment shift in the lithography. Thus,
`the area of the active area can be decreased, resulting in
`improving the integration of the semiconductor device.
`In the first semiconductor device, at least a part of the
`plural holes can be formed so as to stretch over the active
`area and the isolation due to fluctuation in manufacturing
`procedures.
`In other words, even when no margin for the mask
`alignment in the lithography is provided, the problems
`caused in the formation of the holes can be avoided.
`Furthermore, the angle between a side surface of the step
`portion and the surface of the active area is preferably 70
`degrees or more.
`As a result, when the hole interferes the isolation, the part
`of the isolation included in the hole is definitely prevented
`from being etched through over-etch in the formation of the
`holes down to a depth where the impurity concentration is
`low in the active area.
`The isolation is preferably a trench isolation made of an
`insulating material filled in a trench formed by trenching the
`semiconductor substrate by a predetermined depth.
`This is because no bird's beak is caused in the trench
`isolation differently from a LOCOS film as described above,
`and hence, the trench isolation is suitable particularly for the
`high integration and refinement of the semiconductor
`device.
`In the first semiconductor device, when the semiconduc(cid:173)
`tor element is a MISFET including a gate insulating film and
`a gate electrode formed on the active area; and source/drain
`regions formed in the active area on both sides of the gate
`electrode, the following preferred embodiments can be
`adopted:
`The semiconductor device can further comprise a gate
`interconnection made of the same material as that for the
`gate electrode and formed on the isolation, each of the holes
`can be formed on an area including the source/drain region,
`the isolation and the gate interconnection, and the plural
`interconnection members can be connected with the gate
`interconnection on the isolation.
`Owing to this configuration, in the case where the inter-
`65 connection members work as local interconnections for
`connecting a gate interconnection on the isolation with the
`active area, there is no need to separately form holes in the
`
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`US 7,126,174 B2
`
`8
`Also in the second semiconductor device, the semicon(cid:173)
`ductor element can be a MISFET including a gate insulating
`film and a gate electrode formed on the active area; and
`source/drain regions formed in the active area on both sides
`of the gate electrode. This semiconductor device can be
`further provided with electrode sidewalls formed on both
`side surfaces of the gate electrode, and the step sidewall can
`be formed simultaneously with the electrode sidewalls.
`Owing to this structure, the semiconductor elements can
`be a MISFET having the LDD structure suitable for the
`refinement. Because of this structure together with the
`trench isolation structure, the semiconductor device can
`attain a structure particularly suitable for the refinement and
`15 the high integration.
`The first method of manufacturing a semiconductor
`device in which a semiconductor element is disposed in each
`of plural active areas in a semiconductor substrate comprises
`a first step of forming an isolation in a part of the semicon-
`20 ductor substrate, the isolation having a top surface at a
`higher level than a surface of the semiconductor substrate
`and having a step portion in a boundary with the surface of
`the semiconductor substrate; a second step of introducing an
`impurity at a high concentration into each active area of the
`25 semiconductor substrate surrounded by the isolation; a third
`step of forming an in