CERTIFICATE OF TRANSLATION
`
`I Roger P. Lewis, whose address is 42 Bird Street North,
`Martinsburg WV 25401, declare and state the following:
`
`I am well acquainted with the English and Japanese languages
`and have in the past translated numerous English/Japanese
`documents of legal and/or technical content.
`
`I hereby certify that the Japanese translation of the
`attached document identified as:
`
`JP7-330112 and related Office Actions
`
`is true, and that all statements of information and belief
`are believed to be true, and that these and similar
`statements are punishable by fines or imprisonment, or both,
`under Section 1001 of Title 18 of the United States Code.
`
`SINCERELY,
`
`ROGER P. LEWIS
`
`Date: June 10, 2016
`
`1
`
`Global Foundaries US v. Godo Kaisha
`Global Ex. 1023
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`Page 1 of 193
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`[Document Name] Patent Application
`[Patent] H7-330112 (December 19, 1995)
`
`[Received Date] December 19, 1995
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`Page: 1/ 3
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`[Document Name]
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`[Docket Number]
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`[Submission Date]
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`[Submitted to]
`
`
`
`
`
`
`
`
`
`Patent Application
`
`2020270244
`
`December 19, 1995
`
`Commissioner of Japan Patent Office
`
`[International Patent Classification] H01L 21/76
`
`[Title of the Invention]
`
`SEMICONDUCTOR DEVICE AND MANUFACTURING
`
`METHOD THEREOF
`
`[Number of claims]
`
`
`
` 12
`
`[Inventor]
`
`
`
`
`
`
`
`[Address or Domicile] Matsushita Electric Industrial Co., Ltd.
`
`
`
`
`
`[Name]
`
`
`
`
`
`
`
`
`
`1006, Kadoma, Kadoma-shi, Osaka-fu
`
`Toshiki Yabu
`
`[Inventor]
`
`
`
`
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`
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`[Address or Domicile] Matsushita Electric Industrial Co., Ltd.
`
`
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`[Name]
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`
`
`
`
`
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`
`
`1006, Kadoma, Kadoma-shi, Osaka-fu
`
`Takashi Uehara
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`[Inventor]
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`
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`[Address or Domicile] Matsushita Electric Industrial Co., Ltd.
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`[Name]
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`1006, Kadoma, Kadoma-shi, Osaka-fu
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`Mizuki Segawa
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`[Inventor]
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`[Address or Domicile] Matsushita Electric Industrial Co., Ltd.
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`[Name]
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`
`
`1006, Kadoma, Kadoma-shi, Osaka-fu
`
`Takashi Nakabayashi
`
`[Inventor]
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`[Address or Domicile] Matsushita Electric Industrial Co., Ltd.
`
`
`
`
`
`[Name]
`
`
`
`
`
`
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`
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`1006, Kadoma, Kadoma-shi, Osaka-fu
`
`Kyoji Yamashita
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`
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`Page 2 of 193
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`[Document Name] Patent Application
`[Patent] H7-330112 (December 19, 1995)
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`[Received Date] December 19, 1995
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`Page: 2/ 3
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`[Inventor]
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`[Address or Domicile] Matsushita Electric Industrial Co., Ltd.
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`[Name]
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`
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`
`
`
`
`1006, Kadoma, Kadoma-shi, Osaka-fu
`
`Takaaki Ukeda
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`[Inventor]
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`
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`
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`[Address or Domicile] Matsushita Electric Industrial Co., Ltd.
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`
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`[Name]
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`
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`
`
`1006, Kadoma, Kadoma-shi, Osaka-fu
`
`Masatoshi Arai
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`[Inventor]
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`[Address or Domicile] Matsushita Electric Industrial Co., Ltd.
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`
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`[Name]
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`1006, Kadoma, Kadoma-shi, Osaka-fu
`
`Takakazu Yamada
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`[Inventor]
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`[Address or Domicile] Matsushita Electric Industrial Co., Ltd.
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`
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`[Name]
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`1006, Kadoma, Kadoma-shi, Osaka-fu
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`Michikazu Matsumoto
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`[Applicant]
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`[Identification Number] 000005821
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`[Name or Title]
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`[Representative]
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`Matsushita Electric Industrial Co., Ltd.
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`Yoichi Morishita
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`[Agent]
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`[Identification Number] 100077931
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`[Patent Attorney]
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`[Name or Title]
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`
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`Hiroshi Maeda
`
`[Appointed Agent]
`
`[Identification Number] 100094134
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`[Patent Attorney]
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`[Name or Title]
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`
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`Hirotake Koyama
`
`
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`Page 3 of 193
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`[Document Name] Patent Application
`[Patent] H7-330112 (December 19, 1995)
`
`[Received Date] December 19, 1995
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`Page: 3/ 3
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`
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`[Indication of Fees]
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`[Payment Method]
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`Deposit
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`[Deposit Account Number]
`
`014409
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`[Amount deposited]
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`21,000 JPY
`
`[List of Submitted Items]
`
`
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`[Item Name]
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`[Item Name]
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`[Item Name]
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`Specification 1
`
`Drawings
`
`Abstract
`
`1
`
`1
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`[General Power of Attorney Number]
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`9006026
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`[Necessity of Proof]
`
`
`
`Necessary
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`Page 4 of 193
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`

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`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
`
`[Document Name]
`
`Specification
`
`[Received Date] December 19, 1995
`
`Page: 1/ 32
`
`[Title of the Invention]
`
`SEMICONDUCTOR DEVICE AND MANUFACTURING
`
`METHOD THEREOF
`
`[Claims]
`
`1. A semiconductor device, comprising:
`
`
`
`
`
`
`
`a semiconductor substrate,
`
`an element formation region placed in a portion of the substrate,
`
`groove-type element isolation that surrounds the element formation region, and that
`
`comprises a height difference part, which becomes higher in a step manner than the
`
`semiconductor substrate of the element formation region, with the element formation region, and
`
`that is made from an insulating material, and
`
`
`
`height difference-part sidewalls formed on side surfaces of the height difference part between
`
`the element formation region and the groove-type element isolation.
`
`
`
`2. The semiconductor device according to claim 1, wherein
`
`the height difference-part sidewalls are formed with an insulating material.
`
`
`
`
`
`3. The semiconductor device according to claim 1, wherein
`
`
`
`a MISFET, comprising: a gate electrode and electrode-part sidewalls on both side surfaces of
`
`the gate electrode is formed in the element formation region, and
`
`
`
`the height difference-part sidewalls are formed at the same time as the electrode-part
`
`sidewalls.
`
`
`
`4. The substrate device according to claim 3,
`
`
`
`the electrode-part sidewalls are formed with an L-shaped silicon nitride film with
`
`substantially constant thickness that is formed via a protective oxide film throughout the side
`
`surfaces of the gate electrode onto the semiconductor substrate; and
`
`
`
`the height difference-part sidewalls are formed with an L-shaped silicon nitride film with
`
`substantially constant thickness that are formed via a protective oxide film throughout side
`
`surfaces between the element formation region and the groove-type element isolation onto the
`
`semiconductor substrate.
`
`Page 5 of 193
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`

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`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
`
`
`
`[Received Date] December 19, 1995
`
`Page: 2/ 32
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`5. The semiconductor device according to claim 3, wherein
`
`
`
`both of the electrode-part sidewalls and the height difference-part sidewalls are made from a
`
`silicon film, and
`
`
`
`
`
`the semiconductor device further comprises:
`
`
`
`insulating films inserted between the electrode-part sidewalls, and, the gate electrode and
`
`the silicon substrate, respectively, and
`
`
`
`
`
`a source/drain electrode that is formed on a region from the electrode-part sidewalls up to
`
`the height difference-part sidewalls via the source/drain region of the element formation region,
`
`and that is made from silicide.
`
`
`
`6. A method for manufacturing a semiconductor device, comprising:
`
`
`
`
`
`a first step to form an oxide film on a semiconductor substrate;
`
`a second step to accumulate an etching stopper film made from a material different from the
`
`oxide film, on the oxide film;
`
`
`
`a third step to open a region where element isolation is attempted to be formed out of the
`
`etching stopper film, and to etch the semiconductor substrate in this opening part to form a
`
`groove part;
`
`
`
` a fourth step to accumulate an insulating film with thickness, which is a value where the
`
`depth of the groove part and the film thickness of the etching stopper film are added or greater,
`
`over the entire surface;
`
`
`
`a fifth step to planarize the semiconductor substrate where the insulating film has been
`
`accumulated until at least the surface of the etching stopper film is exposed, and, to form groove-
`
`type element isolation surrounding the element formation region in the groove part;
`
`
`
`a sixth step to remove at least the etching stopper film and the oxide film by etching, and to
`
`expose a height difference part where a side of the groove-type element isolation becomes higher
`
`than the semiconductor substrate in the element formation region in a step manner between the
`
`element formation region and the groove-type element isolation;
`
`
`
`a seventh step to accumulate a gate oxide film and a conductive film on the substrate, and
`
`then, to pattern at least a gate electrode from the conductive film;
`
`
`
`an eighth step to accumulate an insulating film over the entire surface of the substrate, and
`
`Page 6 of 193
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`

`

`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
`
`then to form sidewalls made from the insulating film on side surfaces of the gate electrode and
`
`[Received Date] December 19, 1995
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`Page: 3/ 32
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`the height difference part by anisotropic etching, respectively; and
`
`
`
`a ninth step to introduce impurities into the semiconductor substrate in the element formation
`
`region at both sides of the gate electrode to form a source/drain region.
`
`
`
`7. The method for the semiconductor device according to claim 6, wherein
`
`
`
`in the second step, the film thickness of the etching stopper film is regulated so as to expose
`
`the height difference part with a height difference having a predetermined or greater value in the
`
`sixth step, by taking at least the over-etching amount in the eighth step into consideration.
`
`
`
`8. A method for manufacturing a semiconductor device, comprising:
`
`
`
`
`
`
`
`a first step to form an oxide film on a semiconductor substrate;
`
`a second step to accumulate a first conductive film to be a gate electrode on the oxide film;
`
`a third step to open a region where element isolation is attempted to be formed out of the first
`
`conductive film, and to etch the semiconductor substrate in the opening part to form a groove
`
`part;
`
`
`
`a fourth step to accumulate an insulating film with thickness comprising a value where the
`
`depth of the groove part and the film thickness of the etching stopper film are added or greater,
`
`over the entire surface;
`
`
`
`a fifth step to planarize the semiconductor substrate where the insulating film has been
`
`accumulated until at least the surface of the first conductive film is exposed, and, to form groove-
`
`type element isolation surrounding the element formation region in the groove part;
`
`
`
`a sixth step to accumulate a second conductive film to be at least an upper-side gate electrode
`
`over the entire surface of the planarized substrate;
`
`
`
`a seventh step to pattern at least the gate electrode from the first and second conductive films,
`
`and, to expose the height difference part where a side of the element isolation becomes higher
`
`than the semiconductor substrate in the element formation region in a step manner between the
`
`element formation region and the groove-type element isolation;
`
`
`
`an eighth step to accumulate an insulating film over the entire surface of the substrate, and
`
`then to form sidewalls made from the insulating film over side surfaces of the gate electrode and
`
`the upper-side height difference part, respectively; and
`
`Page 7 of 193
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`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
`
`
`
`[Received Date] December 19, 1995
`
`Page: 4/ 32
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`a ninth step to introduce impurities into the semiconductor substrate in the element formation
`
`region on both sides of the gate electrode to form a source/drain region.
`
`
`
`9. The method for manufacturing the semiconductor device according to claim 8, wherein
`
`
`
`in the second step, the film thickness of the first conductive film is regulated so as to expose
`
`a height difference with a difference in level having a predetermined or greater value in the
`
`seventh step, by taking at least the over-etching amount in the eighth step into consideration.
`
`
`
`10. The method for manufacturing the semiconductor device according to claim 6 or 8, further
`
`comprising a step to silicify at least a region in the vicinity of the surface of the source/drain
`
`region after the ninth step is completed.
`
`
`
`11. The method for manufacturing the semiconductor device according to claim 6 or 8, further
`
`comprising: a step to accumulate a protective oxide film over the entire surface of the substrate
`
`after the seventh step and before the eighth step, wherein
`
`
`
`in the eighth step, a silicon nitride film for sidewall formation and a film for a mask are
`
`sequentially accumulated on the protective oxide film;
`
`
`
`a mask for patterning the silicon nitride film at the sides of the gate electrode and the height
`
`difference part is left by etching-back the film for a mask; and
`
`
`
`the mask is removed after patterning an L-shaped silicon nitride film to be sidewalls at sides
`
`of the gate electrode and the height difference part from the silicon nitride film using the mask.
`
`
`
`12. The method for manufacturing a semiconductor device according to claim 6 or 8 wherein,
`
`
`
`in the seventh step, a first protective insulating film is further accumulated over the
`
`conductive film, and the first protective insulating film is patterned along with the gate electrode;
`
`
`
`the method further comprises a step to accumulate a second protective insulating film over
`
`the entire surface of the substrate after the seventh step and before the eighth step;
`
`
`
`in the eighth step, a silicon film for sidewall formation is accumulated over the second
`
`protective insulating film, and electrode-part sidewalls and height difference-part sidewalls made
`
`from the material above are formed on side surfaces of the gate electrode and the height
`
`difference part; and
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`Page 8 of 193
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`

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`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
`
`
`
`[Received Date] December 19, 1995
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`Page: 5/ 32
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`the method further comprises a step to silicify a region across the electrode-part sidewalls,
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`the source/drain region and the height difference-parts.
`
`
`
`[DETAILED DESCRIPTION OF THE INVENTION]
`
`
`
`
`
`
`
`
`
`[0001]
`
`[Technical Field of the Invention]
`
`The present invention relates to the improvement of a structure of a semiconductor device
`
`having groove embedded isolation type of element isolation and the manufacturing method
`
`thereof.
`
`
`
`
`
`
`
`[0002]
`
`[Prior Art]
`
` Recently, demands for miniaturization have increased more in association with the progress
`
`of high integration and technical advantages of semiconductor devices. Consequently,
`
`improvement of the prior art is not enough to keep up with those demands, and there are also
`
`technical fields that are forced to introduce novel technologies. For example, as a method for
`
`forming element isolation, element isolation was conventionally formed by the LOCOS isolation
`
`method from the viewpoint of simplicity and low cost of the process of manufacture, but recently,
`
`it is believed that it is more advantageous to place the groove embedded isolation type of element
`
`isolation (hereafter, simply referred to as groove-type element isolation) in order to form a more
`miniaturized semiconductor device.
`
`
`
`
`
`
`
`[0003]
`
`In other words, since the LOCOS isolation method has adopted a selective oxidation system,
`
`a so-called bird's beak is generated at the boundary with the mask for preventing oxidation, and
`
`an insulating film in the isolation region is penetrated1 into the element region side closer than
`
`the actual mask dimensions causing a change in dimensions to occur, the variation becoming a
`
`numerical value that cannot be allowed for miniaturization of 0.5 µm generation and thereafter.
`
`Consequently, even in the field of mass-production technologies, transformation to the trench
`
`isolation method where the dimension shift is extremely small is started. For example, IBM
`
`Corporation has introduced a groove-type element isolation structure into the mass-production of
`
`MPU as a 0.5 µm CMOS process (reference: IBM Journal of Research and Development, VOL.
`
`
`1 [sic.] migrated?
`
`Page 9 of 193
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`

`

`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
`
`39, No. 1/2, 1995, pp.33-42).
`
`[Received Date] December 19, 1995
`
`Page: 6/ 32
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`
`
`
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`
`
`[0004]
`
`Fig. 6 is a cross-sectional view showing an example of a semiconductor device where
`
`conventional trench isolation and MOSFET are placed. As shown in the drawing, groove-type
`
`element isolation 105a is formed on a silicon substrate 101. Then, a gate insulating film 103a
`
`and a gate electrode 107a, and electrode-part sidewalls 108a on both side surfaces of the gate
`
`electrode 107a are placed in the active region surrounded by the element isolation 105a. Further,
`
`a low-concentration source/drain 'both e-e-'2 106a and a high-concentration source/drain region
`
`106b are placed in regions positioned on both sides of the gate electrode 107a in the active
`
`region, and a channel stop region 115 is placed under the element isolation 105a. Further, gate
`
`wiring 107b made from a polysilicon film in a manner similar to the gate electrode 107 is placed
`
`throughout on the element isolation 105a and the silicon substrate 101 that does not function as
`
`an active region via a gate insulating film 103b, and wiring-part sidewalls 108b are placed on
`
`both side surfaces. In addition, an upper-side gate electrode 109a made from silicide, an upper-
`
`side gate wiring 109b and a source/drain electrode 109c are placed on the gate electrode 107a,
`
`the gate wiring 107b and the high-concentration source/drain region 106b, respectively. The
`
`interlayer insulating film 113 is made from a silicon oxide film, metal wiring 112 formed on the
`
`interlayer insulating film 111, and contact parts 113 that are embedded into contact holes formed
`
`within the interlayer insulating film 111, respectively, and that connect the metal wiring 112 and
`
`the source/drain electrode 109c, respectively.
`
`
`
`
`
`[0005]
`
` Next, with reference to Figs. 7 (a) to (e), the manufacturing steps for a semiconductor device
`
`having the conventional groove-type element isolation shown in Fig. 6 and MOSFET are
`
`explained.
`
`
`
`
`
`
`
`[0006]
`
`First, as shown in Fig. 7 (a), the silicon oxide film 105 (not shown) is accumulated, and then
`
`the entire surface is planarized until the surface of the silicon nitride film 117 is exposed. With
`
`this step, the groove-type element isolation 105a made from a silicon oxide film embedded into
`
`
`2 [transliteration] This is most likely a typo error of '
`
`3 [sic.] '111'?
`
`' and the translation is 'region'.
`
`Page 10 of 193
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`

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`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
`
`the groove part 104 is formed in an element isolation region Reiso. Subsequently, once the silicon
`oxide film 116 is removed, a gate oxide 103 is formed over the entire surface.
`
`[Received Date] December 19, 1995
`
`Page: 7/ 32
`
`
`
`
`
`[0007]
`
` Next, as shown in Fig. 7 (c), impurity ions are implanted under the element isolation 105a,
`
`and after the channel stop region 115 is formed, a polysilicon film 107 is accumulated over the
`
`entire surface, and a photoresist film 121 where a region other than the gate formation region is
`opened is formed on the polysilicon film 107.
`
`
`
`
`
`[0008]
`
` Next, as shown in Fig. 7 (d), the polysilicon film 107 is dry-etched using the photoresist film
`
`121 as a mask, and the gate electrode 107a of MOSFET within an element formation region Refet
`
`and the gate wiring 107b from the element isolation 105a across the silicon substrate 101 are
`
`formed. Then, after the photoresist film 121 is removed, impurity ions are implanted into the
`
`silicon substrate 101 using the gate electrode 107a as a mask, and the low-concentration
`
`source/drain region 106a is formed. Subsequently a silicon oxide film 108 is accumulated over
`the entire surface of the substrate.
`
`
`
`
`
`[0009]
`
` Next, as shown in Fig. 7 (e), the silicon oxide film 108 is anisotropically dry-etched, and
`
`electrode-part sidewalls 108a and the wiring-part sidewalls 108b are formed on both side
`
`surfaces of the gate electrode 107a and the gate wiring 107b, respectively. Then, the gate oxide
`
`film 103 under the silicon oxide film 108 is also removed at the same time, and only the gate
`
`oxide film 103a under the gate electrode 107a and the gate oxide film 103b under the gate wiring
`
`107b remain. Subsequently impurity ions are implanted from an oblique direction using the gate
`
`electrode 107a and the electrode-part sidewalls 108a as masks, and the high-concentration
`
`source/drain region 106b is formed. Then, after a Ti film is accumulated over the entire surface,
`
`high-temperature heat treatment is conducted, and the upper-side gate electrode 109a made from
`
`silicide, the upper-side gate wiring 109b and the source/drain electrode 109c are formed by
`reacting the Ti film with a member made from silicon that makes direct contact with the Ti film.
`
`
`
`
`
`[0010]
`
`Page 11 of 193
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`

`

`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
`
` Steps thereafter are omitted, and the final structure of MOSFET is shown in Fig. 5. In Fig. 54,
`
`[Received Date] December 19, 1995
`
`Page: 8/ 32
`
`the metal wiring 112 is formed on the interlayer insulating film 111, and the contact parts 113
`
`made from a W plug or the like where the contact holes are embedded connect the metal wirings
`112 to the source/drain electrodes 109c.
`
`
`
`
`
`
`
`[0011]
`
`In the case of adopting the groove-type element isolation structure as mentioned above, since
`
`there is no bird's beak as in the LOCOS method to form a thick silicon oxide film by thermal
`
`oxidation, i.e. no implantation of an oxide film into an active region, a dimensional shift in the
`
`source/drain region is suppressed. Then, in the step shown in Fig. 7 (c), the element isolation
`105a and the silicon substrate 101 in the element formation region Refet are planarized.
`
`
`
`
`
`
`
`[0012]
`
`[Problem to be Solved by the Invention]
`
` However, in the semiconductor device having the element isolation with the trench structure
`
`above there are the following problems.
`
`
`
`
`
`
`
`[0013]
`
`In other words, when transitioning from the state shown in Fig. 7 (d) to that shown in Fig. 7
`
`(e), the silicon oxide film 108 is anisotropically etched to form the sidewalls 108a and 108b, but
`
`over-etching needs to be conducted then. This over-etching causes carving out of the surface of
`the element isolation 105a downward to some degree.
`
`
`
`
`
`[0014]
`
`
`Figs. 8 (a) and (b) are cross-sectional views showing the enlarged vicinity of a boundary
`between the high-concentration source/drain region 106b and the element isolation 105a.
`
`
`
`
`
`[0015]
`
` As shown in Fig. 8 (a), the step to implant impurity ions from an oblique direction, and to
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`form the high-concentration source/drain region 106b is conducted between the step shown in
`
`Fig. 7 (d) and the step shown in Fig. 7 (e), but since the element isolation 105a is engraved to the
`
`lower side, on this occasion of ion implantation, the high-concentration source/drain region 106b
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`is formed even to the lower side of the end portion of the element isolation 105a. Therefore, a
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`proximity of the high-concentration source/drain region 106b with the channel stop region 115
`
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`4 [sic.] Symbols 111, 112, 113, etc. are not mentioned in Fig. 5. This may be 'Fig. 6'?
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`Page 12 of 193
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`

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`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
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`occurs, and it causes a defect, such as deterioration of junction withstand voltage or an increase
`in junction leak.
`
`[Received Date] December 19, 1995
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`Page: 9/ 32
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`
`
`
`
`
`
`[0016]
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`Further, as shown in Fig. 8 (b), with this method of sicification where a Ti film or the like is
`
`accumulated on the high-concentration source/drain region 106b and it is reacted with silicon
`
`below, a silicide layer easily erodes an interface between the silicon substrate 101 and the
`
`element isolation 105a, and it may cause occurrence of a short-circuit current between the
`source/drain electrode 109c made from silicide and the channel stop region 115.
`
`
`
`
`
`
`
`[0017]
`
`The present invention has been accomplished in light of such points, and the objective is to
`
`provide a minute high-performance semiconductor device without any deterioration of junction
`
`leak or junction withstand voltage while having the groove-type element isolation structure by
`
`providing a means to prevent engraving of the groove-type element isolation region by over-
`
`etching on the occasion of the sidewall formation as mentioned above, and to provide a
`manufacturing method thereof.
`
`
`
`
`
`
`
`
`
`[0018]
`
`[Means for Solving the Problem]
`
`In order to accomplish said objective, the resolution means by the present invention is to
`
`form a height difference part where a side of a groove-type element isolation becomes higher
`
`between a semiconductor substrate in an element formation region and the groove-type element
`
`isolation, and to place sidewalls in this height difference part. Specifically, the semiconductor
`
`devices according to claims 1 to 5 and the means regarding the method for manufacturing a
`semiconductor device according to claims 6 to 12 are provided.
`
`
`
`
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`
`
`
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`
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`[0019]
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`The semiconductor device of the present invention, as mentioned in claim 1, is equipped with
`
`a semiconductor substrate,
`
`an element formation region placed in a portion of the substrate,
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`groove-type element isolation that surrounds the element formation region, and that
`
`comprises a height difference part, which becomes higher in a step manner than the
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`semiconductor substrate of the element formation region, with the element formation region, and
`
`that is made from an insulating material, and
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`Page 13 of 193
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`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
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`
`
`[Received Date] December 19, 1995
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`Page: 10/ 32
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`height difference-part sidewalls formed on side surfaces of the height difference part between
`
`the element formation region and the groove-type element isolation.
`
`
`
`
`
`[0020]
`
` Because of such a configuration, since the height difference part where the surface of the
`
`groove type element isolation is higher than the surface of the semiconductor substrate in the
`
`element formation region is placed at the end portion of the groove-type element isolation,
`
`implantation of impurity ions into the lower side at the end portion of the element isolation is
`
`inhibited on the occasion of implantation of impurity ions when an impurity diffused layer in the
`
`semiconductor device is formed. Further, even in the case of adopting the structure where the
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`source/drain electrode made from silicide is placed, since the penetration5 of the silicide layer
`
`into the back side is inhibited by the step-side sidewalls, occurrence of a short-circuit current
`
`between the source/drain electrode and the substrate region, such as the channel stop region, can
`
`be prevented. Therefore, reduction in an isolation function among semiconductor devices in the
`
`groove-type element isolation is prevented.
`
`
`
`
`
`[0021]
`
` As described in claim 2, in claim 1, the height difference-part sidewalls can be formed with
`an insulating material.
`
`
`
`
`
`[0022]
`
` As described in claim 3, in claim 1, MISFET having a gate electrode and the electrode-part
`
`sidewalls on both side surfaces of the gate electrode is formed in the element formation region,
`
`and at least a portion of the height difference-part sidewalls can be formed at the same time with
`
`the electrode-part sidewalls.
`
`
`
`
`
`[0023]
`
` As described in claim 4, in claim 3, the electrode-part sidewalls can be formed with an L-
`
`shaped silicon nitride film with substantially constant thickness that is formed via a protective
`
`oxide film throughout side surfaces of the gate electrode onto the semiconductor substrate; and
`
`
`
`the height difference-part sidewalls can be formed with an L-shaped silicon nitride film with
`
`substantially constant thickness that are formed via a protective oxide film throughout side
`
`surfaces between the element formation region and the groove-type element isolation onto the
`
`semiconductor substrate.
`
`
`5 [sic.] migration?
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`Page 14 of 193
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`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
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`
`
`[0024]
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`
`
`[Received Date] December 19, 1995
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`Page: 11/ 32
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` Because of such a configuration, reduction in an isolation function among the semiconductor
`
`devices in the groove-type element isolation can be prevented by the L-shaped silicon nitride
`
`film placed in the height difference part. In addition, since the structure where the film thickness
`
`of the groove-type element isolation is not reduced even by over-etching when forming sidewalls
`
`is realized, it is possible to reduce the value for the height difference. Therefore, since the
`
`semiconductor substrate and the groove-type element isolation on the active region on the
`
`occasion of patterning the gate electrode are closer to a flat state, the accuracy of the finished
`dimensions of the gate is improved.
`
`
`
`
`
`[0025]
`
` As described in claim 5, in claim 3, both of the electrode-part sidewalls and the height
`
`difference-part sidewalls can be made from a silicon film, and
`
`
`
`
`
`the semiconductor device can be further equipped with
`
`
`
`insulating films inserted between the electrode-part sidewalls, and, the gate electrode and
`
`the silicon substrate, respectively, and
`
`
`
`
`
`a source/drain electrode that is formed on a region from the electrode-part sidewalls up to
`
`the height difference-part sidewalls via the source/drain region of the element formation region,
`
`and that is made from silicide.
`
`
`
`
`
`[0026]
`
` Because of such a configuration, the function of inhibiting implantation of impurity ions by
`
`the height difference-parts and another function to inhibit penetration6 of the silicide layer
`
`backward in the silicification step are obtained. In addition, since a source/drain electrode made
`
`from a silicide layer is placed on a wide region throughout the electrode-part sidewalls, the
`
`source/drain region and the height difference-part sidewalls, it becomes easy and certain to form
`
`a contact from the wiring of the upper layer, improving reliability, and making it possible to
`reduce the area of the element formation region.
`
`
`
`
`
`[0027]
`
` A first method for a semiconductor device relating to the present invention, as described in
`
`claim 6, includes:
`
`
`
`a first step to form an oxide film on a semiconductor substrate;
`
`
`6 [sic.] migration?
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`Page 15 of 193
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`[Document Name] Specification
`[Patent] H7-330112 (December 19, 1995)
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`
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`[Received Date] December 19, 1995
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`Page: 12/ 32
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`a second step to accumulate an etching stopper film made from a material, which is different
`
`from the oxide film, on the oxide film;
`
`
`
`a third step to open a region where element isolation is attempted to be formed out of the
`
`etching stopper film, and to etch the semiconductor substrate in this opening part to form a
`
`groove part;
`
`
`
` a fourth step to accumulate an insulating film with thickness, which is a value where the
`
`depth of the groove part and the film thickness of the etching stopper film are added or greater,
`
`over the entire surface;
`
`
`
`a fifth step to planarize the semiconductor substrate where the insulating film has been
`
`accumulated until at least the surface of the etching stopper film is exposed, and, to form groove-
`
`type element isolation surrounding the element formation region in the groove part;
`
`
`
`a sixth step to remove at least the etching stopper film and the oxide film by etching, and to
`
`expose a height difference part where a side of the groove-type element isolation becomes higher
`
`than the semiconductor substrate in the element formation region in a step manner between the
`
`element formation region and the groove-type element isolation;
`
`
`
`a seventh step to accumulate a gate oxide film and a conductive film on the substrate, and
`
`then, to pattern at least a gate electrode from the conductive film;
`
`
`
`an eighth step to accumulate an insulating film over the entire surface of the substrate, and
`
`then to form sidewalls made from the insulating film on side surfaces of the gate electrode and
`
`the height difference part by anisotropic etching, respectively; and
`
`
`
`a ninth step to introduce impurities into the semiconductor substrate in the element formation
`
`region at both sides of the gate electrode to form a source/drain region.
`
`
`
`
`
`[0028]
`
` According to this method, since the height difference part is formed between the
`
`semiconductor substrate in the element formation region in the groove-type element isolation in
`
`the stage when the sixth step is finished, implan