`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Global Foundaries US v. Godo Kaisha
`Global Ex. 1017
`
`Page 1 of 20
`
`

`

`
`U.S. Patent
`
`
`
`June 4, 1991
`
`
`
`
`
`Sheet 1 of 13
`
`
`
`
`
`5,021,353
`
`
`
`IG.
`
`
`
`
`
`| F
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 2 of 20
`
`
`
`Page 2 of 20
`
`

`

`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`|fa
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 3 of 20
`
`
`

`

`
`U.S. Patent
`
`
`
`
`
`June 4, 1991
`
`
`
`
`
`
`Sheet 3 of 13
`
`
`
`5,021,353
`
`
`
`Leapf
`tt
`tt
`ptt|
`tt
`
`CT|
`48
`
`ttoeaHHPreoaYtfe
`
`
`
`W////,.ZASHWildSa
`
`
`
`
`
`
`
`
`Page 4 of 20
`
`Page 4 of 20
`
`
`
`

`

`
`U.S. Patent
`
`
`
`
`
`June 4, 1991
`
`
`
`
`
`
`Sheet 4 of 13
`
`
`
`5,021,353
`
`
`
`;ZEISS
`
`cl
`
`yOla
`
`
`
`
`
`
`cvle
`
`
`CTTTyeeeyyry
`pT|Peeret
`Pyeer
`
`PP
`
`“attity
`
`Ptyerry
`PyyeeeeTTyd
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 5 of 20
`
`Page 5 of 20
`
`
`
`

`

`
`U.S. Patent
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5,021,353
`
`
`
`StaylikSS
`rit)f/fi(i‘<‘iI)EeeeeeeseeDetA7ALI\CTEtTrZ”\£~™EEEEo
`
`
`ROOSTTELEttaPerret
`
`GOlas
`
`Page 6 of 20
`
`
`

`

`
`U.S. Patent
`
`
`
`
`
`June 4, 1991
`
`
`
`
`
`
`
`
`
`
`
`5,021,353
`
`
`
`20ES6o2%6UKS<KDKLR
`Lilia
`TDA
`
`LORELLELASOQYHNENACEITIPARR
`
`
`
`=|
`
`1S
`
`
`
`9lA
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`IEwOcS
`
`1Sleuozseb
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 7 of 20
`
`

`

`
`U.S. Patent
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5,021,353
`
`
`
`
`
`
`
`
`LO
`
`es(FAS
`ier
`
`oweinghaenenaanphereenqan
`
`IsTEYOcS*:
`
`cy79nc=
`
`ZI
`
`LOs
`
`Page 8 of 20
`
`

`

`
`U.S. Patent
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`3,021,353
`
`
`
`ei
`
`LS
`
`YY
`
`8Ol
`
`
`
`
`
`
`
`
`18onetnrn
`,TeeeLSEKY
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 9 of 20
`
`

`

`=,021,353
`
`
`
`bOla
`
`
`U.S. Patent
`
`
`
`
`
`
`
`
`
`eet 90f13
`
`
`
`
`
`
`
`
`
`w4ZZOaOYgmNEEaq:RX
`
`
`
`COOSCOOTCRRASCPPeeyNoesLy
`Ceryeoo
`CaySy
`
`(mani
`
`tTTTATy
`
`pr
`
`SCCPRETY
`
`€6
`
`SLIT
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 10 of 20
`
`

`

`
`U.S. Patent
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5,021,353
`
`
`
`\
`
`(RRRLIOR
`NSSKKEESSPRNNS
`
`LLLLLGFIZZ,—ANs:x7,
`
`SS
`
`Ot
`
`
`
`OlOsa
`
`
`
`
`Page 11 of 20
`
`
`
`
`
`

`

`
`U.S. Patent
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5,021,353
`
`
`
`PSGKili4]HWY\\\s:
`NBNAteeiBRVC
`
`balLatadhadhaa
`|AWNoyZI
`1S€6€6
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`llOla
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`C6WITE
`
`Page 12 of 20
`
`

`

`
`
`
`
`
`
`June 4, 1991
`
`
`
`
`
`
`Sheet 12 of 13
`
`
`
`5,021,353
`
`
`
`
`
`
`
`
`
`
`121
`
`
`
`
`
`
`
`
`ccl
`
`Tcl
`
`
`
`
`€6
`
`c&6
`
`( €6
`
`lel
`
`
`
`Page 13 of 20
`
`|ZI
`ZIJT
`hoheC7,=COI
`9S\cel
`aa
`(4jcNN—a
`eee,
`SLASSLTER
`“LS”1é
`SWXPO
`clOld
`sayyDAROSRWM
`aCywrepag
`CORDS|
`
`
`
`
`
`
`
`
`4
`
`“CCl
`
`Page 13 of 20
`
`

`

`
`U.S. Patent
`
`
`
`June 4, 1991
`
`
`
`
`
`Sheet 13 of 13
`
`
`
`
`
`
`5,021,353
`
`
`
`LeilaSOXXOXxIUVOCOCOCNDKKKRRAYASXPNLOO
`
`
`laliecependleee
`LLZkPSjrm(LoLPONSORRY,SOE
`
`
`;PRRIY“«KORAXS\\I)ANBRANSSSSNSSSS
`
`SESS
`
`LYLB
`
`oe,
`
`ClOld|
`
`Page 14 of 20
`
`Page 14 of 20
`
`
`

`

`1
`
`
`
`5,021,353
`
`
`
`
`
`
`
`SPLIT-POLYSILICON CMOS PROCESS
`
`
`INCORPORATING SELF-ALIGNED
`
`
`SILICIDATION OF CONDUCTIVE REGIONS
`
`
`
`
`
`2
`
`
`
`
`
`
`
`
`arsenic or phosphorus to create the N-wells. The N-
`
`
`
`
`
`
`
`
`well regions are then oxidized using a first conventional
`
`
`
`
`
`
`
`
`
`
`LOCOS (LOCal Oxidation of Silicon) step to create a
`
`
`
`
`
`
`
`
`
`silicon oxide layer to protect them from an optional
`
`
`
`
`
`
`
`
`boron implant which adjusts the concentration of the
`FIELD OF THE INVENTION
`
`
`
`
`
`
`
`
`
`
`
`P-type substrate for the N-channel devices. During the
`
`
`
`
`
`
`
`
`
`
`LOCOSprocess, the pad oxide servesasa stress relief
`
`
`
`This invention describes a process sequence for the
`
`
`
`
`
`
`
`
`
`
`
`layer. Alternatively, an oxide deposition or oxide
`
`
`
`
`
`fabrication of Complimentary Metal Oxide Semicon-
`
`
`
`
`
`
`
`
`growth step could replace the first LOCOSstep,elimi-
`
`
`
`
`
`ductor (hereinafter “CMOS”)integrated circuits. More
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`nating the need for thefirst pad oxide layer and thefirst
`
`
`
`
`
`specifically, it relates to the fabrication of LDD transis-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`nitride layer. A subsequent high-temperature drive step
`tors of both channel types, using self-alignedsilicidation
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ofgates and source/drain regions to reduce the number
`is used to achieve the desired N-well junction depth.
`
`
`
`
`
`
`
`
`
`
`of photomasking steps required in a split-polysilicon
`
`
`
`
`
`Following removalofthe oxide layer, a second layer of
`
`
`
`
`
`
`
`
`
`
`process.
`.
`
`pad oxide is grown over the entire wafer. A second
`
`
`
`
`
`
`
`
`
`
`
`silicon nitride layer is then deposited on top of the pad
`BACKGROUND OF THE INVENTION
`
`
`
`
`
`
`oxide layer.
`Although CMOSintegrated circuit devices are often
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The second photomask is used to pattern portions of
`referred to as “semiconductor” devices, such devices
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the secondsilicon nitride layer which define the future
`are fabricated from various materials which are either
`
`
`
`
`
`
`
`
`
`
`
`
`active areas on the wafer.
`electrically conductive, electrically nonconductive or
`
`
`
`
`
`
`
`
`
`
`
`
`
`The third photomask is used to cover the N-well
`electrically semiconductive. Silicon,
`the most com-
`
`
`
`
`
`
`
`
`
`
`
`
`
`regions in order to effect a selective boron field-isola-
`monly used semiconductor material can be made con-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`tion implant. Following the stripping of the third photo-
`
`
`
`
`
`
`
`
`
`ductive by doping it (introducing an impurity into the
`mask, the regions on the wafer that are not protected by
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`silicon crystal structure) with either an element such as
`the remaining portions of the secondsilicon nitride
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`boron which has oneless valence electron thansilicon,
`layer are oxidized to form field oxide regions using a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`or with an element such as phosphorusor arsenic which
`second conventional LOCOSstep. The nitride layeris
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`have one morevalenceelectron thansilicon. In the case
`then stripped,as is the pad oxide layer. A layer ofsacri-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`of boron doping, electron “holes” become the charge
`ficial oxide is then grown to eliminate the “white rib-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`carriers and the dopedsilicon is referred to as positive
`bon”or Kooieffect in the active areas that follows field
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`or P-type silicon. In the case of phosphorusor arsenic
`oxidation. An unmasked implant may be used as a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`doping,
`the additional electrons become the charge
`
`threshold voltage (V7) adjustment.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`carriers and the dopedsilicon is referred to as negative
`
`
`
`
`
`
`
`The fourth photomask exposes only the channel re-
`
`
`
`
`
`
`
`
`or N-typesilicon. If dopants of opposite type conduc-
`
`
`
`
`
`
`
`
`gions of the N-channel
`transistors to a high-energy
`
`
`
`
`
`
`
`
`
`tivity are used, counter doping will result, and the con-
`
`
`
`
`
`
`
`
`
`
`boron punch-through implant. This implant increases
`
`
`
`
`ductivity type of the most abundant impurity will pre-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`both source-to-drain breakdownvoltage and the thresh-
`vail. Silicon is used either in single-crystal or polycrys-
`
`
`
`
`
`
`
`
`
`
`
`
`
`old voltage,
`thus avoiding the short-channel effects
`talline form. Polycrystalline silicon is referred to herein-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`after as “polysilicon” or simply as ‘poly’. Originally,
`which are inherent to nonimplanted, sub-micron N-
`
`
`
`
`
`
`
`
`
`
`
`
`MOSdevices were manufactured from metal (used as
`
`
`channel devices. Following the punch-through implant,
`
`
`
`
`
`
`
`
`
`the transistor gate), semiconductor material (used as the
`
`
`
`
`
`
`
`
`the fourth photomask is stripped, as is the sacrificial
`
`
`
`
`
`
`
`transistor channel material), and oxide (used as the di-
`
`
`
`
`
`
`
`
`
`
`
`
`
`oxide layer. A layer of gate oxide is then grown onall
`electric between the gate and the substrate. Currently,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`active areas, following which a polysilicon layer is de-
`
`however, most MOStransistors are fabricated using a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`posited on top of the gate oxide using conventional
`conductively-doped polycrystalline silicon layer for the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`means(e.g., chemical vapor deposition). The poly layer
`gate material.
`
`
`
`
`
`
`
`
`
`
`
`
`is then doped with phosphorus, coated with a layer of
`CMOSprocesses begin with a lightly-doped P-type
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`tungsten silicide by various possible techniques(e.g.,
`or N-type silicon substrate, or lightly-doped epitaxial
`
`
`
`
`
`
`
`
`
`
`
`
`
`chemical vapor deposition, sputtering, or evaporation).
`silicon on a heavily doped substrate. For the sake of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The fifth photomask patterns the silicide-coated
`simplicity,
`the prior art CMOS process will be de-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`polysilicon layer to form the gates of both P-channel
`scribed using P-type silicon as the starting material. If
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`and N-channeltransistors. Stripping of the fifth photo-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`N-type silicon were used, the process steps would be
`
`
`
`
`
`
`
`
`
`
`
`
`
`maskis followed by a source/drain oxidation.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`virtually identical, with the exception that
`in some
`The sixth photomask is used to expose only the N-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`cases, dopant types would be reversed. Fabrication of
`channel source and drain regions to a relatively low-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`sub-micron CMOSdevices havingasilicided single
`dosage phosphorusimplant whichcreateslightly-doped
`55
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`poly layer and a single metal layer using prior art tech-
`N- regions. Following the stripping of the sixth mask, a
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`nology generally requires at least 11 photoresist masks
`layer of silicon dioxide is deposited on the wafer. An
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(or simply “photomasks”) to create N-channel and P-
`anisotropic etch and a subsequent optional isotropic
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`channeltransistors on a silicon substrate (an additional
`
`etch of thesilicon dioxide layer leave oxide spacers on
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`one or two masks. is required if lightly-doped drain
`the sides of each N-channel and P-channeltransistor
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`design is required for both types of transistors). No
`gate.
`
`
`
`
`
`
`
`
`
`
`
`attemptis madeatsiliciding source and drain regionsin
`the N-channel
`The seventh photomask exposes
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`this process. The function of these 11 masks is described
`
`
`
`
`
`
`
`
`source and drain regions to a relatively high-dosage
`
`below.
`
`
`
`phosphorusorarsenic implant which creates the heavi-
`
`
`
`
`
`
`
`
`
`
`
`
`
`Thefirst photoresist mask is used to define N-wells.
`ly-doped N-+tregions. Following the stripping of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`This is done by creating a first layer of pad oxide on a
`
`
`
`
`
`
`
`
`
`
`
`
`
`seventh mask, the wafer is optionally subjected to ele-
`
`
`lightly-doped P-type substrate, depositing a layer of
`
`
`
`
`
`
`
`
`
`
`
`
`
`vated temperature for the purpose of diffusing the N-
`
`
`
`
`
`
`nitride on top ofthe pad oxide, masking thenitride layer
`
`
`
`
`
`
`
`
`
`
`
`to expose certain regions which are then implanted with
`channel implants.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`_ 0
`
`
`15
`
`
`
`
`
`
`
`
`
`
`
`40
`
`
`
`45
`
`
`
`
`
`
`65
`
`
`
`
`Page 15 of 20
`
`Page 15 of 20
`
`

`

`5,021,353
`
`
`3
`
`
`
`
`
`
`
`
`The eighth photomask is used for the high-dosage
`
`
`
`
`
`
`
`
`implantation of either boron or boron difluoride, which -
`
`
`
`
`
`
`
`
`
`creates heavily doped source and drain regions for the
`
`
`
`
`
`
`
`P-channel transistors. Following the stripping of the
`
`
`
`
`
`
`
`eighth mask, an elevated-temperature drive step is per-
`
`
`
`
`
`
`
`
`
`formed, after which the transistors are fully formed. All
`
`
`
`
`
`
`
`
`
`structures are then covered by anisolation oxide layer.
`
`
`
`
`
`
`
`
`
`The ninth photomask is used to define contact vias
`
`
`
`
`
`
`
`
`
`
`which will pass through the isolation oxide layer to the
`
`
`
`
`
`
`
`poly structures or active area conductive regions be-
`
`
`
`
`
`
`
`
`
`low. A deposition of an aluminum metal layer follows.
`
`
`
`
`
`
`
`
`
`The tenth photomaskis used to pattern the aluminum
`
`
`
`
`
`
`
`layer for circuit interconnects. Using a blanket deposi-
`
`
`
`
`
`
`
`tion process, the circuitry is covered with one or more
`
`
`
`
`
`passivation layers.
`
`
`
`
`
`
`The eleventh photomask defines bonding pad open-
`
`
`
`
`
`
`
`
`
`ings which will expose bonding pad regions on the
`
`
`
`
`
`
`
`aluminum layer below. This completes the conventional
`
`
`
`
`single-poly, single-metal CMOSprocess.
`
`
`
`
`
`
`The business of producing CMOS semiconductor
`
`
`
`
`
`
`
`devices is a very competitive, high-volume business.
`
`
`
`
`
`
`
`Process efficiency and manufacturability, as well as
`
`
`
`
`
`
`
`
`productquality, reliability, and performanceare the key
`factors that will determine the economic success or
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`failure of such a venture. Each new generation of
`
`
`
`
`
`
`
`
`
`CMOSdevices is expected to be faster and more com-
`
`
`
`
`
`
`
`
`pact than the generation it replaces. Four-fold density
`
`
`
`
`
`
`
`
`
`increases from one generation to the next have become
`
`
`
`
`
`
`
`
`
`standard. If this increase in density is achieved with no
`
`
`
`
`
`
`
`
`
`
`
`increase in die size, device geometries must be more or
`
`
`
`
`
`
`less halved. As geometries shrink, each photolitho-
`
`
`
`
`
`
`
`
`graphic step becomes more costly. The increase and
`
`
`
`
`
`
`
`
`
`cost maybeattributed to a numberoffactors, including:
`
`
`
`
`
`
`higher capital costs for precision “state-of-the-art”
`
`
`photolithographic equipment;
`
`
`
`
`
`
`
`lowered yields and decreasedreliability due to defect
`
`
`
`
`
`
`density increases invariably associated with each photo-
`
`
`masking step;
`
`
`
`
`
`
`
`
`
`
`an increase in the numberof processing steps for each
`
`
`
`
`
`
`
`
`mask level, which slows the fabrication process and
`
`
`
`
`requires additional expensive equipment;
`
`
`
`
`
`
`the requirement for ultra-clean fabrication facilities
`
`
`
`
`
`
`
`
`
`which are both expensive to construct and expensive to
`
`operate;
`
`
`
`
`
`
`greater investment per wafer during fabrication,
`
`
`
`
`
`
`
`
`whichincreases the cost of scrapping defective devices;
`and
`
`
`
`
`
`
`
`
`costs associated with the step required subsequent to
`
`
`
`
`
`
`
`
`
`
`
`the masking step, whether it be an implant or an etch.
`
`
`
`
`
`
`
`From the aforementioned discussion,it is evident that
`
`
`
`
`
`
`
`
`the elimination of photomasking steps from a CMOS
`
`
`
`
`
`
`
`
`
`process will have a direct impact on the cost,reliability,
`
`
`
`
`
`and manufacturability of the product.
`
`
`
`
`
`
`
`
`
`A novel process is disclosed in the 1982 Japanese
`
`
`
`
`
`
`
`
`patent issued to Masahide Ogawa (No. 57-17164) for
`
`
`
`
`
`
`
`fabricating a CMOSintegrated circuit by processing
`
`
`
`
`
`
`
`N-channel and P-channel devices separately. As with
`
`
`
`
`
`
`
`the conventional CMOSprocess, .a single polysilicon
`
`
`
`
`
`
`
`
`
`layer is used to form both N-channel and P-channel
`
`
`
`
`
`
`
`gates. However, N-channel devices are formedfirst,
`
`
`
`
`
`
`
`
`with unetched polysilicon left in the future P-channel
`
`
`
`
`
`
`regions until N-channel processing is complete. The
`
`
`
`
`
`
`
`
`mask used to subsequently pattern the P-channel de-
`
`
`
`
`vices is also used to blanket and protect the already-
`
`
`
`
`
`
`formed N-channel devices. This process is herein re-
`
`
`
`
`
`
`
`
`
`
`ferred to as the split-polysilicon CMOS process. The
`
`
`
`
`
`
`
`spilt-polysilicon CMOS process,
`through largely ig-
`
`
`
`
`
`
`
`
`
`nored by semiconductor manufacturers in the U.S. and
`
`5
`
`
`
`
`
`
`
`15
`
`
`20
`
`
`25
`
`
`
`
`35
`
`
`
`
`40
`
`
`45
`
`
`
`
`50
`
`
`55
`
`
`
`
`65
`
`
`
`
`
`
`
`
`
`
`
`4
`
`
`
`
`
`
`abroad, holds tremendouspotential for reducing photo-
`
`
`
`
`
`
`masking steps in a CMOS process.
`
`
`
`
`
`
`
`
`A pending U.S. Pat. No. 7/427,639, submitted by
`
`
`
`
`
`
`
`
`
`Tyler A. Lowrey, Randal W. Chance, and Ward D.
`
`
`
`
`
`
`
`
`Parkinson of Micron Technology, Inc. of Boise, Id.
`
`
`
`
`details an improved split-polysilicon CMOS process.
`
`
`
`
`
`
`
`
`
`
`The improved CMOSfabrication process is based on
`
`
`
`
`the aforementioned split-polysilicon CMOS process
`
`
`
`
`
`
`
`
`developed in Japan by Mashahide Ogawa. The im-
`
`
`
`
`
`
`proved process utilizes an unmasked N-channel punch-
`
`
`
`
`
`through implant and unmasked N-channel source/drain
`
`
`
`
`
`
`
`
`implants that are self-aligned to gate electrodes to cre-
`
`
`
`
`
`ate high-performance LDD-type N-channeltransistors.
`
`
`
`
`
`These high-performance transistors have both punch-
`
`
`
`
`
`
`through regions and LDD-type source/drain regions.
`
`
`
`
`
`
`
`By utilizing the split-polysilicon CMOSprocessin com-
`
`
`
`
`
`
`
`
`bination with the unmasked implants, the number of
`
`
`
`
`
`
`
`masks required to form both N-channel and P-channel
`
`
`
`
`
`
`
`
`
`
`devices can be reduced from eleven (for the standard
`
`
`
`
`
`
`
`
`CMOSprocess) to eight (for the improved process).
`
`
`
`
`
`
`
`P-channel source and drain regions, although of con-
`
`
`
`
`
`
`
`
`
`ventional non-LDDdesign,are offset from the edges of
`
`
`
`
`
`
`
`
`the P-channel gates by undercutting the gates beneath
`
`
`
`
`
`
`
`the photoresist during the gate-patterning etch. The
`
`
`
`
`
`
`
`
`gate-patterning photoresist is then used as an offsetting
`
`
`implant mask.
`SUMMARYOF THE INVENTION
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The object of the present invention is to reduce the
`
`
`
`
`
`
`
`cost and improve the reliability, performance and
`
`
`manufacturability of CMOSdevices by implementing a
`
`
`
`
`
`
`
`
`
`
`variation of the improvedsplit-polysilicon CMOSfabri-
`
`
`
`
`
`
`
`cation process developed by Mssrs. Lowrey, Chance
`
`
`
`
`
`
`
`
`and Parkinson which provides LDd sources and drains
`for both N-channel and P-channeltransistors with no
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`increase in the number of photomaskingsteps, and in-
`
`
`
`
`
`
`corporatesself-aligned silicidation of transistor gates,
`
`
`
`
`
`
`
`sources and drains. Like the original Micron-developed
`
`
`
`
`
`
`improved split-polysilicon CMOS process,
`the new
`
`
`
`
`
`
`
`
`split-polysilicon silicide process, which is the focus of
`
`
`
`
`
`
`
`
`the present invention, also utilizes eight masks to fabri-
`
`
`
`
`
`
`
`
`
`
`cate both types of transistors. The function of each of
`
`
`
`
`
`
`
`
`the eight required photomasks is described below. For
`
`
`
`
`
`the sake of simplicity,
`the process will be described
`
`
`
`
`
`
`
`
`
`
`
`
`using P-type silicon as the starting material. If N-type
`
`
`
`
`
`
`
`
`
`silicon were used, theprocess steps would bevirtually
`
`
`
`
`
`
`
`
`
`
`identical, with the exception that dopant types would be
`reversed in somecases.
`
`
`
`
`
`
`The first photomask is used to form the N-well re-
`
`
`
`
`
`
`
`
`
`
`
`
`gions in a conventional manner.
`
`
`
`
`
`
`The second photomask is used to conventionally
`
`
`
`
`
`
`
`
`
`define the active areas by patterning a nitride layer.
`
`
`
`
`
`
`
`
`
`The third photomask is used to cover the N-well
`
`
`
`
`
`
`
`
`
`regions in order to effect the boronfield isolation im-
`
`
`
`
`
`plant, also in accordance with conventional CMOS
`
`
`
`
`‘technology. Following the stripping of the third mask,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`LOCOSis used to growthefield oxide regions, and an
`
`
`
`
`
`unmasked boron implantis used as a transistor threshold
`
`
`
`
`
`
`enhancement. The use of a masked punch-through im-
`
`
`
`
`
`
`
`
`
`
`
`
`
`plantat this pointis not required. Following the deposi-
`tion and doping with phosphorusofa polysilicon layer,
`
`
`
`
`
`
`
`
`
`
`
`
`the process further deviates from convention.
`
`
`
`
`
`
`
`
`
`
`
`The fourth photomaskis used to pattern the gates of
`
`the N-channel transistors and to cover the P-channel
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`regions. An anisotropic dry etch is used to form the
`
`
`
`
`
`
`N-channeltransistor gates, following which the fourth -
`
`
`
`
`mask photoresist is stripped. Following an unmasked
`
`
`
`
`
`
`
`
`
`self-aligned boron punch-through implant, a source/-
`
`Page16 of 20
`
`Page 16 of 20
`
`

`

`5,021,353
`
`
`5
`
`
`
`
`
`
`
`drain oxidation is performed. A low-dosage unmasked
`
`
`
`
`
`
`phosphorus implant then creates the lightly-doped N-
`
`
`
`
`
`
`
`
`regions of the N-channel sources and drains. Spacer
`
`
`
`
`
`
`
`
`
`oxide deposition is followed by an anisotropic dry etch
`
`
`
`
`
`
`
`
`
`and an optional isotropic etch (in that order), which
`
`
`
`
`
`
`
`
`
`leave spacers on both sides of the N-channel gates.
`
`
`
`
`
`
`
`Spacer formation is followed by a high-dosage un-
`
`
`
`
`
`
`
`masked phosphorus orarsenic implant, which creates
`
`
`
`
`
`
`
`the heavily-doped N+ regions of the N-channel
`
`
`
`
`
`
`
`
`
`
`sources and drains. Doping of the poly layer in the
`
`
`
`
`
`
`P-channel regions with the aforementioned N-channel
`
`
`
`
`
`
`
`
`implants will have essentially no effect on P-channel
`
`
`
`
`
`
`
`
`transistor performance, since only the gate is doped,
`
`
`
`
`
`
`
`
`with the future source and drain regions remaining
`
`
`
`
`
`
`
`
`
`untouched. Since the gate poly is doped n-type anyway,
`
`
`
`
`
`
`
`
`there is no electrical impact on P-channel transistors.
`
`
`
`
`
`
`
`
`
`
`
`Thefifth photomaskis used to pattern the gates of the
`P-channel transistors and to cover the N-channel! re-
`
`
`
`
`
`
`
`
`:
`gions.
`
`
`
`
`
`
`
`
`
`An anisotropic etch is used to etch the P-channel
`
`
`
`
`
`
`
`transistor gates. A low-dosage boron implant may then
`
`
`
`
`
`
`
`
`
`
`be optionally performed in the regions not protected by
`
`
`
`
`
`
`
`the fifth photomask,thus creating lightly-doped sources
`and drains for the P-channel devices. Removal of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`fifth photomaskis followed by the blanket deposition of
`
`
`
`
`
`
`
`
`‘a spacer oxide layer, which is anisotropically etched
`
`
`
`
`
`
`(and optionally subsequently isotropically etched) to
`
`
`
`
`
`
`
`
`
`create spacers on both sides of the P-channel gates.
`
`
`
`
`
`
`
`
`
`P-channel spacer formation is followed by a boron or
`
`
`
`
`
`boron-defluoride high-dosage unmasked implant, thus
`
`
`
`
`
`
`
`creating heavily-doped sources and drains for the P-
`
`
`
`
`
`
`
`channel devices. Since the dosage of the boron-difluo-
`
`
`
`
`
`
`
`ride implantis only approximately one-third to one-sev-
`
`
`
`
`
`
`
`
`
`
`enth the dosage of the arsenic implants used to create
`
`
`
`
`
`
`
`the source/drain regions for the N-channel devices,
`
`
`
`
`
`
`performance of the N-channel devices remains largely
`
`
`
`
`
`
`unaffected by the partial counter-doping of the N-chan-
`
`
`
`nel source/drain regions.
`A second embodiment of the invention allows P-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`channel transistor gates to be created by an isotropic
`
`
`
`
`
`
`
`
`
`
`dry etch with the fifth photomask in place. The fifth
`
`
`
`
`
`photomask patterns the P-channel transistor gates, and
`
`
`
`
`
`
`
`
`
`the isotropic dry etch produces gates,
`the edges of
`
`
`
`
`
`
`
`
`
`which are purposely undercut (recessed) under the
`
`
`
`
`
`
`
`
`
`patterning photoresist. After the etch, and with the fifth
`
`
`
`
`
`
`
`
`
`photomaskstill in place, a high-dosage boron or boron
`
`
`
`
`
`
`
`
`difluoride implant is used to create P-channel sources
`
`
`
`
`
`
`
`
`and drains. The undercut P-channel gate offsets the
`
`
`
`
`
`
`high-dosage P-channel source/drain implant such that
`
`
`
`
`
`implant diffusion related to subsequent
`temperature
`
`
`
`
`
`
`
`
`
`
`
`steps does not result in excessive gate overlap by these
`
`
`
`
`
`
`
`implants. Using only a single P-channel source/drain
`
`
`
`
`
`
`
`
`implant eliminates the problem of counter-doping of the
`
`
`
`
`
`
`N-channel source/drain regions, since all N-channel
`
`
`
`
`
`
`
`
`devices are protected by the fifth photomask. Removal
`
`
`
`
`
`
`
`
`of the fifth photomaskis followed by the blanket deposi-
`
`
`
`
`
`
`
`
`tion of a spacer oxide layer, which is anisotropically
`
`
`
`
`
`etched (and optionally subsequently isotropically
`
`
`
`
`
`
`
`
`
`
`etched) to create spacers on both sides of the P-channel
`
`gates.
`
`
`
`
`
`
`
`
`
`A layer of titanium metalis sputter deposited (sputter
`
`
`
`
`
`
`
`
`
`deposition is only one of several useable techniques) on
`
`
`
`
`
`
`
`
`top gfall the circuitry. A sintering step causes the tita-
`
`
`
`
`
`
`
`
`
`
`
`
`nium to react with all unoxidized silicon (i.e., all gates
`
`
`
`
`
`
`
`and source/drain regions for both N-channel and P-
`
`
`
`
`
`
`
`
`channeltransistors) to form titanium silicide. A sulfuric
`
`
`
`
`
`
`
`acid and hydrogen peroxide bath and a subsequent am-
`
`
`
`
`
`
`
`monium hydroxide and hydrogen peroxide bath remove
`
`Page 17 of 20
`
`
`
`
`
`
`
`20
`
`
`25
`
`
`30
`
`
`35
`
`
`40
`
`
`45
`
`
`
`
`
`
`
`
`65
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`6
`all unreacted titanium as well as titanium nitride. This
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`self-aligned siliciding step greating improves the speed
`of both N-channel and P-channel devices.
`
`
`
`
`
`
`
`
`
`
`
`
`
`At this point, transistor formation using the improved
`
`
`
`
`CMOSprocess is complete.
`
`
`
`
`
`
`
`
`
`Thesixth, seventh, and eighth photomasksare used to
`
`
`
`
`
`
`
`
`complete the circuitry in a conventional manner, and
`
`
`
`
`
`
`
`correspond respectively to the ninth, tenth, and elev-
`
`
`
`
`
`enth photomasks utilized for the previously-described
`
`
`conventional process.
`
`
`
`
`
`
`
`The improved CMOSprocess provides the following
`
`
`
`
`
`advantages over conventional process technology:
`
`
`
`
`
`
`
`
`
`It permits a dramatic reduction in the number of
`
`
`
`
`
`
`
`photomasking steps required in a modern high density
`
`
`
`CMOSprocess;
`
`
`
`
`
`
`
`
`
`It is applicable to both low and high density (sub-
`
`
`
`micron) integration levels;
`
`
`
`
`
`Use of a masked high-energy boron punchthrough
`
`
`
`
`
`
`
`
`implant for N-channel transistors is not required (a un-
`
`
`
`
`
`maskedself-aligned implant after polysilicon deposition
`
`
`
`is used instead);
`
`
`
`
`
`Individual optimization of N-channel and P-channel
`
`
`
`
`transistors is made possible;
`
`
`
`
`
`
`
`
`It allowslightly-doped drain (LDD) design for both
`
`
`
`
`
`
`
`N-channel and P-channel transistors (the LDD design
`
`
`
`
`
`
`
`
`makespossible a significant reduction in device length
`
`
`
`
`
`
`without incurring the detrimental “short channel” ef-
`
`
`
`
`
`
`
`fects seen with conventional transistor design, in addi-
`
`
`
`
`
`
`
`tion to greatly reducing high electric field hot-electron
`effects);
`,
`
`
`
`
`
`
`
`
`Offset distance of source/drain implants are easily
`
`
`
`
`
`
`changed independently for N-channel and P-channel
`
`
`
`
`
`
`devices, allowing greater flexibility for device optimiza-
`tion;
`
`The N-channel and P-channeltransistors can be inde-
`
`
`
`
`
`
`
`
`
`
`
`
`
`pendently controlled and optimized for best LDD per-
`
`
`
`
`
`
`
`formance and reliability (this fact allows maximum
`
`
`
`
`
`
`shrinkablity for subsequent generation products and
`
`
`
`
`
`
`
`reduces retooling for changes in N-channel or P-chan-
`
`
`nel transistors);
`
`
`
`
`
`It is compatible with contemporary IC fabrication
`
`
`
`equipment, and requires no exotic new equipment;
`
`
`
`
`
`
`Self-aligned siliciding of all transistor gates, sources
`
`
`
`
`
`
`
`
`
`
`
`
`and drains is accomplished without adding any masking
`
`
`steps; and
`
`
`
`
`
`
`
`
`The reduced number of process steps and reduced
`
`
`
`
`
`
`
`mask count
`improves electrical sort yields, reduces
`
`
`
`
`manufacturing costs,
`increases productivity, reduces
`
`
`
`
`
`
`
`
`cycle times through fabrication, reduces total process
`inventory needed for a given run rate, allows more
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`rapid response to process changesin volume quantities,
`
`
`
`
`
`
`
`
`and provides more products having less variation.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`
`
`
`
`
`
`
`
`
`
`
`The drawing Figures each show cross-sections of a
`
`
`portion of a semiconductorcircuit device whichutilizes
`
`
`
`
`
`
`
`
`the present invention.
`_
`
`
`
`
`
`FIG. 1 showsa lightly-doped P-type silicon substrate
`
`
`
`
`
`
`
`
`
`being implanted with phosphorus to create a well of
`
`
`
`
`
`
`
`
`
`N-type silicon following the growth ofa first layer of
`
`
`
`
`
`
`
`
`
`
`pad oxide, deposition of a first silicon nitride layer,
`
`
`
`masking of the first silicon nitride layer with a first
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`photoresist mask and etchingofthesilicon nitride layer;
`
`FIG. 2 shows the semiconductor device of FIG. 1
`
`
`
`
`
`
`
`
`
`
`
`being subjected to an optional P-type substrate boron
`
`
`
`
`
`
`
`
`
`
`
`
`
`adjustment implant following a high temperature step
`
`
`
`
`
`
`
`‘which has caused the N-well phosphorus implant to
`
`
`
`
`
`
`
`
`
`
`
`diffuse into the substrate, oxidation of silicon in the
`
`Page 17 of 20
`
`

`

`
`8
`
`7
`N-well region where it was unprotected by the first
`
`
`
`
`
`
`
`
`
`
`22 at the edge of masking layer 21 during the oxide
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`growth step. Following the stripping offirst silicon
`
`
`
`
`
`
`
`
`
`
`nitride layer to create an oxide mask, and stripping of
`
`
`
`
`
`
`
`
`
`nitride layer 13, the wafer is exposed to an optional
`
`
`
`
`the first nitride layer;
`FIG. 3 shows the semiconductor device of FIG. 2
`boron adjustment implant which optimizes the concen-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`tration of P-type chargecarriers in the substrate regions
`
`
`
`
`
`
`
`
`
`
`following thestripping of the oxide mask andfirst layer
`outside the N-well where N-channel devices will be
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`of pad oxide, growth of a second layer of pad oxide,
`
`
`
`
`
`
`
`
`created. Silicon dioxide masking layer 21 protects the
`
`
`
`
`
`
`
`
`deposition of a second layerofsilicon nitride and mask-
`
`
`
`
`
`
`
`N-well region from this boron adjustment
`implant.
`
`
`
`
`
`
`
`
`
`ing of the second silicon nitride layer with a second
`
`
`
`
`
`
`
`
`Next, the phosphorus atoms implanted in the N-well
`
`
`
`
`
`photomask to define active areas;
`FIG. 4 shows the semiconductor device of FIG. 3
`
`
`
`
`
`
`
`
`
`
`regions 15 and the boron atomsoutside the N-well from
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the optional adjustment implant are driven into the
`
`
`
`
`
`
`
`undergoing a field isolation boron implant with the
`
`
`
`
`
`
`
`
`
`
`
`
`substrate during a high-temperaturestep.
`N-well region masked with a third photomask follow-
`
`
`
`
`
`
`
`
`
`Referring now to FIG.3, following the stripping of
`
`
`
`
`
`
`
`
`ing an etch of the second nitride layer;
`FIG. 5 shows the semiconductor device of FIG. 4
`
`
`
`
`
`
`
`
`
`silicon dioxide masking layer 21 and first pad oxide
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`layer 11, a second pad oxide layer 31 is grown on the
`
`
`
`
`
`
`
`
`
`following the growth offield oxide using the LOCOS
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`surface of the entire wafer. This is followed by the
`process, stripping of the secondnitride layer, deposition
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`deposition of a secondsilicon nitride layer 32. A second
`of a polysilicon layer, masking of the poly layer with a
`
`
`
`
`
`
`
`
`photomask 33 defines active areas for both P-channel
`
`
`
`
`
`
`
`
`
`
`
`fourth photomask, and a first etch of the poly layer to
`
`
`
`
`
`
`
`
`
`devices (t