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`Global Foundaries US v. Godo Kaisha
`Global Ex. 1016
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`Page 1 of 9
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`

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`US. Patent
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`May 28, 1996
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`Sheet 1 of 5
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`5,521,422
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`——————SSS II
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`tr
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`FIG. tb
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`FIG. ta
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`FIG. tc
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`Page 2 of 9
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`U.S. Patent
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`May28, 1996
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`Sheet 2 of 5
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`5,521,422
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`After
`lsofropic
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`Etch
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`FIG. 2
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`PRIOR ART
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`Page 3 of 9
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`Page 3 of 9
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`U.S. Patent
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`May 28, 1996
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`Sheet 3 of 5
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`5,521,422
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`
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`14
`——
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`Is
`12
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`| | ‘
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`10
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`FIG. 3a
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`220
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`9
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`22a
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`FIG. 3e
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`Page 4 of 9
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`Page 4 of 9
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`U.S. Patent
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`May 28, 1996
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`Sheet 4 of 5
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`5,521,422
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`42
`11
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`°
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`10
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`FIG. 4a
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`FIG. 4b
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`22a
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`220
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`JS2b
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`Page 5 of 9
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`U.S. Patent
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`May28, 1996
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`Sheet 5 of 5
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`5,521,422
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`|YOLINGNODALVO
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`Page 6 of 9
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`5,521,422
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`1
`CORNER PROTECTED SHALLOW TRENCH
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`ISOLATION DEVICE
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`FIELD OF THE INVENTION
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`This invention relates generally to semiconductor struc-
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`tures having a trench isolation. More particularly, it relates
`to field effect transistor devices adjacent a corner of a trench
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`used for isolation and methods of avoiding corner parasitic
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`leakage cement.
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`10
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`BACKGROUND OF THE INVENTION
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`Contemporary CMOStechnologies employ field effect
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`transistors that are adjacent or bounded by trenches. The
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`trenches may provide isolation (shallow trench isolation, or
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`STI) or they may provide a location for semiconductor
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`devices, such as capacitors. Parasitic leakage paths have
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`been found because of the proximity of a semiconductor
`device to an edge or cornerof a trench.
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`In one mechanism, described in a paper, “Process and
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`Device Simulation of Trench Isolation Corner Parasitic
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`Device,” by T. Furukawa and J. A. Mandelman,published in
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`the Proceedings of the Electrochemical Society Meeting,
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`Oct. 9-14, 1988, the parasitic leakage path results from an
`enhancementofthe gate electric field near the trench corner.
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`Theelectric field is enhanced by the corner’s small radius of
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`curvature and the proximity of the gate conductor. Process-
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`ing can exacerbate the problem by sharpening the corner and
`thinning the gate dielectric near the corner. In addition, in a
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`worst case scenario for corner field enhancement, the gate
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`conductor wraps around the trench corner. This happens
`whenthe oxidefill in the isolation trench is recessed below
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`the silicon surface during oxide etches following its forma-
`tion.
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`As a result of the enhancedfield, the corner has a lower
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`threshold voltage (Vt) than the planar portion of the device.
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`Thus, a parallel path for current conduction is formed.
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`However, for device widths used in contemporary technolo-
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`gies, the top planar portion of the device carries mostof the
`on-current. Trench comer conduction is a parasitic which
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`usually contributes appreciably only to sub-threshold leak-
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`age. This parasitic leakage current along the corner is most
`easily seen as a humpin the subthreshold current curve of a
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`narrow MOSFET.
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`As mentioned in a paper, “The Current-Carrying Corner
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`Inherent to Trench Isolation,” by Andres Bryant, W. Haen-
`sch, S. Geissler, Jack Mandelman, D. Poindexter, and M.
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`Steger, published in the IEEE Electron Device Letters, Vol.
`14, No. 8, Aug., 1993, the corner device can even dominate
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`on-currents in applications such as DRAM that require
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`narrow channel widths to achieve high density. This parallel
`current-carrying corner device becomes the dominant MOS-
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`FET contributor to standby current in low standby power
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`logic applications and to leakage in DRAM cells. Further-
`more, there exists concern that the enhancedelectric fields
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`due to field crowding at the corer impactdielectric integ-
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`rity.
`A paper, “Behavior of an NMOSTrench-Isolated Corner
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`Parasitic Device at Low Temperature,” by D. Foty, J. Man-
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`delman, and T. Furukawa, published in the Proceedings of
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`the Electrochemical Society Meeting, October, 1989, sug-
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`gests that the corner parasitic device does not improve with
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`decreasing temperature nearly as much as the planar sub-
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`threshold slope. Thus, the corner parasitic device may be
`more ofa problem at low temperature than the planar device.
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`35
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`Page 7 of 9
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`This corner leakage problem has commonly been con-
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`trolled with an increased threshold tailor implant dose, but
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`this can degrade device performance. Thus, alternate
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`schemes for controlling the corner are needed.
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`A paper, “A Deep-Submicron Isolation Technology with
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`T-shaped Oxide (TSO) Structure,” by T. Ishijima et. al.,
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`Proceedings of the IEDM, 1990, p. 257, addresses the
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`problem of trench sidewall inversion. This paper teaches the
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`use ofa pair of aligned photomasksto form a T-shaped oxide
`adjacent the comet of an isolation trench and the use of a
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`channel stop boron implant along sidewalls of the trench.
`The structure moves the device away from the trench
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`sidewall and provides boron to raise the Vt along that
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`sidewall. However, isolation is enlarged when photomask
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`alignment tolerances are included in this two-mask-and-
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`implant scheme, making this solution undesirable. Thus, an
`improved meansto control the cornerparasitic is needed and
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`is provided by the following invention.
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`SUMMARYOF THE INVENTION
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`It is therefore an object of the present invention to avoid
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`comer leakage without degrading device performance.
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`It is another object of this invention to avoid recessing the
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`isolation insulator adjacent the corner.
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`It is another object of this invention to avoid corner
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`leakage and protect the isolation insulator without using
`device area.
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`It is another object of this invention to provide a self-
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`aligned scheme for avoiding corner leakage and protecting
`the isolation insulator.
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`These andother objects of the invention are accomplished
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`by providing a semiconductor structure comprising a semi-
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`conductor substrate having a planar surface. A trench having
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`a sidewall is provided in the substrate. An intersection of the
`trench and the surface forms a corner. A dielectric lines the
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`sidewall of the trench. And, a corner dielectric co-aligned
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`with the corner extends no more than a subminimum dimen-
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`sion distance over the substrate from the corner.
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`In one embodiment
`the corner dielectric is a spacer
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`self-aligned to the edge of the trench dielectric. In another
`embodiment, the corner dielectric is a spacer self-aligned to
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`the edge of a window in insulator used as a mask to form the
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`trench.
`In a third embodiment,
`this spacer defines the
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`position ofthe trench, but the spacer is then removed. When
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`the trench dielectric is later deposited, the trench dielectric
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`forms the corner dielectric in the space provided by the
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`removed spacerresulting in a unitary cap.
`Methodsof fabricating a semiconductor structure of the
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`invention comprise the steps of (a) providing a semiconduc-
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`tor substrate having a substantially planar surface; (b) form-
`ing a coating on the substrate; (c) forming a window in the
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`coating, the window having an edge; (d) forming a trench in
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`the substrate, the trench having a sidewall co-aligned to the
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`edge, an intersection of the trench and the surface forming
`a comer; (e) lining the sidewall and the edge with insulator;
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`and (f) forming a material on the substrate adjacent the
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`corner, the material extending around the trench parallel to
`the corner and extending no more than a subminimum
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`distance from the corner.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The foregoing and other objects, features, and advantages
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`of the invention will be apparent from the following detailed
`description of the invention, as illustrated in the accompa-
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`nying drawings, in which:
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`Page 7 of 9
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`5,521,422
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`3
`FIGS. la—1e are cross sectional views showingthe struc-
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`ture at several steps in the process for making a semicon-
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`ductor structure of a first embodiment of the present inven-
`tion;
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`FIG. 2 is a cross sectional view showing a structure
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`illustrating how gate wrap-around occurs with conventional
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`processing;
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`FIG. 3a—-3e are cross-sectional views showing the struc-
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`ture at several steps in the process for making a semicon-
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`ductor structure of the second embodiment of the present
`invention;
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`FIG. 4a—4c cross-sectional views showing the structure at
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`several steps in the process for making a semiconductor
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`structure of the third embodiment of the present invention;
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`FIG. 5 is cross-sectional view showing the structure of a
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`MOSFETadjacent an isolation of the present invention;
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`FIG. 6a is a simulation plot showing equipotential lines
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`for 2 MOSFET adjacent an isolation with conventional
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`geometry; and
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`FIG. 6b is a simulation plot showing equipotential lines
`for a MOSFETadjacent an isolation with the geometry of
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`the present invention.
`DETAILED DESCRIPTION OF THE
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`INVENTION
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`The present invention provides a self-aligned structure
`over the corner that eliminates a recess formed in an adjacent
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`insulator lined trench. Such trenches include shallow trench
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`isolation (STI) and deep trench capacitor. STI and processes
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`for forming STI are described in commonly assigned U.S.
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`Pat. No. 5,173,439, by Dashet. al., incorporated herein by
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`reference. By eliminating the recess in the insulator, the gate
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`wrap-around problem mentioned hereinaboveis eliminated.
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`The structure also offsets the gate conductor from the trench
`comer, further reducing the corner electric field. Several
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`embodiments are taught,
`including structures that avoid
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`narrowing the channel. The modified gate conductor geom-
`etry results in an electric field at the trench corner that is
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`actually lower than the field at the top planar region (see
`FIGS. 6a—6b). The result is a device which is free of the
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`above mentioned high cornerelectric field parasitic effects.
`In addition, applicants have found that, as a result of
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`increased cornerfield where the gate conductor overlapsthe
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`drain diffusion, gate induced drain leakage (GIDL)is sig-
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`nificantly increased. By eliminating the high field at the
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`the present invention also eliminates this GIDL
`comer,
`concern.
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`In one embodiment, illustrated in FIGS. la—le, a corner
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`dielectric is provided self-aligned to raised STI. The corner
`dielectric is a spacer that protects the STI corner from attack
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`by subsequent etches and that spaces a later formed FET
`away from the corner.
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`In theprocess,silicon substrate 10 is provided with a pad
`oxide 11 andnitride surface coating 12 as illustrated in FIG.
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`la. Window 13 with nearly vertical sidewall 14 is photo-
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`lithographically defined in surface coating 12 and oxide 11
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`as shown in FIG. 1b. Then trench 16 is etched, defined by
`window 13 as illustrated in FIG. 1c.
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`Trench 16 and window 13 are thenfilled with insulator18.
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`Insulator 18 is then polished, stopping on surface coating 12
`as illustrated in FIG. 1d. Then surface coating 12 is removed,
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`leaving insulator 18 with nearly vertical sidewalls 20
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`extending above the surface 21 ofsilicon substrate 10.
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`Spacer 22 is then provided self-aligned to sidewall 20 of
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`insulator 18 by the standard process of depositing a spacer
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`insulator having a desired thickness and directional etching
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`to selectively remove the spacer insulator from horizontal
`surfaces. The spacer insulator can be a material such as CVD
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`oxide, oxidized polysilicon, TEOS, silicon nitride, and
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`boron nitride. Spacer 22 protects the STI adjacent corner 24
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`during subsequent etches, preventing divoting and gate
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`wrap-around. Preferably, spacer 22 has a dimension that is
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`less than the minimum photolithographic dimension capable
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`of being formed by a particular process technology.
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`In a preferred embodiment,at least a portion of spacer 22
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`remains in place after subsequentetches, thereby also mov-
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`ing the gate controlled channelregion of a later formed FET
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`away from corer 24. Thus, high field effects including the
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`corner parasitic FET and GIDL at the drain diffusion are
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`eliminated. No additional photomasking is required for the
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`formation of spacers 22, a significant advantage over the
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`priorart.
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`Several experiments have been performed to confirm that
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`the RIE proposed for the spacer formation is not detrimental
`to device characteristics. Results indicate that flatband and
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`breakdowncharacteristics of silicon on which spacers have
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`been formed are not degraded.
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`FIG.2 illustrates a mechanism responsible for gate wrap-
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`around and showshowthe present invention eliminates this
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`problem. Divot 30 in insulator 18 in trench 16 adjacent
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`comer 24 arises during isotropic etches used in standard
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`semiconductor processing after trench 16 is filled with
`insulator 18. Divot 30 is formed adjacent corner 24 as a
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`result of the vertical and horizontal attack by etch ant on
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`insulator at comer 24. By providing a sufficiently thick
`spacer 22 over corner 24 (FIG. le), etchant cannot access
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`and form a recess or divot in insulator 18.
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`In a second embodiment, illustrated in FIGS. 3a—3e, a
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`cornerdielectric is also provided self-aligned to raised STI.
`The corner dielectric is again a spacer that protects the STI
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`comer from attack by subsequent etches and that spaces a
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`later formed FET away from the corner. But in this embodi-
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`ment the spacer is formed before the STI, it is inverted
`compared to the spacer of the first embodiment, andit is
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`formed within the minimum dimension space oftheisola-
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`tion. Thus, unlike the first embodiment presented herein-
`above, in this embodiment no device area is consumed by
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`the corner dielectric, a significant advantage. Furthermore,
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`in this embodiment, the RIE etching of the spacer does not
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`effect the device region.
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`In the process, silicon substrate 10 is again provided with
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`nitride surface coating 12. Window 13 with nearly vertical
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`sidewall 14 is again photolithographically defined in surface
`coating 12 as shown in FIG. 3a. In the next step, spacer 22a
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`is formed along sidewall 14 of coating 12. Then trench 16is
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`etched, defined by spacer 22a in window 13asillustrated in
`FIG. 1c. Then, as illustrated in FIG. 1d,
`trench 16 and
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`window 13 are filled with insulator 18. Insulator 18 is then
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`polished, stopping on surface coating 12. Then surface
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`coating 12 is removed, leaving insulator 18 with spacer 22a
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`extending above the surface 21 ofsilicon substrate 10.
`Aswith thefirst embodiment, spacer 22a protects the STI
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`adjacent comer 24 during subsequent etches, preventing
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`divoting and gate wrap-around. Similarly, at least a portion
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`of spacer 22a remains in place after subsequent etchsteps,
`moving a later formed FET away from corner 24. And no
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`additional photomasking is required for the formation of
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`spacer 22a. This embodiment has a significant advantage
`over the first embodiment
`in that spacer 22a is within
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`window 13, which can have a minimum dimension. Thus,
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`spacer 22a does not take up device area, an advantage
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`Page 8 of 9
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`Page 8 of 9
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`6
`duction and the GIDL concerns due to high cornerfields are
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`eliminated.
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`While several embodiments of the invention, together
`with modifications thereof, have been described in detail
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`herein and illustrated in the accompanying drawings, it will
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`be evident that various further modifications are possible
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`without departing from the scope of the invention. For
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`example, the trench need not be filled with insulator. The
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`insulator can be a thin lining along a sidewall or along the
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`top portion of the sidewall. The examples given are intended
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`only to beillustrative rather than exclusive and nothing in
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`the above specification is intended to limit the invention
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`more narrowly than the appended claims.
`Whatis claimedis:
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`1. A semiconductor structure comprising:
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`a semiconductor substrate having a planar surface;
`a trenchin said substrate, said trench having a sidewall, an
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`intersection of said trench and said surface forming a
`comer;
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`a comerdielectric co-aligned with said corner and extend-
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`ing over said surface; and
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`a field effect transistor having a channel having a current
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`path extending parallel
`to said corner, said channel
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`being spaced from said corner by said cornerdielectric.
`2. A semiconductor structure as recited in claim 1,
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`wherein said corner dielectric comprises a spacer.
`3. A semiconductorstructure as recited in claim 1 wherein
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`said corner dielectric comprises one of silicon dioxide,
`silicon nitride, and boron nitride.
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`4. A semiconductorstructure as recited in claim 1 wherein
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`said trench is a shallow trench isolation.
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`5. A semiconductorstructure as recited in claim 1, further
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`comprising an insulator in said trench, wherein said insula-
`tor fills said trench.
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`6. A semiconductorstructure as recited in claim 1, further
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`comprising an insulator in said trench, wherein said corner
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`dielectric and said insulator comprise the same material.
`7. A semiconductor structure as recited in claim 6,
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`wherein said corner dielectric and said trench dielectric are
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`a unitary structure.
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`8. A semiconductor structure as recited in claim 1, said
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`channel being defined bya gate, said gate being spaced from
`said corner by said corner dielectric.
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`9. A semiconductor structure as recited in claim 8, said
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`corner dielectric comprising a spacer.
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`10. A semiconductor structure as recited in claim 9,
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`further comprising an insulator in said trench, wherein said
`insulatorfills said trench.
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`oF
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`5,521,422
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`5
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`particularly for narrow devices such as DRAM cells. Trench
`16 can have a dimension that is a subminimum dimension.
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`In a third embodiment,
`illustrated in FIGS. 4a-4c, a
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`unitary structure having a cornerdielectric co-aligned with
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`the corner and extending a subminimum dimension distance
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`over the substrate from the corner is provided. In this case
`comerdielectric 22cis not itself a spacer butit fills the space
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`left when previously formed spacer 22a is removed. This
`embodiment differs from the second embodiment in that
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`spacer 22a of FIG. 3c is removed after trench 16 is etched
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`as illustrated in FIG. 4b. Then, insulator 18a is deposited to
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`fill both trench 16 and the space 22b left vacant by removed
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`spacer 22a. After polishing, coating 12 is removed leaving
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`a unitary raised STI structure having a subminimum dimen-
`sion corner dielectric 22c, as illustrated in FIG. 4c. In this
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`unitary structur, corner dielectric 22c and insulator 18a are
`formed of the same material. As with the second embodi-
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`ment, corner dielectric 22c does not take up device area.
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`Trench 16 can have a subminimum dimension while the
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`isolation as a whole 32 covers no more than a minimum
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`dimension. FIG. 4calso illustrates the formation of thermal
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`oxide layer 34 before deposition of insulator 18a, as is well
`knownin theart.
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`Asused in this application the phrase,“a cornerdielectric
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`co-aligned with the corner” meansthat the cornerdielectric
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`is aligned to an original edge to which the corneris also
`aligned (or either or both are aligned to an edge, such as a
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`spacer edge, derived from the original edge). Similarly, the
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`phrase “a trench having a sidewall co-aligned to an edge,”
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`means that the sidewall is aligned to an original edge to
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`which the edge is also aligned (or either or both are aligned
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`to an edge, such as a spacer edge, derived from the original
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`edge). Separate photolithography steps are avoided by using
`co-aligned structures; both structures are formed from a
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`single masking step aligned to the same mask edge.Little or
`no additional surface area is consumed compared to pro-
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`cesses requiring separate photolithography steps for both
`structures.
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`With any of the above embodiments, a MOSFETcan then
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`formed boundedby a comerdielectric rather than the corner
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`and sidewall of the STI. As illustrated in FIG. 5, gate
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`dielectric 38 is formed by conventional processing. Gate
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`conductor 40 is then deposited and photolithographically
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`defined. Gate conductor 40 is spaced from corner 24 by
`corer dielectric 22, 22a, or 22c. Thus, the electric field in
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`the comer region is significantly reduced.
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`Device modeling, illustrated in FIGS. 6a—6b, showsthat
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`the modified geometry described here results in a drastic
`reduction of the trench corerelectric field. Parasitic con-
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`10
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`15
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`20
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`25
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`30
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`35
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`40
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`45
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`Page 9 of 9
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`*
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`RF RO
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`Page 9 of 9
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